From: Jinqian Yang <yangjinqian1@huawei.com>
To: Thomas Gleixner <tglx@kernel.org>, <lpieralisi@kernel.org>,
<maz@kernel.org>, <alex@shazbot.org>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <liuyonglong@huawei.com>,
<wangzhou1@hisilicon.com>, <linuxarm@huawei.com>
Subject: Re: [RFC PATCH v2] irqchip/gic-v3-its: enable dynamic MSI-X allocation
Date: Mon, 13 Jul 2026 15:01:32 +0800 [thread overview]
Message-ID: <697a78bb-6cbf-4484-adfa-fdffe5bb0180@huawei.com> (raw)
In-Reply-To: <877bn1qn3p.ffs@fw13>
Hi,
On 2026/7/12 4:37, Thomas Gleixner wrote:
> On Sat, Jul 11 2026 at 10:20, Jinqian Yang wrote:
>> On ARM64 platforms with GICv3 ITS, VFIO PCI passthrough currently
>> cannot dynamically allocate MSI-X vectors after MSI-X has been
>> enabled. When QEMU needs to extend the vector range, it must
>> disable MSI-X, free all interrupts, then re-enable with a larger
>> allocation. This creates an interrupt loss window for already-active
>> vectors.
>>
>> Consider HNS3 with RoCE: NIC and RDMA share one PCI device and
>> ITS DeviceID, with MSI-X vectors partitioned as NIC (lower range)
>> then RoCE (starting at base_vector = num_nic_msi). In VFIO
>> passthrough, loading hns_roce after hns3 forces QEMU to tear down
>> all interrupts before re-allocating the larger range. During this
>> process, NIC interrupts may be lost. Testing confirmed that this
>> occasionally occurs, causing the network port reset to fail. This
>> appears to be unavoidable, as it's a standard approach adopted by
>> all network card vendors.
>>
>> On Hisilicon HIP09 (ARM64, GICv3/GICv4.1) with latest upstream kernel
>> and QEMU 8.2. VFIO passthrough of HNS3 NIC to VM: load both hns3 and
>> hns_roce_hw_v2 drivers and trigger FLR, this bug will occur occasionally.
>> After enabling dynamic MSIX allocation, this bug no longer occurs.
>>
>> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com>
>> ---
>> Changes in v2:
>> - Updated the commit message to add test information.
>
> Well, it contains test information, but it does not tell me _WHY_ this
> is safe to do, i.e. what makes gic-v3-its eligible to set this flag?
Yes, the commit message should explain this. The GICv3 ITS is eligible
because:
When set this flag, for the ITT, adding a new vector only inserts a new
entry, existing entries are untouched, so already-active vectors are
unaffected.
The ITT are sized to hwsize at MSI-X domain creation time. so there
is always sufficient space for any vector index that may be dynamiclly
allocated later. So the ITT never needs to be resized at runtime. The
dynamic allocation path(msi_domain_alloc_irq_at -> populate_alloc_info)
simply copies the pre-prepared alloc_data without re-invoking
msi_prepare(). Then picking a free EventID from the already-allocated
ITT and a free LPI form the already-reserved bitmap --- no existing
vector is affected.
I'll add this to the commit message in v3.
Thanks,
Jinqian
prev parent reply other threads:[~2026-07-13 7:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-11 2:20 [RFC PATCH v2] irqchip/gic-v3-its: enable dynamic MSI-X allocation Jinqian Yang
2026-07-11 7:04 ` Marc Zyngier
2026-07-11 20:37 ` Thomas Gleixner
2026-07-13 7:01 ` Jinqian Yang [this message]
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