Re: [PATCH v2 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY

[Christian Marangi <ansuelsmth@gmail.com>]

On Mon, Aug 31, 2026 at 08:51:46AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Aug 27, 2026 at 02:21:20PM +0200, Christian Marangi wrote:
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/phy/phy.h>
> > +
> > +    phy@1fc7f000 {
> > +        compatible = "airoha,an7583-pcie-gen3-phy";
> > +        reg = <0x1fc7f000 0xfff>,
> > +              <0x1fc7e000 0xfff>,
> 
> Sashiko has a valid point here.
> 
> This should reflect real hardware, not current driver. It is very, very
> unlikely that hardware designers designed a block of 0xfff size or 0x4
>

Hi for 0xfff yes the block is 0x1000 but I was reporting how it was defined
in the original DTS. For the 0x4 is for real a single register for that
usage. Documentation is scarce for that single block but this also reflect
the same implementation used on EN7581. I updated the example to address
the strange block of 0xfff.
 
> > +              <0x1fc30044 0x4>,
> > +              <0x1fc35030 0x4>;
> 

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