[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Tony Lindgren]

Hi all,

I've got some patches almost ready to go to merge the omap1
configs into a single omap1_defconfig. While working on getting
that done, I had to come up with a better solution for entry-armv.S
macros to detect the soc we're running on.

I suggest we add asm_irq_base and asm_irq_flags as in the first
patch in this series does. This way we can do the soc based detection
in init_irq or similar place. This might help also the multi-arm
work too.

Regards,

Tony

---

Tony Lindgren (4):
      ARM: Add asm_irq_base and asm_irq_flags for entry-armv.S macros
      omap2+: Use asm_irq_base for entry-macro.S
      omap1: Use asm_irq_flags for entry-macro.S
      omap1: Use get_irqnr_preamble


 arch/arm/include/asm/irq.h                     |    2 +
 arch/arm/kernel/entry-armv.S                   |   13 ++++++++
 arch/arm/mach-omap1/include/mach/entry-macro.S |   20 +++----------
 arch/arm/mach-omap1/irq.c                      |    4 +++
 arch/arm/mach-omap2/include/mach/entry-macro.S |   37 +++---------------------
 arch/arm/mach-omap2/io.c                       |   20 +++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h         |    2 +
 7 files changed, 49 insertions(+), 49 deletions(-)

-- 
Signature

[PATCH 1/4] ARM: Add asm_irq_base and asm_irq_flags for entry-armv.S macros

[Tony Lindgren]

This way we can use the SoC specific code to detect what we're
running on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/irq.h   |    2 ++
 arch/arm/kernel/entry-armv.S |   13 +++++++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 2721a58..2610c59 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -20,6 +20,8 @@
 #ifndef __ASSEMBLY__
 struct irqaction;
 struct pt_regs;
+extern void __iomem *asm_irq_base;
+extern unsigned int asm_irq_flags;
 extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c09e357..37cdb27 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -63,6 +63,19 @@
 
 	.endm
 
+/*
+ * Allow machine specific code to initialize asm_irq_base and asm_irq_flags
+ * for use in get_irqnr_preamble and get_irqnr_and_base macros
+ */
+	.pushsection .data
+	.globl	asm_irq_base
+asm_irq_base:
+	.long	0
+	.globl	asm_irq_flags
+asm_irq_flags:
+	.long	0
+	.popsection
+
 #ifdef CONFIG_KPROBES
 	.section	.kprobes.text,"ax",%progbits
 #else

[PATCH 2/4] omap2+: Use asm_irq_base for entry-macro.S

[Tony Lindgren]

This way we can use the generic omap SoC detection code instead.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/include/mach/entry-macro.S |   37 +++---------------------
 arch/arm/mach-omap2/io.c                       |   20 +++++++++++++
 2 files changed, 25 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1..c29728c 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -38,41 +38,14 @@
  */
 
 #ifdef MULTI_OMAP2
-		.pushsection .data
-omap_irq_base:	.word	0
-		.popsection
 
-		/* Configure the interrupt base on the first interrupt */
+		/*
+		 * Configure the interrupt base on the first interrupt.
+		 * See also omap_irq_base_init for setting asm_irq_base.
+		 */
 		.macro  get_irqnr_preamble, base, tmp
-9:
-		ldr	\base, =omap_irq_base	@ irq base address
+		ldr	\base, =asm_irq_base	@ irq base address
 		ldr	\base, [\base, #0]	@ irq base value
-		cmp	\base, #0		@ already configured?
-		bne	9997f			@ nothing to do
-
-		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
-		and	\tmp, \tmp, #0x000f0000	@ only check architecture
-		cmp	\tmp, #0x00070000	@ is v6?
-		beq	2400f			@ found v6 so it's omap24xx
-		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
-		and	\tmp, \tmp, #0x000000f0	@ check cortex 8 or 9
-		cmp	\tmp, #0x00000080	@ cortex A-8?
-		beq	3400f			@ found A-8 so it's omap34xx
-		cmp	\tmp, #0x00000090	@ cortex A-9?
-		beq	4400f			@ found A-9 so it's omap44xx
-2400:		ldr	\base, =OMAP2_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-3400:		ldr	\base, =OMAP3_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-4400:		ldr	\base, =OMAP4_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-9997:
 		.endm
 
 		/* Check the pending interrupts. Note that base already set */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a1939b1..7ac1d31 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -46,6 +46,7 @@
 #include "clockdomains.h"
 
 #include <plat/omap_hwmod.h>
+#include <plat/multi.h>
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -311,6 +312,23 @@ static int __init _omap2_init_reprogram_sdrc(void)
 	return v;
 }
 
+/*
+ * Initialize asm_irq_base for entry-macro.S
+ */
+static inline void omap_irq_base_init(void)
+{
+#ifdef MULTI_OMAP2
+	if (cpu_is_omap242x())
+		asm_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+	else if (cpu_is_omap34xx())
+		asm_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+	else if (cpu_is_omap44xx())
+		asm_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+	else
+		pr_err("Could not initialize asm_irq_base\n");
+#endif
+}
+
 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 				 struct omap_sdrc_params *sdrc_cs1)
 {
@@ -352,4 +370,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 		_omap2_init_reprogram_sdrc();
 	}
 	gpmc_init();
+
+	omap_irq_base_init();
 }

[PATCH 3/4] omap1: Use asm_irq_flags for entry-macro.S

[Tony Lindgren]

Initialize asm_irq_flags in omap_init_irq and use it in
get_irqnr_and_base to detect between omap7xx and omap15xx/16xx.

Note that both INT_1510_IH2_IRQ and INT_1510_IH2_IRQ are defined
as 0, so use INT_1510_IH2_IRQ for both of them.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap1/include/mach/entry-macro.S |   18 +++---------------
 arch/arm/mach-omap1/irq.c                      |    4 ++++
 arch/arm/plat-omap/include/plat/irqs.h         |    2 +-
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index df9060e..25b74f9 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -14,20 +14,6 @@
 #include <mach/irqs.h>
 #include <asm/hardware/gic.h>
 
-#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
-	(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-#define INT_IH2_IRQ		INT_7XX_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ		INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ		INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ		INT_1510_IH2_IRQ
-#endif
-
  		.macro	disable_fiq
 		.endm
 
@@ -47,9 +33,11 @@
 		beq	1510f
 
 		ldr	\irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+		ldr	\tmp, =asm_irq_flags	@ irq flags address
+		ldr	\tmp, [\tmp, #0]	@ irq flags value
 		cmp	\irqnr, #0
 		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-		cmpeq	\irqnr, #INT_IH2_IRQ
+		cmpeq	\irqnr, \tmp
 		ldreq	\base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
 		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
 		addeqs	\irqnr, \irqnr, #32
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index db913c3..e7f2166 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -180,22 +180,26 @@ void __init omap_init_irq(void)
 
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 	if (cpu_is_omap7xx()) {
+		asm_irq_flags = INT_7XX_IH2_IRQ;
 		irq_banks = omap7xx_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
 	}
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
 	if (cpu_is_omap1510()) {
+		asm_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap1510_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
 	}
 	if (cpu_is_omap310()) {
+		asm_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap310_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
 	}
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
 	if (cpu_is_omap16xx()) {
+		asm_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap1610_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
 	}
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 65e20a6..2910de9 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -77,7 +77,7 @@
 /*
  * OMAP-1610 specific IRQ numbers for interrupt handler 1
  */
-#define INT_1610_IH2_IRQ	0
+#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
 #define INT_1610_IH2_FIQ	2
 #define INT_1610_McBSP2_TX	4
 #define INT_1610_McBSP2_RX	5

[PATCH 4/4] omap1: Use get_irqnr_preamble

[Tony Lindgren]

This saves some cycles for multiple interrupts case.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap1/include/mach/entry-macro.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index 25b74f9..1bdcae1 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -18,13 +18,13 @@
 		.endm
 
 		.macro  get_irqnr_preamble, base, tmp
+		ldr	\base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
 		ldr	\irqnr, [\base, #IRQ_ITR_REG_OFFSET]
 		ldr	\tmp, [\base, #IRQ_MIR_REG_OFFSET]
 		mov	\irqstat, #0xffffffff

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Nicolas Pitre]

On Fri, 3 Dec 2010, Tony Lindgren wrote:

> Hi all,
> 
> I've got some patches almost ready to go to merge the omap1
> configs into a single omap1_defconfig. While working on getting
> that done, I had to come up with a better solution for entry-armv.S
> macros to detect the soc we're running on.
> 
> I suggest we add asm_irq_base and asm_irq_flags as in the first
> patch in this series does. This way we can do the soc based detection
> in init_irq or similar place. This might help also the multi-arm
> work too.

Did you see Eric Miao's patch series that introduces runtime IRQ demux 
handler support?

http://www.spinics.net/linux/lists/arm-kernel/msg92836.html

That is likely to be a better solution.


Nicolas

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Tony Lindgren]

* Nicolas Pitre <nico@fluxnic.net> [101203 21:39]:
> On Fri, 3 Dec 2010, Tony Lindgren wrote:
> 
> > Hi all,
> > 
> > I've got some patches almost ready to go to merge the omap1
> > configs into a single omap1_defconfig. While working on getting
> > that done, I had to come up with a better solution for entry-armv.S
> > macros to detect the soc we're running on.
> > 
> > I suggest we add asm_irq_base and asm_irq_flags as in the first
> > patch in this series does. This way we can do the soc based detection
> > in init_irq or similar place. This might help also the multi-arm
> > work too.
> 
> Did you see Eric Miao's patch series that introduces runtime IRQ demux 
> handler support?
> 
> http://www.spinics.net/linux/lists/arm-kernel/msg92836.html
> 
> That is likely to be a better solution.

Yeah that works too, although is a bit heavier for simple cases.

In the omap case just the irq base is different between omap2 vs omap3.
And only level2 interrupt bit is different omap7xx vs omap16xx.

Handling the difference between omap2/3 and omap4 would be the use
case for handle_arch_irq. Currently that too can be handled
without handle_arch_irq, but from multi-arm point of view
handle_arch_irq is needed in the long run.

I can do things either way quite easily for sure. But my preference
would be to have both options available. This is because asm_irq_base
and asm_irq_flags can be used to reduce 15 omap1 defconfigs into one
defconfig with quite minimal changes. And for omap2+, these patches
allow getting rid of the SoC detection code in entry-macro.S. Also,
after these patches, moving to use handle_arch_irq can be done a bit
easier later on.

Regards,

Tony

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Nicolas Pitre]

On Sat, 4 Dec 2010, Tony Lindgren wrote:

> * Nicolas Pitre <nico@fluxnic.net> [101203 21:39]:
> > On Fri, 3 Dec 2010, Tony Lindgren wrote:
> > 
> > > Hi all,
> > > 
> > > I've got some patches almost ready to go to merge the omap1
> > > configs into a single omap1_defconfig. While working on getting
> > > that done, I had to come up with a better solution for entry-armv.S
> > > macros to detect the soc we're running on.
> > > 
> > > I suggest we add asm_irq_base and asm_irq_flags as in the first
> > > patch in this series does. This way we can do the soc based detection
> > > in init_irq or similar place. This might help also the multi-arm
> > > work too.
> > 
> > Did you see Eric Miao's patch series that introduces runtime IRQ demux 
> > handler support?
> > 
> > http://www.spinics.net/linux/lists/arm-kernel/msg92836.html
> > 
> > That is likely to be a better solution.
> 
> Yeah that works too, although is a bit heavier for simple cases.
> 
> In the omap case just the irq base is different between omap2 vs omap3.
> And only level2 interrupt bit is different omap7xx vs omap16xx.
> 
> Handling the difference between omap2/3 and omap4 would be the use
> case for handle_arch_irq. Currently that too can be handled
> without handle_arch_irq, but from multi-arm point of view
> handle_arch_irq is needed in the long run.
> 
> I can do things either way quite easily for sure. But my preference
> would be to have both options available. This is because asm_irq_base
> and asm_irq_flags can be used to reduce 15 omap1 defconfigs into one
> defconfig with quite minimal changes. And for omap2+, these patches
> allow getting rid of the SoC detection code in entry-macro.S. Also,
> after these patches, moving to use handle_arch_irq can be done a bit
> easier later on.

My only problem with your approach is the global addition of 
asm_irq_base and asm_irq_flags in generic code which might not be useful 
and/or appropriate for all targets.  If you were confining them to some 
OMAP specific file then I wouldn't mind as much.  Looking at the patch I 
see that you had omap_irq_base before.  Why wasn't that sufficient?  
Only omap_irq_flags would be missing.


Nicolas

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Tony Lindgren]

* Nicolas Pitre <nico@fluxnic.net> [101204 18:26]:
> On Sat, 4 Dec 2010, Tony Lindgren wrote:
> 
> My only problem with your approach is the global addition of 
> asm_irq_base and asm_irq_flags in generic code which might not be useful 
> and/or appropriate for all targets.  If you were confining them to some 
> OMAP specific file then I wouldn't mind as much.  Looking at the patch I 
> see that you had omap_irq_base before.  Why wasn't that sufficient?  
> Only omap_irq_flags would be missing.

I guess I was thinking this is something that might help others
to build more machines into one defconfig. If that's not the case,
sure these can be kept omap specific.

After a quick browsing of the entry-macro.S files, looks like
there's some similar ifdeffery for get_irqnr_* macros that just might
be possible to clear out with asm_irq_base and asm_irq_flags:

arch/arm/mach-davinci/include/mach/entry-macro.S
arch/arm/mach-s5p64x0/include/mach/entry-macro.S
arch/arm/mach-ixp4xx/include/mach/entry-macro.S
arch/arm/mach-h720x/include/mach/entry-macro.S
arch/arm/plat-mxc/include/mach/entry-macro.S

Maybe let's wait a while to see if there are other use cases,
if not, I'll make them omap specific.

Regards,

Tony

[PATCH 0/4] Patches to make multi-soc handling in entry-armv.S easier

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [101204 19:00]:
> * Nicolas Pitre <nico@fluxnic.net> [101204 18:26]:
> > On Sat, 4 Dec 2010, Tony Lindgren wrote:
> > 
> > My only problem with your approach is the global addition of 
> > asm_irq_base and asm_irq_flags in generic code which might not be useful 
> > and/or appropriate for all targets.  If you were confining them to some 
> > OMAP specific file then I wouldn't mind as much.  Looking at the patch I 
> > see that you had omap_irq_base before.  Why wasn't that sufficient?  
> > Only omap_irq_flags would be missing.
> 
> I guess I was thinking this is something that might help others
> to build more machines into one defconfig. If that's not the case,
> sure these can be kept omap specific.
> 
> After a quick browsing of the entry-macro.S files, looks like
> there's some similar ifdeffery for get_irqnr_* macros that just might
> be possible to clear out with asm_irq_base and asm_irq_flags:
> 
> arch/arm/mach-davinci/include/mach/entry-macro.S
> arch/arm/mach-s5p64x0/include/mach/entry-macro.S
> arch/arm/mach-ixp4xx/include/mach/entry-macro.S
> arch/arm/mach-h720x/include/mach/entry-macro.S
> arch/arm/plat-mxc/include/mach/entry-macro.S
> 
> Maybe let's wait a while to see if there are other use cases,
> if not, I'll make them omap specific.

OK, no other people interested, will post the omap specific
versions as a reply to this message.

Regards,

Tony

[PATCH 1/3] omap1: Use asm_irq_flags for entry-macro.S

[Tony Lindgren]

Initialize asm_irq_flags in omap_init_irq and use it in
get_irqnr_and_base to detect between omap7xx and omap15xx/16xx.

Note that both INT_1510_IH2_IRQ and INT_1510_IH2_IRQ are defined
as 0, so use INT_1510_IH2_IRQ for both of them.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index df9060e..c9be6d4 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -14,18 +14,17 @@
 #include <mach/irqs.h>
 #include <asm/hardware/gic.h>
 
-#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
-	(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-#define INT_IH2_IRQ		INT_7XX_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ		INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ		INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ		INT_1510_IH2_IRQ
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_flags as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
+		.pushsection .data
+		.globl	omap_irq_flags
+omap_irq_flags:
+		.word	0
+		.popsection
 #endif
 
  		.macro	disable_fiq
@@ -47,9 +46,11 @@
 		beq	1510f
 
 		ldr	\irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+		ldr	\tmp, =omap_irq_flags	@ irq flags address
+		ldr	\tmp, [\tmp, #0]	@ irq flags value
 		cmp	\irqnr, #0
 		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-		cmpeq	\irqnr, #INT_IH2_IRQ
+		cmpeq	\irqnr, \tmp
 		ldreq	\base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
 		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
 		addeqs	\irqnr, \irqnr, #32
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index db913c3..6bddbc8 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = {
 
 void __init omap_init_irq(void)
 {
+	extern unsigned int omap_irq_flags;
 	int i, j;
 
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 	if (cpu_is_omap7xx()) {
+		omap_irq_flags = INT_7XX_IH2_IRQ;
 		irq_banks = omap7xx_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
 	}
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
 	if (cpu_is_omap1510()) {
+		omap_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap1510_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
 	}
 	if (cpu_is_omap310()) {
+		omap_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap310_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
 	}
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
 	if (cpu_is_omap16xx()) {
+		omap_irq_flags = INT_1510_IH2_IRQ;
 		irq_banks = omap1610_irq_banks;
 		irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
 	}
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 65e20a6..2910de9 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -77,7 +77,7 @@
 /*
  * OMAP-1610 specific IRQ numbers for interrupt handler 1
  */
-#define INT_1610_IH2_IRQ	0
+#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
 #define INT_1610_IH2_FIQ	2
 #define INT_1610_McBSP2_TX	4
 #define INT_1610_McBSP2_RX	5

[PATCH 1/3] omap1: Use asm_irq_flags for entry-macro.S

[Janusz Krzysztofik]

Wednesday 08 December 2010 02:47:28 Tony Lindgren napisa?(a):
> Initialize asm_irq_flags in omap_init_irq and use it in
> get_irqnr_and_base to detect between omap7xx and omap15xx/16xx.
>
> Note that both INT_1510_IH2_IRQ and INT_1510_IH2_IRQ are defined
> as 0, so use INT_1510_IH2_IRQ for both of them.

Tested on Amstrad Delta.

> Signed-off-by: Tony Lindgren <tony@atomide.com>

Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>

> diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S
> b/arch/arm/mach-omap1/include/mach/entry-macro.S index df9060e..c9be6d4
> 100644
> --- a/arch/arm/mach-omap1/include/mach/entry-macro.S
> +++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
> @@ -14,18 +14,17 @@
>  #include <mach/irqs.h>
>  #include <asm/hardware/gic.h>
>
> -#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
> -	(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
> -#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
> -#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
> -#define INT_IH2_IRQ		INT_7XX_IH2_IRQ
> -#elif defined(CONFIG_ARCH_OMAP15XX)
> -#define INT_IH2_IRQ		INT_1510_IH2_IRQ
> -#elif defined(CONFIG_ARCH_OMAP16XX)
> -#define INT_IH2_IRQ		INT_1610_IH2_IRQ
> -#else
> -#warning "IH2 IRQ defaulted"
> -#define INT_IH2_IRQ		INT_1510_IH2_IRQ
> +/*
> + * We use __glue to avoid errors with multiple definitions of
> + * .globl omap_irq_flags as it's included from entry-armv.S but not
> + * from entry-common.S.
> + */
> +#ifdef __glue
> +		.pushsection .data
> +		.globl	omap_irq_flags
> +omap_irq_flags:
> +		.word	0
> +		.popsection
>  #endif
>
>   		.macro	disable_fiq
> @@ -47,9 +46,11 @@
>  		beq	1510f
>
>  		ldr	\irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
> +		ldr	\tmp, =omap_irq_flags	@ irq flags address
> +		ldr	\tmp, [\tmp, #0]	@ irq flags value
>  		cmp	\irqnr, #0
>  		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
> -		cmpeq	\irqnr, #INT_IH2_IRQ
> +		cmpeq	\irqnr, \tmp
>  		ldreq	\base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
>  		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
>  		addeqs	\irqnr, \irqnr, #32
> diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
> index db913c3..6bddbc8 100644
> --- a/arch/arm/mach-omap1/irq.c
> +++ b/arch/arm/mach-omap1/irq.c
> @@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = {
>
>  void __init omap_init_irq(void)
>  {
> +	extern unsigned int omap_irq_flags;
>  	int i, j;
>
>  #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
>  	if (cpu_is_omap7xx()) {
> +		omap_irq_flags = INT_7XX_IH2_IRQ;
>  		irq_banks = omap7xx_irq_banks;
>  		irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
>  	}
>  #endif
>  #ifdef CONFIG_ARCH_OMAP15XX
>  	if (cpu_is_omap1510()) {
> +		omap_irq_flags = INT_1510_IH2_IRQ;
>  		irq_banks = omap1510_irq_banks;
>  		irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
>  	}
>  	if (cpu_is_omap310()) {
> +		omap_irq_flags = INT_1510_IH2_IRQ;
>  		irq_banks = omap310_irq_banks;
>  		irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
>  	}
>  #endif
>  #if defined(CONFIG_ARCH_OMAP16XX)
>  	if (cpu_is_omap16xx()) {
> +		omap_irq_flags = INT_1510_IH2_IRQ;
>  		irq_banks = omap1610_irq_banks;
>  		irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
>  	}
> diff --git a/arch/arm/plat-omap/include/plat/irqs.h
> b/arch/arm/plat-omap/include/plat/irqs.h index 65e20a6..2910de9 100644
> --- a/arch/arm/plat-omap/include/plat/irqs.h
> +++ b/arch/arm/plat-omap/include/plat/irqs.h
> @@ -77,7 +77,7 @@
>  /*
>   * OMAP-1610 specific IRQ numbers for interrupt handler 1
>   */
> -#define INT_1610_IH2_IRQ	0
> +#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
>  #define INT_1610_IH2_FIQ	2
>  #define INT_1610_McBSP2_TX	4
>  #define INT_1610_McBSP2_RX	5
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/3] omap1: Use asm_irq_flags for entry-macro.S

[Tony Lindgren]

* Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> [101210 08:06]:
> Wednesday 08 December 2010 02:47:28 Tony Lindgren napisa?(a):
> > Initialize asm_irq_flags in omap_init_irq and use it in
> > get_irqnr_and_base to detect between omap7xx and omap15xx/16xx.
> >
> > Note that both INT_1510_IH2_IRQ and INT_1510_IH2_IRQ are defined
> > as 0, so use INT_1510_IH2_IRQ for both of them.
> 
> Tested on Amstrad Delta.
> 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>

Thanks, merging these into omap-for-linus.

Regards,

Tony

[PATCH 2/3] omap1: Use get_irqnr_preamble

[Tony Lindgren]

This saves some cycles for multiple interrupts case.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index c9be6d4..584bf7b 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -31,13 +31,13 @@ omap_irq_flags:
 		.endm
 
 		.macro  get_irqnr_preamble, base, tmp
+		ldr	\base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
 		ldr	\irqnr, [\base, #IRQ_ITR_REG_OFFSET]
 		ldr	\tmp, [\base, #IRQ_MIR_REG_OFFSET]
 		mov	\irqstat, #0xffffffff

[PATCH 3/3] omap2+: Initialize omap_irq_base for entry-macro.S from platform code

[Tony Lindgren]

This way we can use the generic omap SoC detection code instead.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1..6032941 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -38,41 +38,27 @@
  */
 
 #ifdef MULTI_OMAP2
+
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_base as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
 		.pushsection .data
-omap_irq_base:	.word	0
+		.globl	omap_irq_base
+omap_irq_base:
+		.word	0
 		.popsection
+#endif
 
-		/* Configure the interrupt base on the first interrupt */
+		/*
+		 * Configure the interrupt base on the first interrupt.
+		 * See also omap_irq_base_init for setting omap_irq_base.
+		 */
 		.macro  get_irqnr_preamble, base, tmp
-9:
 		ldr	\base, =omap_irq_base	@ irq base address
 		ldr	\base, [\base, #0]	@ irq base value
-		cmp	\base, #0		@ already configured?
-		bne	9997f			@ nothing to do
-
-		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
-		and	\tmp, \tmp, #0x000f0000	@ only check architecture
-		cmp	\tmp, #0x00070000	@ is v6?
-		beq	2400f			@ found v6 so it's omap24xx
-		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
-		and	\tmp, \tmp, #0x000000f0	@ check cortex 8 or 9
-		cmp	\tmp, #0x00000080	@ cortex A-8?
-		beq	3400f			@ found A-8 so it's omap34xx
-		cmp	\tmp, #0x00000090	@ cortex A-9?
-		beq	4400f			@ found A-9 so it's omap44xx
-2400:		ldr	\base, =OMAP2_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-3400:		ldr	\base, =OMAP3_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-4400:		ldr	\base, =OMAP4_IRQ_BASE
-		ldr	\tmp, =omap_irq_base
-		str	\base, [\tmp, #0]
-		b	9b
-9997:
 		.endm
 
 		/* Check the pending interrupts. Note that base already set */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562dd..3d18349 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -46,6 +46,7 @@
 #include "clockdomains.h"
 
 #include <plat/omap_hwmod.h>
+#include <plat/multi.h>
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -311,6 +312,25 @@ static int __init _omap2_init_reprogram_sdrc(void)
 	return v;
 }
 
+/*
+ * Initialize asm_irq_base for entry-macro.S
+ */
+static inline void omap_irq_base_init(void)
+{
+	extern void __iomem *omap_irq_base;
+
+#ifdef MULTI_OMAP2
+	if (cpu_is_omap242x())
+		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+	else if (cpu_is_omap34xx())
+		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+	else if (cpu_is_omap44xx())
+		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+	else
+		pr_err("Could not initialize omap_irq_base\n");
+#endif
+}
+
 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 				 struct omap_sdrc_params *sdrc_cs1)
 {
@@ -352,4 +372,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 		_omap2_init_reprogram_sdrc();
 	}
 	gpmc_init();
+
+	omap_irq_base_init();
 }

[PATCH 3/3] omap2+: Initialize omap_irq_base for entry-macro.Sfrom platform code

[Rajendra Nayak]

Hi Tony,

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org
[mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf
> Of Tony Lindgren
> Sent: Wednesday, December 08, 2010 7:19 AM
> To: Nicolas Pitre
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: [PATCH 3/3] omap2+: Initialize omap_irq_base for
entry-macro.Sfrom platform code
>
> This way we can use the generic omap SoC detection code instead.
>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
>
> diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S
b/arch/arm/mach-omap2/include/mach/entry-macro.S
> index 06e64e1..6032941 100644
> --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> @@ -38,41 +38,27 @@
>   */
>
>  #ifdef MULTI_OMAP2
> +
> +/*
> + * We use __glue to avoid errors with multiple definitions of
> + * .globl omap_irq_base as it's included from entry-armv.S but not
> + * from entry-common.S.
> + */
> +#ifdef __glue
>  		.pushsection .data
> -omap_irq_base:	.word	0
> +		.globl	omap_irq_base
> +omap_irq_base:
> +		.word	0
>  		.popsection
> +#endif
>
> -		/* Configure the interrupt base on the first interrupt */
> +		/*
> +		 * Configure the interrupt base on the first interrupt.
> +		 * See also omap_irq_base_init for setting omap_irq_base.
> +		 */
>  		.macro  get_irqnr_preamble, base, tmp
> -9:
>  		ldr	\base, =omap_irq_base	@ irq base address
>  		ldr	\base, [\base, #0]	@ irq base value
> -		cmp	\base, #0		@ already configured?
> -		bne	9997f			@ nothing to do
> -
> -		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
> -		and	\tmp, \tmp, #0x000f0000	@ only check architecture
> -		cmp	\tmp, #0x00070000	@ is v6?
> -		beq	2400f			@ found v6 so it's
omap24xx
> -		mrc	p15, 0, \tmp, c0, c0, 0	@ get processor revision
> -		and	\tmp, \tmp, #0x000000f0	@ check cortex 8 or 9
> -		cmp	\tmp, #0x00000080	@ cortex A-8?
> -		beq	3400f			@ found A-8 so it's
omap34xx
> -		cmp	\tmp, #0x00000090	@ cortex A-9?
> -		beq	4400f			@ found A-9 so it's
omap44xx
> -2400:		ldr	\base, =OMAP2_IRQ_BASE
> -		ldr	\tmp, =omap_irq_base
> -		str	\base, [\tmp, #0]
> -		b	9b
> -3400:		ldr	\base, =OMAP3_IRQ_BASE
> -		ldr	\tmp, =omap_irq_base
> -		str	\base, [\tmp, #0]
> -		b	9b
> -4400:		ldr	\base, =OMAP4_IRQ_BASE
> -		ldr	\tmp, =omap_irq_base
> -		str	\base, [\tmp, #0]
> -		b	9b
> -9997:
>  		.endm
>
>  		/* Check the pending interrupts. Note that base already
set */
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 40562dd..3d18349 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -46,6 +46,7 @@
>  #include "clockdomains.h"
>
>  #include <plat/omap_hwmod.h>
> +#include <plat/multi.h>
>
>  /*
>   * The machine specific code may provide the extra mapping besides the
> @@ -311,6 +312,25 @@ static int __init _omap2_init_reprogram_sdrc(void)
>  	return v;
>  }
>
> +/*
> + * Initialize asm_irq_base for entry-macro.S
> + */
> +static inline void omap_irq_base_init(void)
> +{
> +	extern void __iomem *omap_irq_base;
> +
> +#ifdef MULTI_OMAP2
> +	if (cpu_is_omap242x())

Looks like this should be a cpu_is_omap24xx(). The
current master is broken on a 2430sdp and a git-bisect
pointed me to this patch.

Regards,
Rajendra

> +		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
> +	else if (cpu_is_omap34xx())
> +		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
> +	else if (cpu_is_omap44xx())
> +		omap_irq_base =
OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
> +	else
> +		pr_err("Could not initialize omap_irq_base\n");
> +#endif
> +}
> +
>  void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>  				 struct omap_sdrc_params *sdrc_cs1)
>  {
> @@ -352,4 +372,6 @@ void __init omap2_init_common_hw(struct
omap_sdrc_params *sdrc_cs0,
>  		_omap2_init_reprogram_sdrc();
>  	}
>  	gpmc_init();
> +
> +	omap_irq_base_init();
>  }
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/3] omap2+: Initialize omap_irq_base for entry-macro.Sfrom platform code

[Tony Lindgren]

* Rajendra Nayak <rnayak@ti.com> [101213 03:57]:
> >
> > +static inline void omap_irq_base_init(void)
> > +{
> > +	extern void __iomem *omap_irq_base;
> > +
> > +#ifdef MULTI_OMAP2
> > +	if (cpu_is_omap242x())
> 
> Looks like this should be a cpu_is_omap24xx(). The
> current master is broken on a 2430sdp and a git-bisect
> pointed me to this patch.

Thanks, just noticed that too. Here's a fix for that.

Regards,

Tony


From: Tony Lindgren <tony@atomide.com>
Date: Tue, 14 Dec 2010 19:17:31 -0800
Subject: [PATCH] omap: Fix setting omap_irq_base for 2430

We need to test for 24xx not 242x. Otherwise interrupts won't work.

Reported-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -320,7 +320,7 @@ static inline void omap_irq_base_init(void)
 	extern void __iomem *omap_irq_base;
 
 #ifdef MULTI_OMAP2
-	if (cpu_is_omap242x())
+	if (cpu_is_omap24xx())
 		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
 	else if (cpu_is_omap34xx())
 		omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);