[PATCH v5 net-next 0/2] Add multilink SERDES configuration support

[PATCH v5 net-next 0/2] Add multilink SERDES configuration support

[Gokul Praveen]

Add multilink SERDES configuration support on TI J784S4 SoC.

This patch series enables multilink SERDES configurations that require
different clock speeds for different links on TI J784S4 SoC.

For multilink SERDES configurations where the links require different
clock speeds (e.g., USXGMII+SGMII), all three clocks (refclk,
pll1_refclk, and phy_en_refclk) are needed. USXGMII requires a clock
speed of 156.25 MHz while SGMII requires 100 MHz. Since one reference
clock (refclk) alone cannot cater to these different clock speed
requirements, the second input reference clock (pll1_refclk) along with
phy_en_refclk is also needed.

Patch 1 updates the dt-bindings to support all three clocks by increasing
the maxItems to 3 and updating the clock-names parameter to allow both
pll1_refclk and phy_en_refclk to be used simultaneously.

Patch 2 adds the PLL1 refclk to the J784S4 SERDES nodes (SERDES0, SERDES1,
SERDES2, and SERDES4) as the assigned clocks parameter already references
PLL1 but the clocks parameter list was incomplete, causing multilink 
configuration failures.

Boot logs:
https://gist.github.com/GokulPraveen2001/7a09cc5ed0151d264f32cbbc31896605

Gokul Praveen (2):
  dt-bindings: phy: cadence-torrent: Update property values to support
    multilink SERDES configuration
  arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

 .../devicetree/bindings/phy/phy-cadence-torrent.yaml     | 3 ++-
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi               | 3 ++-
 3 files changed, 10 insertions(+), 5 deletions(-)

-- 
2.34.1

[PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Gokul Praveen]

Update the maxItems value of clocks parameter as 3 clocks
(refclk,pll1_refclk,phy_en_refclk) are supported.

Update the clock-names parameter to support mutilink SERDES configuration
as the existing enum configuration of the clock-names parameter does not
allow both pll1_refclk and phy_en_refclk to be used at the same time,
hence preventing the support for the configuration  (refclk,pll1_refclk,
phy_en_refclk), which is neeed for multilink SERDES usecases.

For multilink SERDES configurations where the links require different
clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
are needed.

For example,considering the USXGMII+SGMII multilink SERDES configuration
usecase, having only 1 reference clock(refclk) fails because USXGMII
requires a clock speed of 156.25 Mhz and SGMII protocol requires an
clock speed of 100 Mhz.

Since one reference clock(refclk) alone cannot cater to the 2
different clock speed requirements of these protocols, the second
input reference clock(pll1_refclk) along with phy_en_refclk
is also needed.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 9af39b33646a..ac0f625cd76d 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -34,7 +34,7 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     description:
       PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
       pll1_refclk is optional and used for multi-protocol configurations requiring
@@ -48,6 +48,7 @@ properties:
     items:
       - const: refclk
       - enum: [ pll1_refclk, phy_en_refclk ]
+      - const: phy_en_refclk
 
   reg:
     minItems: 1
-- 
2.34.1

[PATCH v5 net-next 2/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

[Gokul Praveen]

Add PLL1 refclk to "clocks" and "clock-names" parameter of SERDES0,
SERDES1,SERDES2 and SERDES4 node as "assigned clocks" parameter has PLL1
and serdes multilink configuration fails without PLL1.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi               | 3 ++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18..e5224bd7f538 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -1149,8 +1149,9 @@ serdes0: serdes@5060000 {
 			resets = <&serdes_wiz0 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
@@ -1186,8 +1187,9 @@ serdes1: serdes@5070000 {
 			resets = <&serdes_wiz1 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
@@ -1229,8 +1231,9 @@ serdes4: serdes@5050000 {
 			resets = <&serdes_wiz4 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 78fcd0c40abc..53109e2fe527 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -122,8 +122,9 @@ serdes2: serdes@5020000 {
 			resets = <&serdes_wiz2 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
-- 
2.34.1

Re: [PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Conor Dooley]

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On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
> Update the maxItems value of clocks parameter as 3 clocks
> (refclk,pll1_refclk,phy_en_refclk) are supported.
> 
> Update the clock-names parameter to support mutilink SERDES configuration
> as the existing enum configuration of the clock-names parameter does not
> allow both pll1_refclk and phy_en_refclk to be used at the same time,
> hence preventing the support for the configuration  (refclk,pll1_refclk,
> phy_en_refclk), which is neeed for multilink SERDES usecases.
> 
> For multilink SERDES configurations where the links require different
> clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
> are needed.
> 
> For example,considering the USXGMII+SGMII multilink SERDES configuration
> usecase, having only 1 reference clock(refclk) fails because USXGMII
> requires a clock speed of 156.25 Mhz and SGMII protocol requires an
> clock speed of 100 Mhz.
> 
> Since one reference clock(refclk) alone cannot cater to the 2
> different clock speed requirements of these protocols, the second
> input reference clock(pll1_refclk) along with phy_en_refclk
> is also needed.

This binding supports 2 devices and the generic compatible. Do all these
devices have the new refclk?

Thanks,
Conor.

> 
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
>  Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..ac0f625cd76d 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>        pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -48,6 +48,7 @@ properties:
>      items:
>        - const: refclk
>        - enum: [ pll1_refclk, phy_en_refclk ]
> +      - const: phy_en_refclk
>  
>    reg:
>      minItems: 1
> -- 
> 2.34.1
> 

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Re: [PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Praveen, Gokul]

Hi Conor,

On 08-07-2026 22:09, Conor Dooley wrote:
> On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
>> Update the maxItems value of clocks parameter as 3 clocks
>> (refclk,pll1_refclk,phy_en_refclk) are supported.
>>
>> Update the clock-names parameter to support mutilink SERDES configuration
>> as the existing enum configuration of the clock-names parameter does not
>> allow both pll1_refclk and phy_en_refclk to be used at the same time,
>> hence preventing the support for the configuration  (refclk,pll1_refclk,
>> phy_en_refclk), which is neeed for multilink SERDES usecases.
>>
>> For multilink SERDES configurations where the links require different
>> clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
>> are needed.
>>
>> For example,considering the USXGMII+SGMII multilink SERDES configuration
>> usecase, having only 1 reference clock(refclk) fails because USXGMII
>> requires a clock speed of 156.25 Mhz and SGMII protocol requires an
>> clock speed of 100 Mhz.
>>
>> Since one reference clock(refclk) alone cannot cater to the 2
>> different clock speed requirements of these protocols, the second
>> input reference clock(pll1_refclk) along with phy_en_refclk
>> is also needed.
> This binding supports 2 devices and the generic compatible. Do all these
> devices have the new refclk?

Not all of these devices have the new refclk(pll1_refclk), Conor, which 
is is why the enum was kept as it is and in these devices multilink 
serdes configuration will not be possible due to the limitation of not 
having the new refclk(pll1_refclk).

However, The intent of this patch is to add multilink serdes support for 
the devices which have the new refclk because the

earlier clock-names configuration could not support having all the 3 
clocks(refclk, pll1_refclk, phy_en_refclk) in the clock-names, which is 
needed for mutlilink serdes configuration configuration.

Also, Please feel free to ask if you have any other queries, Conor and 
thank you for this query .

Thanks and Best Regards

Gokul Praveen

> Thanks,
> Conor.
>
>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>> ---
>>   Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> index 9af39b33646a..ac0f625cd76d 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> @@ -34,7 +34,7 @@ properties:
>>   
>>     clocks:
>>       minItems: 1
>> -    maxItems: 2
>> +    maxItems: 3
>>       description:
>>         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>>         pll1_refclk is optional and used for multi-protocol configurations requiring
>> @@ -48,6 +48,7 @@ properties:
>>       items:
>>         - const: refclk
>>         - enum: [ pll1_refclk, phy_en_refclk ]
>> +      - const: phy_en_refclk
>>   
>>     reg:
>>       minItems: 1
>> -- 
>> 2.34.1
>>

Re: [PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Conor Dooley]

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On Thu, Jul 09, 2026 at 03:37:15PM +0530, Praveen, Gokul wrote:
> Hi Conor,
> 
> On 08-07-2026 22:09, Conor Dooley wrote:
> > On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
> > > Update the maxItems value of clocks parameter as 3 clocks
> > > (refclk,pll1_refclk,phy_en_refclk) are supported.
> > > 
> > > Update the clock-names parameter to support mutilink SERDES configuration
> > > as the existing enum configuration of the clock-names parameter does not
> > > allow both pll1_refclk and phy_en_refclk to be used at the same time,
> > > hence preventing the support for the configuration  (refclk,pll1_refclk,
> > > phy_en_refclk), which is neeed for multilink SERDES usecases.
> > > 
> > > For multilink SERDES configurations where the links require different
> > > clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
> > > are needed.
> > > 
> > > For example,considering the USXGMII+SGMII multilink SERDES configuration
> > > usecase, having only 1 reference clock(refclk) fails because USXGMII
> > > requires a clock speed of 156.25 Mhz and SGMII protocol requires an
> > > clock speed of 100 Mhz.
> > > 
> > > Since one reference clock(refclk) alone cannot cater to the 2
> > > different clock speed requirements of these protocols, the second
> > > input reference clock(pll1_refclk) along with phy_en_refclk
> > > is also needed.
> > This binding supports 2 devices and the generic compatible. Do all these
> > devices have the new refclk?
> 
> Not all of these devices have the new refclk(pll1_refclk), Conor, which is
> is why the enum was kept as it is and in these devices multilink serdes
> configuration will not be possible due to the limitation of not having the
> new refclk(pll1_refclk).

In that case, please restrict 3 clocks to only the devices which have
them.

pw-bot: changes-requested

Thanks,
Conor.

> 
> However, The intent of this patch is to add multilink serdes support for the
> devices which have the new refclk because the
> 
> earlier clock-names configuration could not support having all the 3
> clocks(refclk, pll1_refclk, phy_en_refclk) in the clock-names, which is
> needed for mutlilink serdes configuration configuration.
> 
> Also, Please feel free to ask if you have any other queries, Conor and thank
> you for this query .
> 
> Thanks and Best Regards
> 
> Gokul Praveen
> 
> > Thanks,
> > Conor.
> > 
> > > Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> > > ---
> > >   Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
> > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > index 9af39b33646a..ac0f625cd76d 100644
> > > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > @@ -34,7 +34,7 @@ properties:
> > >     clocks:
> > >       minItems: 1
> > > -    maxItems: 2
> > > +    maxItems: 3
> > >       description:
> > >         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
> > >         pll1_refclk is optional and used for multi-protocol configurations requiring
> > > @@ -48,6 +48,7 @@ properties:
> > >       items:
> > >         - const: refclk
> > >         - enum: [ pll1_refclk, phy_en_refclk ]
> > > +      - const: phy_en_refclk
> > >     reg:
> > >       minItems: 1
> > > -- 
> > > 2.34.1
> > > 

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Re: [PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Gokul Praveen]

Hi Conor,

On 09/07/26 21:21, Conor Dooley wrote:
> On Thu, Jul 09, 2026 at 03:37:15PM +0530, Praveen, Gokul wrote:
>> Hi Conor,
>>
>> On 08-07-2026 22:09, Conor Dooley wrote:
>>> On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
>>>> Update the maxItems value of clocks parameter as 3 clocks
>>>> (refclk,pll1_refclk,phy_en_refclk) are supported.
>>>>
>>>> Update the clock-names parameter to support mutilink SERDES configuration
>>>> as the existing enum configuration of the clock-names parameter does not
>>>> allow both pll1_refclk and phy_en_refclk to be used at the same time,
>>>> hence preventing the support for the configuration  (refclk,pll1_refclk,
>>>> phy_en_refclk), which is neeed for multilink SERDES usecases.
>>>>
>>>> For multilink SERDES configurations where the links require different
>>>> clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
>>>> are needed.
>>>>
>>>> For example,considering the USXGMII+SGMII multilink SERDES configuration
>>>> usecase, having only 1 reference clock(refclk) fails because USXGMII
>>>> requires a clock speed of 156.25 Mhz and SGMII protocol requires an
>>>> clock speed of 100 Mhz.
>>>>
>>>> Since one reference clock(refclk) alone cannot cater to the 2
>>>> different clock speed requirements of these protocols, the second
>>>> input reference clock(pll1_refclk) along with phy_en_refclk
>>>> is also needed.
>>> This binding supports 2 devices and the generic compatible. Do all these
>>> devices have the new refclk?
>> Not all of these devices have the new refclk(pll1_refclk), Conor, which is
>> is why the enum was kept as it is and in these devices multilink serdes
>> configuration will not be possible due to the limitation of not having the
>> new refclk(pll1_refclk).
> In that case, please restrict 3 clocks to only the devices which have
> them.
>
> pw-bot: changes-requested
>
> Thanks,
> Conor.
>
Apologies for my earlier message.

I confirmed that all of these devices(ie:2 devices and the generic 
compatible) support the 3 clocks.

It was a misinformation earlier from my side.Apologies for that.

Thanking you

Yours respectfully

Gokul Praveen

>> However, The intent of this patch is to add multilink serdes support for the
>> devices which have the new refclk because the
>>
>> earlier clock-names configuration could not support having all the 3
>> clocks(refclk, pll1_refclk, phy_en_refclk) in the clock-names, which is
>> needed for mutlilink serdes configuration configuration.
>>
>> Also, Please feel free to ask if you have any other queries, Conor and thank
>> you for this query .
>>
>> Thanks and Best Regards
>>
>> Gokul Praveen
>>
>>> Thanks,
>>> Conor.
>>>
>>>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>>>> ---
>>>>    Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>>> index 9af39b33646a..ac0f625cd76d 100644
>>>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>>> @@ -34,7 +34,7 @@ properties:
>>>>      clocks:
>>>>        minItems: 1
>>>> -    maxItems: 2
>>>> +    maxItems: 3
>>>>        description:
>>>>          PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>>>>          pll1_refclk is optional and used for multi-protocol configurations requiring
>>>> @@ -48,6 +48,7 @@ properties:
>>>>        items:
>>>>          - const: refclk
>>>>          - enum: [ pll1_refclk, phy_en_refclk ]
>>>> +      - const: phy_en_refclk
>>>>      reg:
>>>>        minItems: 1
>>>> -- 
>>>> 2.34.1
>>>>