From: Marc Zyngier <maz@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"oupton@kernel.org" <oupton@kernel.org>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>
Subject: Re: [PATCH v2 0/4] KVM: arm64: GICv5 KVM IRS review fixes
Date: Thu, 13 Aug 2026 16:01:04 +0100 [thread overview]
Message-ID: <861pc212vj.wl-maz@kernel.org> (raw)
In-Reply-To: <20260811150941.941295-1-sascha.bischoff@arm.com>
On Tue, 11 Aug 2026 16:09:46 +0100,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
>
> Hi all,
>
> v1 [1] combined irqchip and KVM fixes identified by Sashiko [2] while
> reviewing the GICv5 KVM IRS series [3]. Following feedback, v2 splits
> the fixes into separate irqchip and KVM postings. This posting
> contains the KVM fixes; the irqchip fixes are posted separately.
Reviewed-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2026-08-13 15:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 15:09 [PATCH v2 0/4] KVM: arm64: GICv5 KVM IRS review fixes Sascha Bischoff
2026-08-11 15:10 ` [PATCH v2 1/4] KVM: arm64: vgic: Free gic_kvm_info on initialization failure Sascha Bischoff
2026-08-12 13:14 ` Joey Gouly
2026-08-11 15:10 ` [PATCH v2 2/4] KVM: arm64: vgic: Prevent speculative SPI array underflow Sascha Bischoff
2026-08-12 13:43 ` Joey Gouly
2026-08-11 15:11 ` [PATCH v2 3/4] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs Sascha Bischoff
2026-08-12 12:56 ` Joey Gouly
2026-08-11 15:11 ` [PATCH v2 4/4] KVM: arm64: Validate GICv5 timer PPIs before claiming ownership Sascha Bischoff
2026-08-12 12:53 ` Joey Gouly
2026-08-13 15:01 ` Marc Zyngier [this message]
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