From: Marc Zyngier <maz@kernel.org>
To: Vincent Donnefort <vdonnefort@google.com>
Cc: oupton@kernel.org, kvmarm@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com,
seiden@linux.ibm.com, suzuki.poulose@arm.com,
yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org,
kernel-team@android.com, fuad.tabba@linux.dev,
stable@vger.kernel.org
Subject: Re: [PATCH v1] KVM: arm64: pkvm: Clear GICv3 LRs in the hypervisor
Date: Wed, 21 Oct 2026 13:22:28 +0100 [thread overview]
Message-ID: <86qzhjz1iz.wl-maz@kernel.org> (raw)
In-Reply-To: <20261021110000.508827-1-vdonnefort@google.com>
On Wed, 21 Oct 2026 12:00:00 +0100,
Vincent Donnefort <vdonnefort@google.com> wrote:
>
> The LR registers are architecturally UNKNOWN when the CPU boots or
> resumes. However, in protected mode, only the used ones are reset.
> During boot the HVC __vgic_v3_init_lrs() is never called because
> vgic_present is only set in init_subsystems(), after cpu_hyp_init() was
> called.
Why don't you fix this rather than making the init even more
different?
> Also, the PM notifier isn't registered for pKVM and the HVC
> becomes unavailable after the host is deprivileged.
Sanitising the LRs on PSCI_ON is probably the right thing to do, but I
don't understand why resetting the LRs is out of reach from the host,
given that the host is fully in charge of the interrupt injection, and
therefore controls the LRs.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2026-10-21 12:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 11:00 [PATCH v1] KVM: arm64: pkvm: Clear GICv3 LRs in the hypervisor Vincent Donnefort
2026-10-21 12:12 ` Fuad Tabba
2026-10-21 12:22 ` Marc Zyngier [this message]
2026-10-21 12:50 ` Vincent Donnefort
2026-10-21 13:25 ` Marc Zyngier
2026-10-21 15:14 ` Vincent Donnefort
2026-10-21 15:37 ` Marc Zyngier
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