[PATCH 0/2] MediaTek MT8195 HDMI PHY Fixes

[PATCH 0/2] MediaTek MT8195 HDMI PHY Fixes

[AngeloGioacchino Del Regno]

This series adds two fixes for the MT8195-class HDMI PHY, found in
MT8195, MT8188 and Genio variants.

This is fixing PLL calculation, and TMDS clock dividers, to achieve
all of the modes requiring data rates higher than 3.4Gbps, with the
successfully tested target being 3840x2160@60Hz.

This was tested on MT8395 MediaTek Genio 1200, Radxa NIO-12L and on
MT8390 MediaTek Genio 700, with 3 different HDMI displays (two TVs
and a 4k LG workstation display).

AngeloGioacchino Del Regno (2):
  phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow
  phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

-- 
2.54.0

[PATCH 1/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow

[AngeloGioacchino Del Regno]

When trying to calculate a PLL rate for target display resolutions
above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more
than 32-bits long but the division to finally calculate the digital
clock divider is being done with div_u64(), which expects a 32bit
unsigned divisor.

Fix the overflow by using div64_u64() instead.

Fixes: 9d9ff3d2a4a5 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index 1426a2db984d..e6ee8e080022 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -290,7 +290,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
 	posdiv2 = 1;
 
 	/* Digital clk divider, max /32 */
-	digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk);
+	digital_div = div64_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk);
 	if (!(digital_div <= 32 && digital_div >= 1))
 		return -EINVAL;
 
-- 
2.54.0

Re: [PATCH 1/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow

[Manivannan Sadhasivam]

On Wed, Jul 01, 2026 at 02:19:35PM +0200, AngeloGioacchino Del Regno wrote:
> When trying to calculate a PLL rate for target display resolutions
> above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more
> than 32-bits long but the division to finally calculate the digital
> clock divider is being done with div_u64(), which expects a 32bit
> unsigned divisor.
> 
> Fix the overflow by using div64_u64() instead.
> 
> Fixes: 9d9ff3d2a4a5 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[AngeloGioacchino Del Regno]

The comment in the mtk_phy_tmds_clk_ratio() function clearly and
correctly explains that the TMDS ratio has to be 1/10 for data
rates under 3.4Gbps, and 1/40 over that.

Unfortunately though, the TXC_DIV register setting was wrong, as
in value 3 means to divide by 8 and, in order to achieve the in
spec 1/40 (tmds) data rate, this has to divide by 4 instead!
In order to achieve the correct 1/40 (tmds) data rate, this has

Add definitions for the TXC_DIV register values clearly explaining
the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
value to the register in mtk_phy_tmds_clk_ratio().

This fixes out of spec clocking and, with this change, SoCs using
the MT8195 class HDMI PHYs can now successfully be configured to
output 3840x2160@60Hz over HDMI.

Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 +-
 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index e6ee8e080022..a4bc1268946d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -36,7 +36,7 @@ mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable)
 	 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10
 	 */
 	if (enable)
-		mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3);
+		mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, VAL_TXC_DIV4);
 	else
 		mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV);
 }
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
index e26caaf4d104..58800d7659ca 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
@@ -17,6 +17,9 @@
 
 #define HDMI20_CLK_CFG 0x70
 #define REG_TXC_DIV GENMASK(31, 30)
+#define VAL_TXC_DIV2 1
+#define VAL_TXC_DIV4 2
+#define VAL_TXC_DIV8 3
 
 #define HDMI_1_CFG_0 0x00
 #define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5)
-- 
2.54.0

Re: [PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[Manivannan Sadhasivam]

On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
> The comment in the mtk_phy_tmds_clk_ratio() function clearly and
> correctly explains that the TMDS ratio has to be 1/10 for data
> rates under 3.4Gbps, and 1/40 over that.
> 
> Unfortunately though, the TXC_DIV register setting was wrong, as
> in value 3 means to divide by 8 and, in order to achieve the in
> spec 1/40 (tmds) data rate, this has to divide by 4 instead!
> In order to achieve the correct 1/40 (tmds) data rate, this has

This statement is cut-off!

> 
> Add definitions for the TXC_DIV register values clearly explaining
> the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
> value to the register in mtk_phy_tmds_clk_ratio().
> 
> This fixes out of spec clocking and, with this change, SoCs using
> the MT8195 class HDMI PHYs can now successfully be configured to
> output 3840x2160@60Hz over HDMI.
> 
> Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

With above comment addressed,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[AngeloGioacchino Del Regno]

On 9/9/26 17:06, Manivannan Sadhasivam wrote:
> On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
>> The comment in the mtk_phy_tmds_clk_ratio() function clearly and
>> correctly explains that the TMDS ratio has to be 1/10 for data
>> rates under 3.4Gbps, and 1/40 over that.
>>
>> Unfortunately though, the TXC_DIV register setting was wrong, as
>> in value 3 means to divide by 8 and, in order to achieve the in
>> spec 1/40 (tmds) data rate, this has to divide by 4 instead!
>> In order to achieve the correct 1/40 (tmds) data rate, this has
> 
> This statement is cut-off!
> 

Oh oops. It's just a forgotten line that has to be removed....

Should I resend or can you simply remove the line
"In order to achieve the correct 1/40 (tmds) data rate, this has"
while applying?

Thanks,
Angelo

>>
>> Add definitions for the TXC_DIV register values clearly explaining
>> the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
>> value to the register in mtk_phy_tmds_clk_ratio().
>>
>> This fixes out of spec clocking and, with this change, SoCs using
>> the MT8195 class HDMI PHYs can now successfully be configured to
>> output 3840x2160@60Hz over HDMI.
>>
>> Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> With above comment addressed,
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> 
> - Mani
> 

Re: [PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[Manivannan Sadhasivam]

On Thu, Sep 10, 2026 at 10:39:06AM +0200, AngeloGioacchino Del Regno wrote:
> On 9/9/26 17:06, Manivannan Sadhasivam wrote:
> > On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
> > > The comment in the mtk_phy_tmds_clk_ratio() function clearly and
> > > correctly explains that the TMDS ratio has to be 1/10 for data
> > > rates under 3.4Gbps, and 1/40 over that.
> > > 
> > > Unfortunately though, the TXC_DIV register setting was wrong, as
> > > in value 3 means to divide by 8 and, in order to achieve the in
> > > spec 1/40 (tmds) data rate, this has to divide by 4 instead!
> > > In order to achieve the correct 1/40 (tmds) data rate, this has
> > 
> > This statement is cut-off!
> > 
> 
> Oh oops. It's just a forgotten line that has to be removed....
> 
> Should I resend or can you simply remove the line
> "In order to achieve the correct 1/40 (tmds) data rate, this has"
> while applying?
> 

I do not apply the patches, only Vinod does. It would help if you can just
send a next version with this change and tags.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[AngeloGioacchino Del Regno]

On 9/11/26 07:11, Manivannan Sadhasivam wrote:
> On Thu, Sep 10, 2026 at 10:39:06AM +0200, AngeloGioacchino Del Regno wrote:
>> On 9/9/26 17:06, Manivannan Sadhasivam wrote:
>>> On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
>>>> The comment in the mtk_phy_tmds_clk_ratio() function clearly and
>>>> correctly explains that the TMDS ratio has to be 1/10 for data
>>>> rates under 3.4Gbps, and 1/40 over that.
>>>>
>>>> Unfortunately though, the TXC_DIV register setting was wrong, as
>>>> in value 3 means to divide by 8 and, in order to achieve the in
>>>> spec 1/40 (tmds) data rate, this has to divide by 4 instead!
>>>> In order to achieve the correct 1/40 (tmds) data rate, this has
>>>
>>> This statement is cut-off!
>>>
>>
>> Oh oops. It's just a forgotten line that has to be removed....
>>
>> Should I resend or can you simply remove the line
>> "In order to achieve the correct 1/40 (tmds) data rate, this has"
>> while applying?
>>
> 
> I do not apply the patches, only Vinod does. It would help if you can just
> send a next version with this change and tags.
> 
> - Mani
> 

Sure, will send v2 in a jiffy.

Cheers,
Angelo

Re: [PATCH 0/2] MediaTek MT8195 HDMI PHY Fixes

[AngeloGioacchino Del Regno]

On 7/1/26 14:19, AngeloGioacchino Del Regno wrote:
> This series adds two fixes for the MT8195-class HDMI PHY, found in
> MT8195, MT8188 and Genio variants.
> 
> This is fixing PLL calculation, and TMDS clock dividers, to achieve
> all of the modes requiring data rates higher than 3.4Gbps, with the
> successfully tested target being 3840x2160@60Hz.
> 
> This was tested on MT8395 MediaTek Genio 1200, Radxa NIO-12L and on
> MT8390 MediaTek Genio 700, with 3 different HDMI displays (two TVs
> and a 4k LG workstation display).
> 
> AngeloGioacchino Del Regno (2):
>    phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow
>    phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting
> 
>   drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++--
>   drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 3 +++
>   2 files changed, 5 insertions(+), 2 deletions(-)
> 

This series * performing fixes * got completely ignored.

PHY maintainers, ping.

Cheers,
Angelo