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From: "Yingchao Deng (Consultant)" <quic_yingdeng@quicinc.com>
To: Yingchao Deng <yingchao.deng@oss.qualcomm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@arm.com>,
	James Clark <james.clark@linaro.org>, Leo Yan <leo.yan@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <coresight@lists.linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
	Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
	Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
	Jie Gan <jie.gan@oss.qualcomm.com>,
	Yingchao Deng <quic_yingdeng@quicinc.com>
Subject: Re: [PATCH v7 0/4] Add Qualcomm extended CTI support
Date: Wed, 15 Apr 2026 11:22:49 +0800	[thread overview]
Message-ID: <9772e300-06cb-4892-810c-bdcf6251bf9f@quicinc.com> (raw)
In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com>


On 3/25/2026 1:43 PM, Yingchao Deng wrote:
> The Qualcomm extended CTI is a heavily parameterized version of ARM’s
> CSCTI. It allows a debugger to send to trigger events to a processor or to
> send a trigger event to one or more processors when a trigger event occurs
> on another processor on the same SoC, or even between SoCs.
>
> Qualcomm extended CTI supports up to 128 triggers. And some of the register
> offsets are changed.
>
> The commands to configure CTI triggers are the same as ARM's CTI.
>
> Prerequisites:
>     This series depends on the following CoreSight fix:
>     [PATCH v2 1/1] coresight: fix issue where coresight component has no claimtags
> Link: https://lore.kernel.org/all/20251027223545.2801-2-mike.leach@linaro.org/
>
> Changes in v7:
> 1. Split the extended CTI support into smaller, logically independent
>     patches to improve reviewability.
> 2. Removed the dual offset-array based register access used in v6 for
>     standard and Qualcomm CTIs. Register addressing is now unified through
>     a single code path by encoding the register index together with the base
>     offset and applying variant-specific translation at the final MMIO
>     access point.
> 3. Removed ext_reg_sel, extend the CTI sysfs interface to expose banked
>     register instances on Qualcomm CTIs only. Numbered sysfs nodes are
>     hidden on standard ARM CTIs, and on Qualcomm CTIs their visibility is
>     derived from nr_trig_max (32 triggers per bank), ensuring that only
>     registers backed by hardware are exposed.
> Link to v6 - https://lore.kernel.org/all/20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com/
>
> Changes in v6:
> 1. Rename regs_idx to ext_reg_sel and add information in documentation
>     file.
> 2. Reset CLAIMSET to zero for qcom-cti during probe.
> 3. Retrieve idx value under spinlock.
> 4. Use yearless copyright for qcom-cti.h.
> Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/
>
> Changes in v5:
> 1. Move common part in qcom-cti.h to coresight-cti.h.
> 2. Convert trigger usage fields to dynamic bitmaps and arrays.
> 3. Fix holes in struct cti_config to save some space.
> 4. Revert the previous changes related to the claim tag in
>     cti_enable/disable_hw.
> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/
>
> Changes in v4:
> 1. Read the DEVARCH registers to identify Qualcomm CTI.
> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
> coresight_cti_reg_store() functions accordingly.
> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/
>
> Changes in v3:
> 1. Rename is_extended_cti() to of_is_extended_cti().
> 2. Add the missing 'i' when write the CTI trigger registers.
> 3. Convert the multi-line output in sysfs to single line.
> 4. Initialize offset arrays using designated initializer.
> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/
>
> Changes in V2:
> 1. Add enum for compatible items.
> 2. Move offset arrays to coresight-cti-core
>
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
> Yingchao Deng (4):
>        coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
>        coresight: cti: encode trigger register index in register offsets
>        coresight: cti: add Qualcomm extended CTI identification and quirks
>        coresight: cti: expose banked sysfs registers for Qualcomm extended CTI
>
>   drivers/hwtracing/coresight/coresight-cti-core.c   | 114 ++++++++++++++++-----
>   .../hwtracing/coresight/coresight-cti-platform.c   |  16 +--
>   drivers/hwtracing/coresight/coresight-cti-sysfs.c  |  75 ++++++++++++--
>   drivers/hwtracing/coresight/coresight-cti.h        |  30 ++++--
>   drivers/hwtracing/coresight/qcom-cti.h             |  65 ++++++++++++
>   5 files changed, 247 insertions(+), 53 deletions(-)
> ---
> base-commit: 5bca1f031b65a4a8caf700537cbbc770252af475
> change-id: 20260324-extended_cti-707638ceee9e
>
> Best regards,

Gentle reminder.

thanks,
Yingchao.



  parent reply	other threads:[~2026-04-15  3:23 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-25  5:43 [PATCH v7 0/4] Add Qualcomm extended CTI support Yingchao Deng
2026-03-25  5:43 ` [PATCH v7 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays Yingchao Deng
2026-03-25  5:43 ` [PATCH v7 2/4] coresight: cti: encode trigger register index in register offsets Yingchao Deng
2026-03-25  5:43 ` [PATCH v7 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks Yingchao Deng
2026-03-25  5:43 ` [PATCH v7 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Yingchao Deng
2026-04-15  3:22 ` Yingchao Deng (Consultant) [this message]
2026-04-15  8:05   ` [PATCH v7 0/4] Add Qualcomm extended CTI support Leo Yan

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