From: Gang Li <ligang.bdlg@bytedance.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
Feiyang Chen <chenfeiyang@loongson.cn>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [QUESTION FOR ARM64 TLB] performance issue and implementation difference of TLB flush
Date: Sat, 6 May 2023 10:51:23 +0800 [thread overview]
Message-ID: <9d976db8-b800-ad84-9c67-0afb942934d9@bytedance.com> (raw)
In-Reply-To: <369d1be2-d418-1bfb-bfc2-b25e4e542d76@bytedance.com>
Hi,
On 2023/4/28 17:27, Mark Rutland wrote:> The architecture allows a CPU
to allocate TLB entries at any time for any
> reason, for any valid translation table entries reachable from the
> root in
> TTBR{0,1}_ELx. That can be due to speculation, prefetching, and/or other
> reasons.
>
TLB will be allocated due to prefetching or branch prediction. Will it
be invalidated when the prediction fails?
> Due to that, it doesn't matter whether or not a CPU explicitly accesses a
> memory location -- TLB entries can be allocated regardless.
> Consequently, the
> spinlock doesn't make any difference.
>
And is there any kind of ARM manual or guide that
explains these details to help us programming better?
Thanks a lot for your help.
Gang Li
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next prev parent reply other threads:[~2023-05-06 2:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 3:26 [QUESTION FOR ARM64 TLB] performance issue and implementation difference of TLB flush Gang Li
2023-04-27 7:30 ` Mark Rutland
2023-05-05 9:48 ` Gang Li
2023-05-05 12:28 ` Gang Li
2023-05-16 3:16 ` Gang Li
2023-05-06 2:51 ` Gang Li [this message]
[not found] ` <ZFpZAGeEXomG/eKS@FVFF77S0Q05N.cambridge.arm.com>
2023-05-16 7:47 ` Gang Li
2023-05-16 11:51 ` Mark Rutland
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