* Re: [PATCH v9 1/8] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE
From: Chris Packham @ 2019-08-26 0:46 UTC (permalink / raw)
To: linux@armlinux.org.uk
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
jlu@pengutronix.de, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
james.morse@arm.com, gregory.clement@free-electrons.com,
bp@alien8.de, mchehab@kernel.org,
linux-arm-kernel@lists.infradead.org, patches@armlinux.org.uk
In-Reply-To: <20190823105020.GZ13294@shell.armlinux.org.uk>
Hi Russell,
On Fri, 2019-08-23 at 11:50 +0100, Russell King - ARM Linux admin
wrote:
> On Fri, Aug 23, 2019 at 11:46:21AM +0100, Russell King - ARM Linux
> admin wrote:
> > On Fri, Jul 12, 2019 at 03:48:57PM +1200, Chris Packham wrote:
> > > From: Jan Luebbe <jlu@pengutronix.de>
> > >
> > > The macro name is too generic, so add a AURORA_ prefix.
> > >
> > > Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > > ---
> > > arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
> >
> > I can't apply this series - this file does not exist in my tree,
> > and
> > from what git tells me, it never has existed. Maybe it's in
> > someone
> > elses tree?
>
> I think the file is in my tree, just as arch/arm/mm/cache-aurora-l2.h
> which is where it has been since it was originally submitted in 2012.
>
Sorry there is a missing patch that moves it next to the
hardware/cache-*.h. I can send the missing patch or I can re-send the
whole series. If I do send the whole series do you want me to rebase it
against a particular tag/tree?
> >
> > > arch/arm/mm/cache-l2x0.c | 4 ++--
> > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h
> > > b/arch/arm/include/asm/hardware/cache-aurora-l2.h
> > > index c86124769831..dc5c479ec4c3 100644
> > > --- a/arch/arm/include/asm/hardware/cache-aurora-l2.h
> > > +++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
> > > @@ -41,7 +41,7 @@
> > > #define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
> > > (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
> > >
> > > -#define MAX_RANGE_SIZE 1024
> > > +#define AURORA_MAX_RANGE_SIZE 1024
> > >
> > > #define AURORA_WAY_SIZE_SHIFT 2
> > >
> > > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> > > index 428d08718107..83b733a1f1e6 100644
> > > --- a/arch/arm/mm/cache-l2x0.c
> > > +++ b/arch/arm/mm/cache-l2x0.c
> > > @@ -1352,8 +1352,8 @@ static unsigned long
> > > aurora_range_end(unsigned long start, unsigned long end)
> > > * since cache range operations stall the CPU pipeline
> > > * until completion.
> > > */
> > > - if (end > start + MAX_RANGE_SIZE)
> > > - end = start + MAX_RANGE_SIZE;
> > > + if (end > start + AURORA_MAX_RANGE_SIZE)
> > > + end = start + AURORA_MAX_RANGE_SIZE;
> > >
> > > /*
> > > * Cache range operations can't straddle a page boundary.
> > > --
> > > 2.22.0
> > >
> > >
> >
> > --
> > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> > FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down
> > 622kbps up
> > According to speedtest.net: 11.9Mbps down 500kbps up
>
>
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^ permalink raw reply
* [PATCH] PCI: mediatek: Remove surplus return from a void function
From: Krzysztof Wilczynski @ 2019-08-25 22:10 UTC (permalink / raw)
To: Matthias Brugger
Cc: Lorenzo Pieralisi, linux-pci, linux-kernel, Ryder Lee,
Bjorn Helgaas, linux-mediatek, linux-arm-kernel
Remove unnecessary empty return statement at the
end of a void function mtk_pcie_intr_handler() in
the drivers/pci/controller/pcie-mediatek.c.
The surplus return statement was added as part of
the work in commit 42fe2f91b4eb ("PCI: mediatek:
Implement chained IRQ handling setup").
Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
---
drivers/pci/controller/pcie-mediatek.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 3eaa7081ab2a..626a7c352dfd 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -635,8 +635,6 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
}
chained_irq_exit(irqchip, desc);
-
- return;
}
static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
--
2.22.1
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* Re: [PATCH v2 2/5] soc: amlogic: Add support for Everything-Else power domains controller
From: Martin Blumenstingl @ 2019-08-25 21:10 UTC (permalink / raw)
To: Neil Armstrong
Cc: ulf.hansson, linux-pm, khilman, linux-kernel, linux-amlogic,
linux-arm-kernel
In-Reply-To: <20190823090418.17148-3-narmstrong@baylibre.com>
Hi Neil,
thank you for this update
I haven't tried this on the 32-bit SoCs yet, but I am confident that I
can make it work by "just" adding the SoC specific bits!
On Fri, Aug 23, 2019 at 11:06 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
[...]
> +/* AO Offsets */
> +
> +#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
> +#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
> +
> +/* HHI Offsets */
> +
> +#define HHI_MEM_PD_REG0 (0x40 << 2)
> +#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
> +#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
> +#define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
> +#define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
> +#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
> +#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
> +#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
> +#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
should we switch to the actual register offsets like we did in the
clock drivers?
[...]
> +static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
nit-pick: maybe name it sm1_pwrc_vpu_hdmi as the datasheet states that
it's for "VPU/HDMI"
[...]
> +#define VPU_HHI_MEMPD(__reg) \
> + { __reg, BIT(8) }, \
> + { __reg, BIT(9) }, \
> + { __reg, BIT(10) }, \
> + { __reg, BIT(11) }, \
> + { __reg, BIT(12) }, \
> + { __reg, BIT(13) }, \
> + { __reg, BIT(14) }, \
> + { __reg, BIT(15) }
the Amlogic implementation from buildroot-openlinux-A113-201901 (the
latest one I have)
kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
uses:
hd_set_reg_bits(P_HHI_MEM_PD_REG0, 0, 8, 8)
that basically translates to: GENMASK(15, 8) (which means we could
drop this macro)
the datasheet also states: 15~8 [...] HDMI memory PD (as a single
8-bit wide register)
[...]
> +static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
> + [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
> + pwrc_ee_get_power, 11, 2),
> + [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
> +};
> +
> +static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
> + [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
> + pwrc_ee_get_power, 11, 2),
> + [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
> + pwrc_ee_get_power),
> + [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
> + pwrc_ee_get_power),
> + [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
> + pwrc_ee_get_power),
> + [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
> + pwrc_ee_get_power),
> + [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
> + [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
> +};
my impression: I find this hard to read as it merges the TOP and
Memory PD domains from above, adding some seemingly random "11, 2" for
the VPU PD as well as pwrc_ee_get_power for some of the power domains
personally I like the way we describe clk_regmap because it's easy to
read (even though it adds a bit of boilerplate). I'm not sure if we
can make it work here, but this (not compile tested) is what I have in
mind (I chose two random power domains):
[PWRC_SM1_VPU_ID] = {
.name = "VPU",
.top_pd = SM1_EE_PD(8),
.mem_pds = {
VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
{ HHI_MEM_PD_REG0, GENMASK(15, 8) },
},
.num_mem_pds = 9,
.reset_names_count = 11,
.clk_names_count = 2,
},
[PWRC_SM1_ETH_ID] = {
.name = "ETH",
.mem_pds = { HHI_MEM_PD_REG0, GENMASK(3, 2) },
.num_mem_pds = 1,
},
...
I'd like to get Kevin's feedback on this
what you have right now is probably good enough for the initial
version of this driver. I'm bringing this discussion up because we
will add support for more SoCs to this driver (we migrate GX over to
it and I want to add 32-bit SoC support, which probably means at least
Meson8 - assuming they kept the power domains identical between
Meson8/8b/8m2).
[...]
> +struct meson_ee_pwrc_domain {
> + struct generic_pm_domain base;
> + bool enabled;
> + struct meson_ee_pwrc *pwrc;
> + struct meson_ee_pwrc_domain_desc desc;
> + struct clk_bulk_data *clks;
> + int num_clks;
> + struct reset_control *rstc;
> + int num_rstc;
> +};
> +
> +struct meson_ee_pwrc {
> + struct regmap *regmap_ao;
> + struct regmap *regmap_hhi;
> + struct meson_ee_pwrc_domain *domains;
> + struct genpd_onecell_data xlate;
> +};
(my impressions on this: I was surprised to find more structs down
here, I expected them to be together with the other structs further
up)
> +static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain)
> +{
> + u32 reg;
> +
> + regmap_read(pwrc_domain->pwrc->regmap_ao,
> + pwrc_domain->desc.top_pd->sleep_reg, ®);
> +
> + return (reg & pwrc_domain->desc.top_pd->sleep_mask);
should this also check for top_pd->iso_* as well as mem_pd->*?
if the top_pd part was optional we could even use the get_power
callback for *all* power domains in this driver (right now audio and
Ethernet don't have any get_power callback)
> +}
> +
> +static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
> +{
> + struct meson_ee_pwrc_domain *pwrc_domain =
> + container_of(domain, struct meson_ee_pwrc_domain, base);
> + int i;
> +
> + if (pwrc_domain->desc.top_pd)
> + regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
> + pwrc_domain->desc.top_pd->sleep_reg,
> + pwrc_domain->desc.top_pd->sleep_mask,
> + pwrc_domain->desc.top_pd->sleep_mask);
> + udelay(20);
all four udelay(20) occurrences should probably be usleep_range(20,
100); (or some other max value), see [0]
[...]
> + /*
> + * TOFIX: This is a special case for the VPU power domain, which can
> + * be enabled previously by the bootloader. In this case the VPU
nit-pick: the indentation seems to be off here
[...]
> +static int meson_ee_pwrc_probe(struct platform_device *pdev)
> +{
> + const struct meson_ee_pwrc_domain_data *match;
> + struct regmap *regmap_ao, *regmap_hhi;
> + struct meson_ee_pwrc *pwrc;
> + int i, ret;
> +
> + match = of_device_get_match_data(&pdev->dev);
> + if (!match) {
> + dev_err(&pdev->dev, "failed to get match data\n");
> + return -ENODEV;
> + }
> +
> + pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
> + if (!pwrc)
> + return -ENOMEM;
> +
> + pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
> + sizeof(*pwrc->xlate.domains),
> + GFP_KERNEL);
> + if (!pwrc->xlate.domains)
> + return -ENOMEM;
> +
> + pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
> + sizeof(*pwrc->domains), GFP_KERNEL);
> + if (!pwrc->domains)
> + return -ENOMEM;
> +
> + pwrc->xlate.num_domains = match->count;
> +
> + regmap_hhi = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
> + if (IS_ERR(regmap_hhi)) {
> + dev_err(&pdev->dev, "failed to get HHI regmap\n");
> + return PTR_ERR(regmap_hhi);
> + }
> +
> + regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> + "amlogic,ao-sysctrl");
> + if (IS_ERR(regmap_ao)) {
> + dev_err(&pdev->dev, "failed to get AO regmap\n");
> + return PTR_ERR(regmap_ao);
> + }
> +
> + pwrc->regmap_ao = regmap_ao;
> + pwrc->regmap_hhi = regmap_hhi;
> +
> + platform_set_drvdata(pdev, pwrc);
> +
> + for (i = 0 ; i < match->count ; ++i) {
> + struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
> +
> + memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc));
> +
> + ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom);
> + if (ret)
> + return ret;
> +
> + pwrc->xlate.domains[i] = &dom->base;
> + }
> +
> + of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
return of_genpd_add_provider_onecell(...) to propagate errors (if any)
bonus question: what about the video decoder power domains?
here is an example from vdec_1_start
(drivers/staging/media/meson/vdec/vdec_1.c):
/* Enable power for VDEC_1 */
regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
GEN_PWR_VDEC_1, 0);
usleep_range(10, 20);
[...]
/* enable VDEC Memories */
amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0);
/* Remove VDEC1 Isolation */
regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0);
(my point here is that it mixes video decoder "DOS" registers with
AO_RTI_GEN_PWR registers)
do we also want to add support for these "DOS" power domains to the
meson-ee-pwrc driver?
what about the AO_RTI_GEN_PWR part then - should we keep management
for the video decoder power domain bits in AO_RTI_GEN_PWR as part of
the video decoder driver?
Martin
[0] https://www.kernel.org/doc/Documentation/timers/timers-howto.rst
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* [GIT PULL] ARM: at91: SoC for 5.4
From: Alexandre Belloni @ 2019-08-25 20:32 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson, arm, soc
Cc: Ludovic Desroches, linux-arm-kernel, linux-kernel
Hello,
A non urgent fix for the generated header in mach-at91 and mostly
MAINTAINERS updates.
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux tags/at91-5.4-soc
for you to fetch changes up to 2cb831e0f152e483ab797b44787a4ff426267fbc:
mailmap: map old company name to new one @microchip.com (2019-08-23 21:53:40 +0200)
----------------------------------------------------------------
AT91 SoC for 5.4
- MAINTAINERS updates
- a generated headers parallel build fix
----------------------------------------------------------------
Masahiro Yamada (1):
ARM: at91: move platform-specific asm-offset.h to arch/arm/mach-at91
Nicolas Ferre (3):
MAINTAINERS: at91: Collect all pinctrl/gpio drivers in same entry
MAINTAINERS: at91: remove the TC entry
mailmap: map old company name to new one @microchip.com
.mailmap | 1 +
MAINTAINERS | 14 +-------------
arch/arm/mach-at91/.gitignore | 1 +
arch/arm/mach-at91/Makefile | 5 +++--
arch/arm/mach-at91/pm_suspend.S | 2 +-
5 files changed, 7 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/mach-at91/.gitignore
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* [GIT PULL] ARM: at91: DT for 5.4
From: Alexandre Belloni @ 2019-08-25 20:26 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson, arm, soc
Cc: Ludovic Desroches, linux-arm-kernel, linux-kernel
Hi,
A few DT changes affecting only the style but not the DTB output. There
may be some late DT changes a bit later (but hopefully not too late).
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux tags/at91-5.4-dt
for you to fetch changes up to bb3e9c767c6134a5761470038e8c75cdb6f04867:
ARM: dts: at91: at91sam9x5dm.dtsi: Style cleanup (2019-08-21 18:41:36 +0200)
----------------------------------------------------------------
AT91 DT for 5.4
- style cleanup for at91sam9x5 based boards
- avoid colliding node and property names
----------------------------------------------------------------
Rob Herring (1):
ARM: dts: at91: Avoid colliding 'display' node and property names
Uwe Kleine-König (10):
dt-bindings: add vendor prefix "acme" for "Acme Systems srl"
ARM: dts: at91: Add label for sam9x5's internal RTC
ARM: dts: at91: ariag25: Style cleanup
ARM: dts: at91: ariettag25: style cleanup
ARM: dts: at91: cosino: Style cleanup
ARM: dts: at91: kizboxmini: Style cleanup
ARM: dts: at91: at91sam9g15: Style cleanup
ARM: dts: at91: at91sam9xx5ek: Style cleanup
ARM: dts: at91: at91sam9x5_lcd.dtsi: Style cleanup
ARM: dts: at91: at91sam9x5dm.dtsi: Style cleanup
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm/boot/dts/at91-ariag25.dts | 255 ++++++++++----------
arch/arm/boot/dts/at91-ariettag25.dts | 100 ++++----
arch/arm/boot/dts/at91-cosino.dtsi | 203 ++++++++--------
arch/arm/boot/dts/at91-cosino_mega2560.dts | 93 ++++----
arch/arm/boot/dts/at91-kizboxmini.dts | 179 +++++++-------
arch/arm/boot/dts/at91sam9261ek.dts | 2 +-
arch/arm/boot/dts/at91sam9263ek.dts | 2 +-
arch/arm/boot/dts/at91sam9g15.dtsi | 28 +--
arch/arm/boot/dts/at91sam9g15ek.dts | 12 +-
arch/arm/boot/dts/at91sam9g25ek.dts | 89 ++++---
arch/arm/boot/dts/at91sam9g35ek.dts | 22 +-
arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 +-
arch/arm/boot/dts/at91sam9rlek.dts | 2 +-
arch/arm/boot/dts/at91sam9x25ek.dts | 36 ++-
arch/arm/boot/dts/at91sam9x35ek.dts | 43 ++--
arch/arm/boot/dts/at91sam9x5.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 194 +++++++--------
arch/arm/boot/dts/at91sam9x5dm.dtsi | 86 ++++---
arch/arm/boot/dts/at91sam9x5ek.dtsi | 265 ++++++++++-----------
20 files changed, 785 insertions(+), 832 deletions(-)
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH v2 4/5] arm64: dts: meson-sm1-sei610: add HDMI display support
From: Martin Blumenstingl @ 2019-08-25 20:00 UTC (permalink / raw)
To: Neil Armstrong
Cc: ulf.hansson, linux-pm, khilman, linux-kernel, linux-amlogic,
linux-arm-kernel
In-Reply-To: <20190823090418.17148-5-narmstrong@baylibre.com>
On Fri, Aug 23, 2019 at 11:06 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Add the HDMI support nodes for the Amlogic SM1 Based SEI610 Board.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
this looks sane so feel free to add my:
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: meson-sm1-sei610: add USB support
From: Martin Blumenstingl @ 2019-08-25 19:59 UTC (permalink / raw)
To: Neil Armstrong
Cc: ulf.hansson, linux-pm, khilman, linux-kernel, linux-amlogic,
linux-arm-kernel
In-Reply-To: <20190823090418.17148-6-narmstrong@baylibre.com>
On Fri, Aug 23, 2019 at 11:06 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Add the USB properties for the Amlogic SM1 Based SEI610 Board in order to
> support the USB DRD Type-C port and the USB3 Type A port.
>
> The USB DRD Type-C controller uses the ID signal to toggle the USB role
> between the DWC3 Host controller and the DWC2 Device controller.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
(based on the patch description as I don't have the schematics for this board)
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: khadas-vim3: add support for the SM1 based VIM3
From: Martin Blumenstingl @ 2019-08-25 19:55 UTC (permalink / raw)
To: Neil Armstrong; +Cc: khilman, linux-kernel, linux-arm-kernel, linux-amlogic
In-Reply-To: <20190823081427.17228-4-narmstrong@baylibre.com>
On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Add the Amlogic SM1 based Khadas VIM3, sharing all the same features
> as the G12B based one, but:
> - a different DVFS support since only a single cluster is available
> - audio is still not available on SM1
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
schematics are not available yet but this looks sane so:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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^ permalink raw reply
* Re: [PATCH 2/3] amlogic: arm: add Amlogic SM1 based Khadas VIM3 variant bindings
From: Martin Blumenstingl @ 2019-08-25 19:51 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, linux-amlogic, linux-kernel, linux-arm-kernel,
devicetree
In-Reply-To: <20190823081427.17228-3-narmstrong@baylibre.com>
Hi Neil,
the subject should be: dt-bindings: arm: amlogic: ...
On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> The Khadas VIM3 is also available with the Pin-to-pin compatible
> Amlogic SM1 SoC in the S905D3 variant package.
>
> Change the description to match the S905X3/D3/Y3 variants like the G12A
> description, and add the vim3 compatible.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/arm/amlogic.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
> index b48ea1e4913a..2751dd778ce0 100644
> --- a/Documentation/devicetree/bindings/arm/amlogic.yaml
> +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
> @@ -150,9 +150,10 @@ properties:
> - const: amlogic,s922x
> - const: amlogic,g12b
>
> - - description: Boards with the Amlogic Meson SM1 S905X3 SoC
> + - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
> items:
> - enum:
> - seirobotics,sei610
> + - khadas,vim3
> - const: amlogic,sm1
on the GXL we differentiate between S905X and S905D
do we need to differentiate S905X3 from S905D3 (for example)?
Martin
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^ permalink raw reply
* Re: [PATCH 1/3] arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
From: Martin Blumenstingl @ 2019-08-25 19:41 UTC (permalink / raw)
To: Neil Armstrong; +Cc: khilman, linux-kernel, linux-arm-kernel, linux-amlogic
In-Reply-To: <20190823081427.17228-2-narmstrong@baylibre.com>
On Fri, Aug 23, 2019 at 10:15 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> To prepare support of the Amlogic SM1 based Khadas VIM3, move the non-G12B
> specific nodes (all except DVFS and Audio) to a new meson-khadas-vim3.dtsi
out of curiosity: is audio because of different routing on the board
or is it just because the audio driver needs more work for SM1?
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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^ permalink raw reply
* Re: [PATCH 0/7] arm64: dts: meson: ir keymap updates
From: Martin Blumenstingl @ 2019-08-25 19:38 UTC (permalink / raw)
To: Christian Hewitt
Cc: Mark Rutland, devicetree, Kevin Hilman, linux-kernel, Rob Herring,
linux-amlogic, linux-arm-kernel
In-Reply-To: <1566705688-18442-1-git-send-email-christianshewitt@gmail.com>
On Sun, Aug 25, 2019 at 6:03 AM Christian Hewitt
<christianshewitt@gmail.com> wrote:
>
> This series adds keymaps for several box/board vendor IR remote devices
> to respective device-tree files. The keymaps were submitted in [0] and
> have been queued for inclusion in Linux 5.4.
>
> The Khadas remote change swaps the rc-geekbox keymap for rc-khadas. The
> Geekbox branded remote was only sold for a brief period when VIM(1) was
> a new device. The Khadas branded remote that replaced it exchanged the
> Geekbox full-screen key for an Android mouse button using a different IR
> keycode. The rc-khadas keymap supports the mouse button keycode and maps
> it to KEY_MUTE.
>
> [0] https://patchwork.kernel.org/project/linux-media/list/?series=160309
>
> Christian Hewitt (7):
> arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap
> arm64: dts: meson-g12a-x96-max: add rc-x96max keymap
> arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap
> arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap
> arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap
> arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap
> arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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^ permalink raw reply
* [PATCH net-next v4 1/3] net: ethernet: mediatek: Add basic PHYLINK support
From: René van Dorst @ 2019-08-25 17:43 UTC (permalink / raw)
To: John Crispin, Sean Wang, Nelson Chang, David S . Miller,
Matthias Brugger
Cc: Frank Wunderlich, netdev, linux-mips, Russell King,
René van Dorst, linux-mediatek, Stefan Roese,
linux-arm-kernel
In-Reply-To: <20190825174341.20750-1-opensource@vdorst.com>
This convert the basics to PHYLINK API.
SGMII support is not in this patch.
Signed-off-by: René van Dorst <opensource@vdorst.com>
--
v3->v4:
* In link_down() a ~ was missing before the (, RX and TX bits have to be
cleared. Spotted by Russell King
v2->v3:
* Make link_down() similar as link_up() suggested by Russell King
v1->v2:
* Also report 1000Base-X support suggested by Russell King
* Reverse christmas on many places suggested by David Miller
* Rebase too pickup the mt76x8 changes.
---
drivers/net/ethernet/mediatek/Kconfig | 2 +-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 424 +++++++++++---------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 31 +-
3 files changed, 265 insertions(+), 192 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
index b76cf2e1c9dc..4968352ba188 100644
--- a/drivers/net/ethernet/mediatek/Kconfig
+++ b/drivers/net/ethernet/mediatek/Kconfig
@@ -9,7 +9,7 @@ if NET_VENDOR_MEDIATEK
config NET_MEDIATEK_SOC
tristate "MediaTek SoC Gigabit Ethernet support"
- select PHYLIB
+ select PHYLINK
---help---
This driver supports the gigabit ethernet MACs in the
MediaTek SoC family.
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 8ddbb8dcf032..7d2566dd4ce0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -18,6 +18,7 @@
#include <linux/tcp.h>
#include <linux/interrupt.h>
#include <linux/pinctrl/devinfo.h>
+#include <linux/phylink.h>
#include "mtk_eth_soc.h"
@@ -186,168 +187,224 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
mtk_w32(eth, val, TRGMII_TCK_CTRL);
}
-static void mtk_phy_link_adjust(struct net_device *dev)
+static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
{
- struct mtk_mac *mac = netdev_priv(dev);
- u16 lcl_adv = 0, rmt_adv = 0;
- u8 flowctrl;
- u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
- MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
- MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
- MAC_MCR_BACKPR_EN;
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+ struct mtk_eth *eth = mac->hw;
+ u32 mcr_cur, mcr_new;
+ int val, ge_mode = 0;
+
+ /* MT76x8 has no hardware settings between for the MAC */
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+ mac->interface != state->interface) {
+ /* Setup soc pin functions */
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
+ if (mac->id)
+ goto err_phy;
+ if (!MTK_HAS_CAPS(mac->hw->soc->caps,
+ MTK_GMAC1_TRGMII))
+ goto err_phy;
+ /* fall through */
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII:
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ ge_mode = 1;
+ break;
+ case PHY_INTERFACE_MODE_REVMII:
+ ge_mode = 2;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (mac->id)
+ goto err_phy;
+ ge_mode = 3;
+ break;
+ default:
+ goto err_phy;
+ }
- if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
- return;
+ /* Setup clock for 1st gmac */
+ if (!mac->id &&
+ MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
+ if (MTK_HAS_CAPS(mac->hw->soc->caps,
+ MTK_TRGMII_MT7621_CLK)) {
+ if (mt7621_gmac0_rgmii_adjust(mac->hw,
+ state->interface))
+ goto err_phy;
+ } else {
+ if (state->interface !=
+ PHY_INTERFACE_MODE_TRGMII)
+ mtk_gmac0_rgmii_adjust(mac->hw,
+ state->speed);
+ }
+ }
- switch (dev->phydev->speed) {
+ /* put the gmac into the right mode */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+ val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
+ val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
+ regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+
+ mac->interface = state->interface;
+ }
+
+ /* Setup gmac */
+ mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
+ mcr_new = mcr_cur;
+ mcr_new &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
+ MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
+ MAC_MCR_FORCE_RX_FC);
+ mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
+ MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
+
+ switch (state->speed) {
case SPEED_1000:
- mcr |= MAC_MCR_SPEED_1000;
+ mcr_new |= MAC_MCR_SPEED_1000;
break;
case SPEED_100:
- mcr |= MAC_MCR_SPEED_100;
+ mcr_new |= MAC_MCR_SPEED_100;
break;
}
-
- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) {
- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
- if (mt7621_gmac0_rgmii_adjust(mac->hw,
- dev->phydev->interface))
- return;
- } else {
- if (!mac->trgmii)
- mtk_gmac0_rgmii_adjust(mac->hw,
- dev->phydev->speed);
- }
+ if (state->duplex == DUPLEX_FULL) {
+ mcr_new |= MAC_MCR_FORCE_DPX;
+ if (state->pause & MLO_PAUSE_TX)
+ mcr_new |= MAC_MCR_FORCE_TX_FC;
+ if (state->pause & MLO_PAUSE_RX)
+ mcr_new |= MAC_MCR_FORCE_RX_FC;
}
- if (dev->phydev->link)
- mcr |= MAC_MCR_FORCE_LINK;
+ /* Only update control register when needed! */
+ if (mcr_new != mcr_cur)
+ mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
- if (dev->phydev->duplex) {
- mcr |= MAC_MCR_FORCE_DPX;
+ return;
- if (dev->phydev->pause)
- rmt_adv = LPA_PAUSE_CAP;
- if (dev->phydev->asym_pause)
- rmt_adv |= LPA_PAUSE_ASYM;
+err_phy:
+ dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
+ mac->id, phy_modes(state->interface));
+}
- lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising);
- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+static int mtk_mac_link_state(struct phylink_config *config,
+ struct phylink_link_state *state)
+{
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+ u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
- if (flowctrl & FLOW_CTRL_TX)
- mcr |= MAC_MCR_FORCE_TX_FC;
- if (flowctrl & FLOW_CTRL_RX)
- mcr |= MAC_MCR_FORCE_RX_FC;
+ state->link = (pmsr & MAC_MSR_LINK);
+ state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
- netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
- flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
- flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
+ switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
+ case 0:
+ state->speed = SPEED_10;
+ break;
+ case MAC_MSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case MAC_MSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
}
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+ if (pmsr & MAC_MSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (pmsr & MAC_MSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
- if (!of_phy_is_fixed_link(mac->of_node))
- phy_print_status(dev->phydev);
+ return 1;
}
-static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
- struct device_node *phy_node)
+static void mtk_mac_an_restart(struct phylink_config *config)
{
- struct phy_device *phydev;
- int phy_mode;
-
- phy_mode = of_get_phy_mode(phy_node);
- if (phy_mode < 0) {
- dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
- return -EINVAL;
- }
-
- phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
- mtk_phy_link_adjust, 0, phy_mode);
- if (!phydev) {
- dev_err(eth->dev, "could not connect to PHY\n");
- return -ENODEV;
- }
+ /* Do nothing */
+}
- dev_info(eth->dev,
- "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
- mac->id, phydev_name(phydev), phydev->phy_id,
- phydev->drv->name);
+static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+ u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
- return 0;
+ mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
+ mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
}
-static int mtk_phy_connect(struct net_device *dev)
+static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface,
+ struct phy_device *phy)
{
- struct mtk_mac *mac = netdev_priv(dev);
- struct mtk_eth *eth;
- struct device_node *np;
- u32 val;
- int err;
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+ u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
- eth = mac->hw;
- np = of_parse_phandle(mac->of_node, "phy-handle", 0);
- if (!np && of_phy_is_fixed_link(mac->of_node))
- if (!of_phy_register_fixed_link(mac->of_node))
- np = of_node_get(mac->of_node);
- if (!np)
- return -ENODEV;
+ mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
+ mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+}
- err = mtk_setup_hw_path(eth, mac->id, of_get_phy_mode(np));
- if (err)
- goto err_phy;
-
- mac->ge_mode = 0;
- switch (of_get_phy_mode(np)) {
- case PHY_INTERFACE_MODE_TRGMII:
- mac->trgmii = true;
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_SGMII:
- break;
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_GMII:
- mac->ge_mode = 1;
- break;
- case PHY_INTERFACE_MODE_REVMII:
- mac->ge_mode = 2;
- break;
- case PHY_INTERFACE_MODE_RMII:
- if (!mac->id)
- goto err_phy;
- mac->ge_mode = 3;
- break;
- default:
- goto err_phy;
- }
+static void mtk_validate(struct phylink_config *config,
+ unsigned long *supported,
+ struct phylink_link_state *state)
+{
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
- /* No MT7628/88 support for now */
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
- /* put the gmac into the right mode */
- regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
- val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
- val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
- regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ state->interface != PHY_INTERFACE_MODE_MII &&
+ state->interface != PHY_INTERFACE_MODE_GMII &&
+ !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
+ phy_interface_mode_is_rgmii(state->interface)) &&
+ !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
+ !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII)) {
+ linkmode_zero(supported);
+ return;
}
- /* couple phydev to net_device */
- if (mtk_phy_connect_node(eth, mac, np))
- goto err_phy;
+ phylink_set_port_modes(mask);
+ phylink_set(mask, Autoneg);
- of_node_put(np);
+ if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
+ phylink_set(mask, 1000baseT_Full);
+ } else {
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_Full);
+ phylink_set(mask, 100baseT_Half);
+ phylink_set(mask, 100baseT_Full);
+
+ if (state->interface != PHY_INTERFACE_MODE_MII) {
+ phylink_set(mask, 1000baseT_Half);
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
+ }
+ }
- return 0;
+ phylink_set(mask, Pause);
+ phylink_set(mask, Asym_Pause);
-err_phy:
- if (of_phy_is_fixed_link(mac->of_node))
- of_phy_deregister_fixed_link(mac->of_node);
- of_node_put(np);
- dev_err(eth->dev, "%s: invalid phy\n", __func__);
- return -EINVAL;
+ linkmode_and(supported, supported, mask);
+ linkmode_and(state->advertising, state->advertising, mask);
}
+static const struct phylink_mac_ops mtk_phylink_ops = {
+ .validate = mtk_validate,
+ .mac_link_state = mtk_mac_link_state,
+ .mac_an_restart = mtk_mac_an_restart,
+ .mac_config = mtk_mac_config,
+ .mac_link_down = mtk_mac_link_down,
+ .mac_link_up = mtk_mac_link_up,
+};
+
static int mtk_mdio_init(struct mtk_eth *eth)
{
struct device_node *mii_np;
@@ -2013,6 +2070,14 @@ static int mtk_open(struct net_device *dev)
{
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
+ int err;
+
+ err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
+ if (err) {
+ netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+ err);
+ return err;
+ }
/* we run 2 netdevs on the same dma ring so we only bring it up once */
if (!refcount_read(ð->dma_refcnt)) {
@@ -2030,7 +2095,7 @@ static int mtk_open(struct net_device *dev)
else
refcount_inc(ð->dma_refcnt);
- phy_start(dev->phydev);
+ phylink_start(mac->phylink);
netif_start_queue(dev);
return 0;
}
@@ -2063,8 +2128,11 @@ static int mtk_stop(struct net_device *dev)
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
+ phylink_stop(mac->phylink);
+
netif_tx_disable(dev);
- phy_stop(dev->phydev);
+
+ phylink_disconnect_phy(mac->phylink);
/* only shutdown DMA if this is the last user */
if (!refcount_dec_and_test(ð->dma_refcnt))
@@ -2159,15 +2227,6 @@ static int mtk_hw_init(struct mtk_eth *eth)
ethsys_reset(eth, RSTCTRL_FE);
ethsys_reset(eth, RSTCTRL_PPE);
- regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
- for (i = 0; i < MTK_MAC_COUNT; i++) {
- if (!eth->mac[i])
- continue;
- val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
- val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
- }
- regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
-
if (eth->pctl) {
/* Set GE2 driving and slew rate */
regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
@@ -2180,11 +2239,11 @@ static int mtk_hw_init(struct mtk_eth *eth)
}
/* Set linkdown as the default for each GMAC. Its own MCR would be set
- * up with the more appropriate value when mtk_phy_link_adjust call is
- * being invoked.
+ * up with the more appropriate value when mtk_mac_config call is being
+ * invoked.
*/
for (i = 0; i < MTK_MAC_COUNT; i++)
- mtk_w32(eth, 0, MTK_MAC_MCR(i));
+ mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
/* Indicates CDM to parse the MTK special tag from CPU
* which also is working out for untag packets.
@@ -2212,7 +2271,7 @@ static int mtk_hw_init(struct mtk_eth *eth)
mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < MTK_MAC_COUNT; i++) {
u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
/* setup the forward port to send frame to PDMA */
@@ -2264,7 +2323,7 @@ static int __init mtk_init(struct net_device *dev)
dev->dev_addr);
}
- return mtk_phy_connect(dev);
+ return 0;
}
static void mtk_uninit(struct net_device *dev)
@@ -2272,20 +2331,20 @@ static void mtk_uninit(struct net_device *dev)
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
- phy_disconnect(dev->phydev);
- if (of_phy_is_fixed_link(mac->of_node))
- of_phy_deregister_fixed_link(mac->of_node);
+ phylink_disconnect_phy(mac->phylink);
mtk_tx_irq_disable(eth, ~0);
mtk_rx_irq_disable(eth, ~0);
}
static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
+ struct mtk_mac *mac = netdev_priv(dev);
+
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
- return phy_mii_ioctl(dev->phydev, ifr, cmd);
+ return phylink_mii_ioctl(mac->phylink, ifr, cmd);
default:
break;
}
@@ -2326,16 +2385,6 @@ static void mtk_pending_work(struct work_struct *work)
eth->dev->pins->default_state);
mtk_hw_init(eth);
- for (i = 0; i < MTK_MAC_COUNT; i++) {
- if (!eth->mac[i] ||
- of_phy_is_fixed_link(eth->mac[i]->of_node))
- continue;
- err = phy_init_hw(eth->netdev[i]->phydev);
- if (err)
- dev_err(eth->dev, "%s: PHY init failed.\n",
- eth->netdev[i]->name);
- }
-
/* restart DMA and enable IRQs */
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!test_bit(i, &restart))
@@ -2398,9 +2447,7 @@ static int mtk_get_link_ksettings(struct net_device *ndev,
if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
return -EBUSY;
- phy_ethtool_ksettings_get(ndev->phydev, cmd);
-
- return 0;
+ return phylink_ethtool_ksettings_get(mac->phylink, cmd);
}
static int mtk_set_link_ksettings(struct net_device *ndev,
@@ -2411,7 +2458,7 @@ static int mtk_set_link_ksettings(struct net_device *ndev,
if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
return -EBUSY;
- return phy_ethtool_ksettings_set(ndev->phydev, cmd);
+ return phylink_ethtool_ksettings_set(mac->phylink, cmd);
}
static void mtk_get_drvinfo(struct net_device *dev,
@@ -2445,22 +2492,10 @@ static int mtk_nway_reset(struct net_device *dev)
if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
return -EBUSY;
- return genphy_restart_aneg(dev->phydev);
-}
+ if (!mac->phylink)
+ return -ENOTSUPP;
-static u32 mtk_get_link(struct net_device *dev)
-{
- struct mtk_mac *mac = netdev_priv(dev);
- int err;
-
- if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
- return -EBUSY;
-
- err = genphy_update_link(dev->phydev);
- if (err)
- return ethtool_op_get_link(dev);
-
- return dev->phydev->link;
+ return phylink_ethtool_nway_reset(mac->phylink);
}
static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
@@ -2580,7 +2615,7 @@ static const struct ethtool_ops mtk_ethtool_ops = {
.get_msglevel = mtk_get_msglevel,
.set_msglevel = mtk_set_msglevel,
.nway_reset = mtk_nway_reset,
- .get_link = mtk_get_link,
+ .get_link = ethtool_op_get_link,
.get_strings = mtk_get_strings,
.get_sset_count = mtk_get_sset_count,
.get_ethtool_stats = mtk_get_ethtool_stats,
@@ -2608,9 +2643,10 @@ static const struct net_device_ops mtk_netdev_ops = {
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
- struct mtk_mac *mac;
const __be32 *_id = of_get_property(np, "reg", NULL);
- int id, err;
+ struct phylink *phylink;
+ int phy_mode, id, err;
+ struct mtk_mac *mac;
if (!_id) {
dev_err(eth->dev, "missing mac id\n");
@@ -2654,6 +2690,32 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
u64_stats_init(&mac->hw_stats->syncp);
mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
+ /* phylink create */
+ phy_mode = of_get_phy_mode(np);
+ if (phy_mode < 0) {
+ dev_err(eth->dev, "incorrect phy-mode\n");
+ err = -EINVAL;
+ goto free_netdev;
+ }
+
+ /* mac config is not set */
+ mac->interface = PHY_INTERFACE_MODE_NA;
+ mac->mode = MLO_AN_PHY;
+ mac->speed = SPEED_UNKNOWN;
+
+ mac->phylink_config.dev = ð->netdev[id]->dev;
+ mac->phylink_config.type = PHYLINK_NETDEV;
+
+ phylink = phylink_create(&mac->phylink_config,
+ of_fwnode_handle(mac->of_node),
+ phy_mode, &mtk_phylink_ops);
+ if (IS_ERR(phylink)) {
+ err = PTR_ERR(phylink);
+ goto free_netdev;
+ }
+
+ mac->phylink = phylink;
+
SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eth->netdev[id]->watchdog_timeo = 5 * HZ;
eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
@@ -2682,8 +2744,7 @@ static int mtk_probe(struct platform_device *pdev)
{
struct device_node *mac_np;
struct mtk_eth *eth;
- int err;
- int i;
+ int err, i;
eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
if (!eth)
@@ -2869,6 +2930,7 @@ static int mtk_probe(struct platform_device *pdev)
static int mtk_remove(struct platform_device *pdev)
{
struct mtk_eth *eth = platform_get_drvdata(pdev);
+ struct mtk_mac *mac;
int i;
/* stop all devices to make sure that dma is properly shut down */
@@ -2876,6 +2938,8 @@ static int mtk_remove(struct platform_device *pdev)
if (!eth->netdev[i])
continue;
mtk_stop(eth->netdev[i]);
+ mac = netdev_priv(eth->netdev[i]);
+ phylink_disconnect_phy(mac->phylink);
}
mtk_hw_deinit(eth);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index cc1466ae0926..7f5f541daad7 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -14,6 +14,7 @@
#include <linux/of_net.h>
#include <linux/u64_stats_sync.h>
#include <linux/refcount.h>
+#include <linux/phylink.h>
#define MTK_QDMA_PAGE_SIZE 2048
#define MTK_MAX_RX_LENGTH 1536
@@ -330,12 +331,19 @@
#define MAC_MCR_SPEED_100 BIT(2)
#define MAC_MCR_FORCE_DPX BIT(1)
#define MAC_MCR_FORCE_LINK BIT(0)
-#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
- MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
- MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
- MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
- MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
- MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
+#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
+
+/* Mac status registers */
+#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
+#define MAC_MSR_EEE1G BIT(7)
+#define MAC_MSR_EEE100M BIT(6)
+#define MAC_MSR_RX_FC BIT(5)
+#define MAC_MSR_TX_FC BIT(4)
+#define MAC_MSR_SPEED_1000 BIT(3)
+#define MAC_MSR_SPEED_100 BIT(2)
+#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
+#define MAC_MSR_DPX BIT(1)
+#define MAC_MSR_LINK BIT(0)
/* TRGMII RXC control register */
#define TRGMII_RCK_CTRL 0x10300
@@ -858,22 +866,23 @@ struct mtk_eth {
/* struct mtk_mac - the structure that holds the info about the MACs of the
* SoC
* @id: The number of the MAC
- * @ge_mode: Interface mode kept for setup restoring
+ * @interface: Interface mode kept for detecting change in hw settings
* @of_node: Our devicetree node
* @hw: Backpointer to our main datastruture
* @hw_stats: Packet statistics counter
- * @trgmii Indicate if the MAC uses TRGMII connected to internal
- switch
*/
struct mtk_mac {
int id;
- int ge_mode;
+ phy_interface_t interface;
+ unsigned int mode;
+ int speed;
struct device_node *of_node;
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
struct mtk_eth *hw;
struct mtk_hw_stats *hw_stats;
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
int hwlro_ip_cnt;
- bool trgmii;
};
/* the struct describing the SoC. these are declared in the soc_xyz.c files */
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH net-next v4 2/3] net: ethernet: mediatek: Re-add support SGMII
From: René van Dorst @ 2019-08-25 17:43 UTC (permalink / raw)
To: John Crispin, Sean Wang, Nelson Chang, David S . Miller,
Matthias Brugger
Cc: Frank Wunderlich, netdev, linux-mips, Russell King,
René van Dorst, linux-mediatek, Stefan Roese,
linux-arm-kernel
In-Reply-To: <20190825174341.20750-1-opensource@vdorst.com>
* Re-add SGMII support but now with PHYLINK API support
So the SGMII changes are more clear
* Move SGMII block setup from mtk_gmac_sgmii_path_setup() to
mtk_mac_config()
* Merge mtk_setup_hw_path() into mtk_mac_config()
* Remove mediatek,physpeed property, fixed-link supports now any speed so
speed = <2500>; is now valid with PHYLINK
* Demagic SGMII register values
* Use phylink state to setup fixed-link mode
Signed-off-by: René van Dorst <opensource@vdorst.com>
--
v3->v4:
* Refactor validate() to incorporate the following items.
* Also report 1000baseX_Full for SGMII and GMII modes.
Suggested by Russell King
* Report both 1000BaseX and 2500BaseX modes in both BaseX mode.
As Russsell King explains here:
https://lore.kernel.org/netdev/20190824091106.GC13294@shell.armlinux.org.uk/
v2->v3:
* Redo validate(), it was totally wrong. Noticed by Russell King.
v1->v2:
* SGMII port only support SGMII at 1Gbit, 1000BASE-X and 2500BASE-X.
Also SGMII mode only does auto-negotiation.
* Change validate() to support mt76x8 changes.
---
drivers/net/ethernet/mediatek/mtk_eth_path.c | 75 +--------
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 151 ++++++++++++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 37 ++++-
drivers/net/ethernet/mediatek/mtk_sgmii.c | 65 +++++---
4 files changed, 213 insertions(+), 115 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/ethernet/mediatek/mtk_eth_path.c
index 28960e4c4e43..ef11cf3d1ccc 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -239,10 +239,9 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)
return err;
}
-static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
+int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
{
- unsigned int val = 0;
- int sid, err, path;
+ int err, path;
path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
MTK_ETH_PATH_GMAC2_SGMII;
@@ -252,33 +251,10 @@ static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
if (err)
return err;
- /* The path GMAC to SGMII will be enabled once the SGMIISYS is being
- * setup done.
- */
- regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
-
- regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
- SYSCFG0_SGMII_MASK, ~(u32)SYSCFG0_SGMII_MASK);
-
- /* Decide how GMAC and SGMIISYS be mapped */
- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 0 : mac_id;
-
- /* Setup SGMIISYS with the determined property */
- if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))
- err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
- else
- err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);
-
- if (err)
- return err;
-
- regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
- SYSCFG0_SGMII_MASK, val);
-
return 0;
}
-static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
+int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
{
int err, path = 0;
@@ -296,7 +272,7 @@ static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
return 0;
}
-static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
+int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
{
int err, path;
@@ -311,46 +287,3 @@ static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
return 0;
}
-int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode)
-{
- int err;
-
- /* No mux'ing for MT7628/88 */
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
- return 0;
-
- switch (phymode) {
- case PHY_INTERFACE_MODE_TRGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_REVMII:
- case PHY_INTERFACE_MODE_RMII:
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
- err = mtk_gmac_rgmii_path_setup(eth, mac_id);
- if (err)
- return err;
- }
- break;
- case PHY_INTERFACE_MODE_SGMII:
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
- err = mtk_gmac_sgmii_path_setup(eth, mac_id);
- if (err)
- return err;
- }
- break;
- case PHY_INTERFACE_MODE_GMII:
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
- err = mtk_gmac_gephy_path_setup(eth, mac_id);
- if (err)
- return err;
- }
- break;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 7d2566dd4ce0..b41884e12434 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -193,8 +193,8 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
struct mtk_eth *eth = mac->hw;
- u32 mcr_cur, mcr_new;
- int val, ge_mode = 0;
+ u32 mcr_cur, mcr_new, sid;
+ int val, ge_mode, err;
/* MT76x8 has no hardware settings between for the MAC */
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
@@ -208,29 +208,42 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
MTK_GMAC1_TRGMII))
goto err_phy;
/* fall through */
- case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII:
- break;
case PHY_INTERFACE_MODE_MII:
- ge_mode = 1;
- break;
case PHY_INTERFACE_MODE_REVMII:
- ge_mode = 2;
- break;
case PHY_INTERFACE_MODE_RMII:
- if (mac->id)
- goto err_phy;
- ge_mode = 3;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
+ err = mtk_gmac_rgmii_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
+ break;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
+ err = mtk_gmac_sgmii_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
+ err = mtk_gmac_gephy_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
break;
default:
goto err_phy;
}
/* Setup clock for 1st gmac */
- if (!mac->id &&
+ if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
+ !phy_interface_mode_is_8023z(state->interface) &&
MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
if (MTK_HAS_CAPS(mac->hw->soc->caps,
MTK_TRGMII_MT7621_CLK)) {
@@ -245,6 +258,23 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
}
}
+ ge_mode = 0;
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ ge_mode = 1;
+ break;
+ case PHY_INTERFACE_MODE_REVMII:
+ ge_mode = 2;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (mac->id)
+ goto err_phy;
+ ge_mode = 3;
+ break;
+ default:
+ break;
+ }
+
/* put the gmac into the right mode */
regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
@@ -254,6 +284,40 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
mac->interface = state->interface;
}
+ /* SGMII */
+ if (state->interface == PHY_INTERFACE_MODE_SGMII ||
+ phy_interface_mode_is_8023z(state->interface)) {
+ /* The path GMAC to SGMII will be enabled once the SGMIISYS is
+ * being setup done.
+ */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+
+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
+ SYSCFG0_SGMII_MASK,
+ ~(u32)SYSCFG0_SGMII_MASK);
+
+ /* Decide how GMAC and SGMIISYS be mapped */
+ sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+ 0 : mac->id;
+
+ /* Setup SGMIISYS with the determined property */
+ if (state->interface != PHY_INTERFACE_MODE_SGMII)
+ err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
+ state);
+ else if (phylink_autoneg_inband(mode))
+ err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
+
+ if (err)
+ goto init_err;
+
+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
+ SYSCFG0_SGMII_MASK, val);
+ } else if (phylink_autoneg_inband(mode)) {
+ dev_err(eth->dev,
+ "In-band mode not supported in non SGMII mode!\n");
+ return;
+ }
+
/* Setup gmac */
mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr_new = mcr_cur;
@@ -264,6 +328,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
switch (state->speed) {
+ case SPEED_2500:
case SPEED_1000:
mcr_new |= MAC_MCR_SPEED_1000;
break;
@@ -288,6 +353,11 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
err_phy:
dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
mac->id, phy_modes(state->interface));
+ return;
+
+init_err:
+ dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
+ mac->id, phy_modes(state->interface), err);
}
static int mtk_mac_link_state(struct phylink_config *config,
@@ -326,7 +396,10 @@ static int mtk_mac_link_state(struct phylink_config *config,
static void mtk_mac_an_restart(struct phylink_config *config)
{
- /* Do nothing */
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+
+ mtk_sgmii_restart_an(mac->hw, mac->id);
}
static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
@@ -366,7 +439,10 @@ static void mtk_validate(struct phylink_config *config,
!(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
phy_interface_mode_is_rgmii(state->interface)) &&
!(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
- !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII)) {
+ !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
+ !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
+ (state->interface == PHY_INTERFACE_MODE_SGMII ||
+ phy_interface_mode_is_8023z(state->interface)))) {
linkmode_zero(supported);
return;
}
@@ -374,19 +450,53 @@ static void mtk_validate(struct phylink_config *config,
phylink_set_port_modes(mask);
phylink_set(mask, Autoneg);
- if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
phylink_set(mask, 1000baseT_Full);
- } else {
+ break;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ phylink_set(mask, 1000baseX_Full);
+ phylink_set(mask, 2500baseX_Full);
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ phylink_set(mask, 1000baseT_Half);
+ /* fall through */
+ case PHY_INTERFACE_MODE_SGMII:
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
+ /* fall through */
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RMII:
+ case PHY_INTERFACE_MODE_REVMII:
+ case PHY_INTERFACE_MODE_NA:
+ default:
phylink_set(mask, 10baseT_Half);
phylink_set(mask, 10baseT_Full);
phylink_set(mask, 100baseT_Half);
phylink_set(mask, 100baseT_Full);
+ break;
+ }
- if (state->interface != PHY_INTERFACE_MODE_MII) {
- phylink_set(mask, 1000baseT_Half);
+ if (state->interface == PHY_INTERFACE_MODE_NA) {
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
+ phylink_set(mask, 2500baseX_Full);
+ }
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseT_Half);
phylink_set(mask, 1000baseX_Full);
}
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseT_Half);
+ }
}
phylink_set(mask, Pause);
@@ -394,6 +504,11 @@ static void mtk_validate(struct phylink_config *config,
linkmode_and(supported, supported, mask);
linkmode_and(state->advertising, state->advertising, mask);
+
+ /* We can only operate at 2500BaseX or 1000BaseX. If requested
+ * to advertise both, only report advertising at 2500BaseX.
+ */
+ phylink_helper_basex_speed(state);
}
static const struct phylink_mac_ops mtk_phylink_ops = {
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 7f5f541daad7..76bd12cb8150 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -412,14 +412,38 @@
/* Register to auto-negotiation restart */
#define SGMSYS_PCS_CONTROL_1 0x0
#define SGMII_AN_RESTART BIT(9)
+#define SGMII_ISOLATE BIT(10)
+#define SGMII_AN_ENABLE BIT(12)
+#define SGMII_LINK_STATYS BIT(18)
+#define SGMII_AN_ABILITY BIT(19)
+#define SGMII_AN_COMPLETE BIT(21)
+#define SGMII_PCS_FAULT BIT(23)
+#define SGMII_AN_EXPANSION_CLR BIT(30)
/* Register to programmable link timer, the unit in 2 * 8ns */
#define SGMSYS_PCS_LINK_TIMER 0x18
#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
/* Register to control remote fault */
-#define SGMSYS_SGMII_MODE 0x20
-#define SGMII_REMOTE_FAULT_DIS BIT(8)
+#define SGMSYS_SGMII_MODE 0x20
+#define SGMII_IF_MODE_BIT0 BIT(0)
+#define SGMII_SPEED_DUPLEX_AN BIT(1)
+#define SGMII_SPEED_10 0x0
+#define SGMII_SPEED_100 BIT(2)
+#define SGMII_SPEED_1000 BIT(3)
+#define SGMII_DUPLEX_FULL BIT(4)
+#define SGMII_IF_MODE_BIT5 BIT(5)
+#define SGMII_REMOTE_FAULT_DIS BIT(8)
+#define SGMII_CODE_SYNC_SET_VAL BIT(9)
+#define SGMII_CODE_SYNC_SET_EN BIT(10)
+#define SGMII_SEND_AN_ERROR_EN BIT(11)
+#define SGMII_IF_MODE_MASK GENMASK(5, 1)
+
+/* Register to set SGMII speed, ANA RG_ Control Signals III*/
+#define SGMSYS_ANA_RG_CS3 0x2028
+#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
+#define RG_PHY_SPEED_1_25G 0x0
+#define RG_PHY_SPEED_3_125G BIT(2)
/* Register to power up QPHY */
#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
@@ -897,7 +921,12 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
u32 ana_rgc3);
int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
-int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id);
-int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode);
+int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
+ const struct phylink_link_state *state);
+void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
+
+int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
+int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
+int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
#endif /* MTK_ETH_H */
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
index ff509d42d818..4db27dfc7ec1 100644
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -16,8 +16,7 @@
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
{
struct device_node *np;
- const char *str;
- int i, err;
+ int i;
ss->ana_rgc3 = ana_rgc3;
@@ -29,19 +28,6 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
ss->regmap[i] = syscon_node_to_regmap(np);
if (IS_ERR(ss->regmap[i]))
return PTR_ERR(ss->regmap[i]);
-
- err = of_property_read_string(np, "mediatek,physpeed", &str);
- if (err)
- return err;
-
- if (!strcmp(str, "2500"))
- ss->flags[i] |= MTK_SGMII_PHYSPEED_2500;
- else if (!strcmp(str, "1000"))
- ss->flags[i] |= MTK_SGMII_PHYSPEED_1000;
- else if (!strcmp(str, "auto"))
- ss->flags[i] |= MTK_SGMII_PHYSPEED_AN;
- else
- return -EINVAL;
}
return 0;
@@ -73,27 +59,45 @@ int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
return 0;
}
-int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id)
+int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
+ const struct phylink_link_state *state)
{
unsigned int val;
- int mode;
if (!ss->regmap[id])
return -EINVAL;
regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
- val &= ~GENMASK(3, 2);
- mode = ss->flags[id] & MTK_SGMII_PHYSPEED_MASK;
- val |= (mode == MTK_SGMII_PHYSPEED_1000) ? 0 : BIT(2);
+ val &= ~RG_PHY_SPEED_MASK;
+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
+ val |= RG_PHY_SPEED_3_125G;
regmap_write(ss->regmap[id], ss->ana_rgc3, val);
/* Disable SGMII AN */
regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
- val &= ~BIT(12);
+ val &= ~SGMII_AN_ENABLE;
regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
/* SGMII force mode setting */
- val = 0x31120019;
+ regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
+ val &= ~SGMII_IF_MODE_MASK;
+
+ switch (state->speed) {
+ case SPEED_10:
+ val |= SGMII_SPEED_10;
+ break;
+ case SPEED_100:
+ val |= SGMII_SPEED_100;
+ break;
+ case SPEED_2500:
+ case SPEED_1000:
+ val |= SGMII_SPEED_1000;
+ break;
+ };
+
+ if (state->duplex == DUPLEX_FULL)
+ val |= SGMII_DUPLEX_FULL;
+
regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
/* Release PHYA power down state */
@@ -103,3 +107,20 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id)
return 0;
}
+
+void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
+{
+ struct mtk_sgmii *ss = eth->sgmii;
+ unsigned int val, sid;
+
+ /* Decide how GMAC and SGMIISYS be mapped */
+ sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+ 0 : mac_id;
+
+ if (!ss->regmap[sid])
+ return;
+
+ regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
+ val |= SGMII_AN_RESTART;
+ regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
+}
--
2.20.1
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* [PATCH net-next v4 3/3] dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the new phylink API
From: René van Dorst @ 2019-08-25 17:43 UTC (permalink / raw)
To: John Crispin, Sean Wang, Nelson Chang, David S . Miller,
Matthias Brugger
Cc: Frank Wunderlich, netdev, linux-mips, Russell King,
René van Dorst, linux-mediatek, Stefan Roese,
linux-arm-kernel
In-Reply-To: <20190825174341.20750-1-opensource@vdorst.com>
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.
Signed-off-by: René van Dorst <opensource@vdorst.com>
--
v3->v4:
* no change
v2->v3:
* no change
v1->v2:
* SGMII port only support BASE-X at 2.5Gbit.
---
.../arm/mediatek/mediatek,sgmiisys.txt | 2 --
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 28 +++++++++++++------
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 -
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
index f5518f26a914..30cb645c0e54 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -9,8 +9,6 @@ Required Properties:
- "mediatek,mt7622-sgmiisys", "syscon"
- "mediatek,mt7629-sgmiisys", "syscon"
- #clock-cells: Must be 1
-- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up
- the capability of the target PHY.
The SGMIISYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 710c5c3d87d3..83e10591e0e5 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -115,24 +115,34 @@
};
ð {
- pinctrl-names = "default";
- pinctrl-0 = <ð_pins>;
status = "okay";
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
- phy-handle = <&phy5>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
};
- mdio-bus {
+ mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
-
- phy5: ethernet-phy@5 {
- reg = <5>;
- phy-mode = "sgmii";
- };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index d1e13d340e26..dac51e98204c 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -931,6 +931,5 @@
"syscon";
reg = <0 0x1b128000 0 0x3000>;
#clock-cells = <1>;
- mediatek,physpeed = "2500";
};
};
--
2.20.1
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^ permalink raw reply related
* [PATCH net-next v4 0/3] net: ethernet: mediatek: convert to PHYLINK
From: René van Dorst @ 2019-08-25 17:43 UTC (permalink / raw)
To: John Crispin, Sean Wang, Nelson Chang, David S . Miller,
Matthias Brugger
Cc: Frank Wunderlich, netdev, linux-mips, Russell King,
René van Dorst, linux-mediatek, Stefan Roese,
linux-arm-kernel
These patches converts mediatek driver to PHYLINK API.
v3->v4:
* Phylink improvements and clean-ups after review
v2->v3:
* Phylink improvements and clean-ups after review
v1->v2:
* Rebase for mt76x8 changes
* Phylink improvements and clean-ups after review
* SGMII port doesn't support 2.5Gbit in SGMII mode only in BASE-X mode.
Refactor the code.
René van Dorst (3):
net: ethernet: mediatek: Add basic PHYLINK support
net: ethernet: mediatek: Re-add support SGMII
dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the
new phylink API
.../arm/mediatek/mediatek,sgmiisys.txt | 2 -
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 28 +-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 -
drivers/net/ethernet/mediatek/Kconfig | 2 +-
drivers/net/ethernet/mediatek/mtk_eth_path.c | 75 +--
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 521 ++++++++++++------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 68 ++-
drivers/net/ethernet/mediatek/mtk_sgmii.c | 65 ++-
8 files changed, 470 insertions(+), 292 deletions(-)
--
2.20.1
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^ permalink raw reply
* [PATCH 1/2] kbuild: change *FLAGS_<basetarget>.o to take the path relative to $(obj)
From: Masahiro Yamada @ 2019-08-25 17:28 UTC (permalink / raw)
To: linux-kbuild
Cc: Michal Marek, Suzuki K Poulose, Marc Zyngier, x86, Russell King,
linux-kernel, Masahiro Yamada, Ingo Molnar, Borislav Petkov,
linux-arm-kernel, Andy Lutomirski, H. Peter Anvin, James Morse,
Thomas Gleixner, kvmarm, Julien Thierry
Kbuild provides per-file compiler flag addition/removal:
CFLAGS_<basetarget>.o
CFLAGS_REMOVE_<basetarget>.o
AFLAGS_<basetarget>.o
AFLAGS_REMOVE_<basetarget>.o
CPPFLAGS_<basetarget>
HOSTCFLAGS_<basetarget>.o
HOSTCXXFLAGS_<basetarget>.o
The <basetarget> is the filename of the target without its suffix.
This syntax comes into a trouble when two files with the same name
appear in one Makefile, for example:
obj-y += foo.o
obj-y += dir/foo.o
CFLAGS_foo.o := <some-flags>
Here, the <some-flags> applies to both foo.o and dir/foo.o
The real world problem is:
scripts/kconfig/util.c
scripts/kconfig/lxdialog/util.c
Both files are compiled into scripts/kconfig/mconf, but only the
latter should be given with additional flags for ncurses.
It is more sensible to use the relative path to the Makefile, like this:
obj-y += foo.o
CFLAGS_foo.o := <some-flags>
obj-y += dir/foo.o
CFLAGS_dir/foo.o := <other-flags>
The $* variable is replaced with the stem ('%') part in a pattern rule.
In other words, this only works for pattern rules.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/kvm/Makefile | 5 +++--
arch/x86/entry/vdso/Makefile | 3 ++-
scripts/Makefile.host | 30 +++++++++++++++---------------
scripts/Makefile.lib | 10 +++++-----
scripts/kconfig/Makefile | 8 ++++----
5 files changed, 29 insertions(+), 27 deletions(-)
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 531e59f5be9c..b76b75bd9e00 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -8,13 +8,14 @@ ifeq ($(plus_virt),+virt)
plus_virt_def := -DREQUIRES_VIRT=1
endif
+KVM := ../../../virt/kvm
+
ccflags-y += -I $(srctree)/$(src) -I $(srctree)/virt/kvm/arm/vgic
-CFLAGS_arm.o := $(plus_virt_def)
+CFLAGS_$(KVM)/arm/arm.o := $(plus_virt_def)
AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
-KVM := ../../../virt/kvm
kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o
obj-$(CONFIG_KVM_ARM_HOST) += hyp/
diff --git a/arch/x86/entry/vdso/Makefile b/arch/x86/entry/vdso/Makefile
index 8df549138193..0f2154106d01 100644
--- a/arch/x86/entry/vdso/Makefile
+++ b/arch/x86/entry/vdso/Makefile
@@ -89,6 +89,7 @@ $(vobjs): KBUILD_CFLAGS := $(filter-out $(GCC_PLUGINS_CFLAGS) $(RETPOLINE_CFLAGS
#
CFLAGS_REMOVE_vdso-note.o = -pg
CFLAGS_REMOVE_vclock_gettime.o = -pg
+CFLAGS_REMOVE_vdso32/vclock_gettime.o = -pg
CFLAGS_REMOVE_vgetcpu.o = -pg
CFLAGS_REMOVE_vvar.o = -pg
@@ -128,7 +129,7 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE
$(obj)/vdsox32.so.dbg: $(obj)/vdsox32.lds $(vobjx32s) FORCE
$(call if_changed,vdso_and_check)
-CPPFLAGS_vdso32.lds = $(CPPFLAGS_vdso.lds)
+CPPFLAGS_vdso32/vdso32.lds = $(CPPFLAGS_vdso.lds)
VDSO_LDFLAGS_vdso32.lds = -m elf_i386 -soname linux-gate.so.1
targets += vdso32/vdso32.lds
diff --git a/scripts/Makefile.host b/scripts/Makefile.host
index b402c619147d..cd2b98e2f727 100644
--- a/scripts/Makefile.host
+++ b/scripts/Makefile.host
@@ -80,9 +80,9 @@ host-cxxshobjs := $(addprefix $(obj)/,$(host-cxxshobjs))
# Handle options to gcc. Support building with separate output directory
_hostc_flags = $(KBUILD_HOSTCFLAGS) $(HOST_EXTRACFLAGS) \
- $(HOSTCFLAGS_$(basetarget).o)
+ $(HOSTCFLAGS_$*.o)
_hostcxx_flags = $(KBUILD_HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \
- $(HOSTCXXFLAGS_$(basetarget).o)
+ $(HOSTCXXFLAGS_$*.o)
# $(objtree)/$(obj) for including generated headers from checkin source files
ifeq ($(KBUILD_EXTMOD),)
@@ -102,7 +102,7 @@ hostcxx_flags = -Wp,-MD,$(depfile) $(_hostcxx_flags)
# host-csingle -> Executable
quiet_cmd_host-csingle = HOSTCC $@
cmd_host-csingle = $(HOSTCC) $(hostc_flags) $(KBUILD_HOSTLDFLAGS) -o $@ $< \
- $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
+ $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$*)
$(host-csingle): $(obj)/%: $(src)/%.c FORCE
$(call if_changed_dep,host-csingle)
@@ -110,9 +110,9 @@ $(host-csingle): $(obj)/%: $(src)/%.c FORCE
# host-cmulti -> executable
quiet_cmd_host-cmulti = HOSTLD $@
cmd_host-cmulti = $(HOSTCC) $(KBUILD_HOSTLDFLAGS) -o $@ \
- $(addprefix $(obj)/,$($(@F)-objs)) \
- $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
-$(host-cmulti): FORCE
+ $(addprefix $(obj)/, $($*-objs)) \
+ $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$*)
+$(host-cmulti): $(obj)/%: FORCE
$(call if_changed,host-cmulti)
$(call multi_depend, $(host-cmulti), , -objs)
@@ -128,9 +128,9 @@ $(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE
quiet_cmd_host-cxxmulti = HOSTLD $@
cmd_host-cxxmulti = $(HOSTCXX) $(KBUILD_HOSTLDFLAGS) -o $@ \
$(foreach o,objs cxxobjs,\
- $(addprefix $(obj)/,$($(@F)-$(o)))) \
- $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
-$(host-cxxmulti): FORCE
+ $(addprefix $(obj)/, $($*-$(o)))) \
+ $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$*)
+$(host-cxxmulti): $(obj)/%: FORCE
$(call if_changed,host-cxxmulti)
$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs)
@@ -161,9 +161,9 @@ $(host-cxxshobjs): $(obj)/%.o: $(src)/%.c FORCE
# *.o -> .so shared library (host-cshlib)
quiet_cmd_host-cshlib = HOSTLLD -shared $@
cmd_host-cshlib = $(HOSTCC) $(KBUILD_HOSTLDFLAGS) -shared -o $@ \
- $(addprefix $(obj)/,$($(@F:.so=-objs))) \
- $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
-$(host-cshlib): FORCE
+ $(addprefix $(obj)/, $($*-objs)) \
+ $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$*.so)
+$(host-cshlib): $(obj)/%.so: FORCE
$(call if_changed,host-cshlib)
$(call multi_depend, $(host-cshlib), .so, -objs)
@@ -171,9 +171,9 @@ $(call multi_depend, $(host-cshlib), .so, -objs)
# *.o -> .so shared library (host-cxxshlib)
quiet_cmd_host-cxxshlib = HOSTLLD -shared $@
cmd_host-cxxshlib = $(HOSTCXX) $(KBUILD_HOSTLDFLAGS) -shared -o $@ \
- $(addprefix $(obj)/,$($(@F:.so=-objs))) \
- $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(@F))
-$(host-cxxshlib): FORCE
+ $(addprefix $(obj)/, $($*-objs)) \
+ $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$*.so)
+$(host-cxxshlib): $(obj)/%.so: FORCE
$(call if_changed,host-cxxshlib)
$(call multi_depend, $(host-cxxshlib), .so, -objs)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 264611972c4a..0d48e17bfb07 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -109,12 +109,12 @@ basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
modname_flags = -DKBUILD_MODNAME=$(call name-fix,$(modname))
orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) \
- $(ccflags-y) $(CFLAGS_$(basetarget).o)
-_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags))
+ $(ccflags-y) $(CFLAGS_$*.o)
+_c_flags = $(filter-out $(CFLAGS_REMOVE_$*.o), $(orig_c_flags))
orig_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) \
- $(asflags-y) $(AFLAGS_$(basetarget).o)
-_a_flags = $(filter-out $(AFLAGS_REMOVE_$(basetarget).o), $(orig_a_flags))
-_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
+ $(asflags-y) $(AFLAGS_$*.o)
+_a_flags = $(filter-out $(AFLAGS_REMOVE_$*.o), $(orig_a_flags))
+_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$*.lds)
#
# Enable gcov profiling flags for a file, directory or for all files depending
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index bed7a5a2fbe9..ef2f2336c469 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -166,15 +166,15 @@ $(obj)/nconf.o $(obj)/nconf.gui.o: $(obj)/nconf-cfg
# mconf: Used for the menuconfig target based on lxdialog
hostprogs-y += mconf
-lxdialog := checklist.o inputbox.o menubox.o textbox.o util.o yesno.o
-mconf-objs := mconf.o $(addprefix lxdialog/, $(lxdialog)) $(common-objs)
+lxdialog := $(addprefix lxdialog/, \
+ checklist.o inputbox.o menubox.o textbox.o util.o yesno.o)
+mconf-objs := mconf.o $(lxdialog) $(common-objs)
HOSTLDLIBS_mconf = $(shell . $(obj)/mconf-cfg && echo $$libs)
$(foreach f, mconf.o $(lxdialog), \
$(eval HOSTCFLAGS_$f = $$(shell . $(obj)/mconf-cfg && echo $$$$cflags)))
-$(obj)/mconf.o: $(obj)/mconf-cfg
-$(addprefix $(obj)/lxdialog/, $(lxdialog)): $(obj)/mconf-cfg
+$(addprefix $(obj)/, mconf.o $(lxdialog)): $(obj)/mconf-cfg
# qconf: Used for the xconfig target based on Qt
hostprogs-y += qconf
--
2.17.1
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^ permalink raw reply related
* Re: [PATCH v5 08/18] thermal: sun8i: support mod clocks
From: Frank Lee @ 2019-08-25 16:14 UTC (permalink / raw)
To: Vasily Khoruzhick
Cc: Mark Rutland, devicetree, Linux PM, Maxime Ripard,
Greg Kroah-Hartman, Daniel Lezcano, linux-kernel,
Eduardo Valentin, Chen-Yu Tsai, Rob Herring, Jonathan.Cameron,
Mauro Carvalho Chehab, rui.zhang, David S. Miller, arm-linux
In-Reply-To: <CA+E=qVd-hz68VhL0n+3-HDNua2QsT0dOVY9mRjhb5e5+tBW5Fg@mail.gmail.com>
HI Vasily,
On Wed, Aug 14, 2019 at 11:01 AM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>
> On Tue, Aug 13, 2019 at 1:06 PM Ondřej Jirman <megous@megous.com> wrote:
> >
> > On Mon, Aug 12, 2019 at 04:54:15PM -0700, Vasily Khoruzhick wrote:
> > > On Mon, Aug 12, 2019 at 4:46 PM Frank Lee <tiny.windzz@gmail.com> wrote:
> > > >
> > > > HI Vasily,
> > > >
> > > > On Sat, Aug 10, 2019 at 2:17 PM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> > > > >
> > > > > On Fri, Aug 9, 2019 at 10:31 PM Yangtao Li <tiny.windzz@gmail.com> wrote:
> > > > > >
> > > > > > H3 has extra clock, so introduce something in ths_thermal_chip/ths_device
> > > > > > and adds the process of the clock.
> > > > > >
> > > > > > This is pre-work for supprt it.
> > > > > >
> > > > > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > > > > > ---
> > > > > > drivers/thermal/sun8i_thermal.c | 17 ++++++++++++++++-
> > > > > > 1 file changed, 16 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
> > > > > > index b934bc81eba7..6f4294c2aba7 100644
> > > > > > --- a/drivers/thermal/sun8i_thermal.c
> > > > > > +++ b/drivers/thermal/sun8i_thermal.c
> > > > > > @@ -54,6 +54,7 @@ struct tsensor {
> > > > > > };
> > > > > >
> > > > > > struct ths_thermal_chip {
> > > > > > + bool has_mod_clk;
> > > > > > int sensor_num;
> > > > > > int offset;
> > > > > > int scale;
> > > > > > @@ -69,6 +70,7 @@ struct ths_device {
> > > > > > struct regmap *regmap;
> > > > > > struct reset_control *reset;
> > > > > > struct clk *bus_clk;
> > > > > > + struct clk *mod_clk;
> > > > > > struct tsensor sensor[MAX_SENSOR_NUM];
> > > > > > };
> > > > > >
> > > > > > @@ -274,6 +276,12 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
> > > > > > if (IS_ERR(tmdev->bus_clk))
> > > > > > return PTR_ERR(tmdev->bus_clk);
> > > > > >
> > > > > > + if (tmdev->chip->has_mod_clk) {
> > > > > > + tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod");
> > > > > > + if (IS_ERR(tmdev->mod_clk))
> > > > > > + return PTR_ERR(tmdev->mod_clk);
> > > > > > + }
> > > > > > +
> > > > > > ret = reset_control_deassert(tmdev->reset);
> > > > > > if (ret)
> > > > > > return ret;
> > > > > > @@ -282,12 +290,18 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
> > > > > > if (ret)
> > > > > > goto assert_reset;
> > > > > >
> > > > > > - ret = sun50i_ths_calibrate(tmdev);
> > > > > > + ret = clk_prepare_enable(tmdev->mod_clk);
> > > > >
> > > > > You have to set rate of modclk before enabling it since you can't rely
> > > > > on whatever bootloader left for you.
> > > > >
> > > > > Also I found that parameters you're using for PC_TEMP_PERIOD, ACQ0 and
> > > > > ACQ1 are too aggressive and may result in high interrupt rate to the
> > > > > point when it may stall RCU. I changed driver a bit to use params from
> > > > > Philipp Rossak's work (modclk set to 4MHz, PC_TEMP_PERIOD is 7, ACQ0
> > > > > is 255, ACQ1 is 63) and it fixed RCU stalls for me, see [1] for
> > > > > details.
> > > >
> > > > Why is the RCU stall happening, is it caused by a deadlock?
> > > > Can you provide log information and your configuration?
> > > > I am a bit curious.
> > >
> > > It's not deadlock, I believe it just can't handle that many interrupts
> > > when running at lowest CPU frequency. Even with Philipp's settings
> > > there's ~20 interrupts a second from ths. I don't remember how many
> > > interrupts were there with your settings.
> > >
> > > Unfortunately there's nothing interesting in backtraces, I'm using
> > > Pine64-LTS board.
> >
> > Recently there was a similar issue, with buggy CCU driver that caused
> > CIR interrupts being fired constantly, and it also resulted in RCU
> > stalls. Looks like a comon cause of RCU stalls.
> >
> > THS timing settings probably need to be made specific to the SoC, because
> > I noticed that the same settings lead to wildly different timings on
> > different SoCs.
> >
> > It would be good to measure how often ths interrupt fires with this driver
> > on various SoCs.
> >
> > 20 times a second and more sounds like overkill. I'd expect a useful
> > range to be at most 5-10 times a second. That should be enough to stop
> > overheating the SoC due to suddenly increased load, even without a
> > heatsink.
>
> Note that A64 has 3 sensors and each sensor has individual interrupt,
> so technically it's 6-7 interrupts per sensor per second
You only need to increase the value of the period to reduce the number
of interrupts.
Can you test the relationship between the period and the number of interrupts
when the mod clock does not change and stays 24M?
Thx.
Yangtao
>
> > regards,
> > o.
> >
> > > > Thx,
> > > > Yangtao
> > > >
> > > > >
> > > > > [1] https://github.com/anarsoul/linux-2.6/commit/46b8bb0fe2ccd1cd88fa9181a2ecbf79e8d513b2
> > > > >
> > > > >
> > > > > > if (ret)
> > > > > > goto bus_disable;
> > > > > >
> > > > > > + ret = sun50i_ths_calibrate(tmdev);
> > > > > > + if (ret)
> > > > > > + goto mod_disable;
> > > > > > +
> > > > > > return 0;
> > > > > >
> > > > > > +mod_disable:
> > > > > > + clk_disable_unprepare(tmdev->mod_clk);
> > > > > > bus_disable:
> > > > > > clk_disable_unprepare(tmdev->bus_clk);
> > > > > > assert_reset:
> > > > > > @@ -395,6 +409,7 @@ static int sun8i_ths_remove(struct platform_device *pdev)
> > > > > > {
> > > > > > struct ths_device *tmdev = platform_get_drvdata(pdev);
> > > > > >
> > > > > > + clk_disable_unprepare(tmdev->mod_clk);
> > > > > > clk_disable_unprepare(tmdev->bus_clk);
> > > > > > reset_control_assert(tmdev->reset);
> > > > > >
> > > > > > --
> > > > > > 2.17.1
> > > > > >
> > > > > >
> > > > > > _______________________________________________
> > > > > > linux-arm-kernel mailing list
> > > > > > linux-arm-kernel@lists.infradead.org
> > > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
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^ permalink raw reply
* [GIT PULL 7/7] i.MX defconfig update for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-defconfig-5.4
for you to fetch changes up to cd1b1264632a3fe739016843005e49e42c60be55:
arm64: defconfig: CONFIG_DRM_ETNAVIV=m (2019-08-03 17:15:37 +0200)
----------------------------------------------------------------
i.MX defconfig update for 5.4:
- Enable pinctrl and clock driver support for i.MX8MN SoC.
- Enable SDMA support for i.MX8MQ and i.MX8MM SoC, including
FW_LOADER_USER_HELPER and FW_LOADER_USER_HELPER_FALLBACK to support
SDMA firmware loading via udev.
- Enable module build of i.MX8 DDR PMU driver and ETNAVIV GPU driver.
- Enable module build of OV5645 camera driver in imx_v6_v7_defconfig.
----------------------------------------------------------------
Anson Huang (2):
arm64: defconfig: Select CONFIG_PINCTRL_IMX8MN by default
arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
Christian Gmeiner (1):
arm64: defconfig: CONFIG_DRM_ETNAVIV=m
Fabio Estevam (1):
ARM: imx_v6_v7_defconfig: Select the OV5645 camera driver
Leonard Crestez (1):
arm64: defconfig: Build imx8 ddr pmu as module
Robin Gong (1):
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
arch/arm/configs/imx_v6_v7_defconfig | 1 +
arch/arm64/configs/defconfig | 7 +++++++
2 files changed, 8 insertions(+)
_______________________________________________
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^ permalink raw reply
* [GIT PULL 6/7] i.MX arm64 device tree update for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt64-5.4
for you to fetch changes up to 215701807e53a379e1c9b2e6401676779ef85ea0:
arm64: dts: imx8mq: Add mux controller to iomuxc_gpr (2019-08-24 22:47:07 +0200)
----------------------------------------------------------------
i.MX arm64 device tree update for 5.4:
- New board support: i.MX8MQ Nitrogen8m, Hummingboard Pulse,
PICO-PI-IMX8M, i.MX8QXP AI_ML, and LS1046A FRWY board.
- Add gpio-ranges for GPIO devices on i.MX8MQ and i.MX8MM.
- Update OPP table according to latest data sheet and add opp-suspend
to OPP table for i.MX8MQ and i.MX8MM.
- Add IDEL states for i.MX8MM SoC.
- Correct I2C clock divider for Layerscape SoCs.
- Add series alias and LPUART baud clock for i.MX8QXP SoC.
- Add MIPI D-PHY device for i.MX8MQ and enable it on imx8mq-librem5
board.
- Enable USB1 and Type-C support for i.MX8MM EVK board.
- Add Thermal Monitor Unit support for LS1028A SoC.
- Misc small update and correction on Layerscape and i.MX8 support.
----------------------------------------------------------------
Abel Vesa (1):
arm64: dts: imx8mm: Init rates and parents configs for clocks
Anson Huang (9):
arm64: dts: imx8mq: Add gpio-ranges property
arm64: dts: imx8mm: Add gpio-ranges property
arm64: dts: imx8mm: Add "fsl,imx8mq-src" as src's fallback compatible
arm64: dts: imx8mm: Correct OPP table according to latest datasheet
arm64: dts: imx8mq: Correct OPP table according to latest datasheet
arm64: dts: imx8mq: Add clock for TMU node
arm64: dts: imx8mq: Add opp-suspend property to OPP table
arm64: dts: imx8mm: Add opp-suspend property to OPP table
arm64: dts: imx8mm: Enable cpu-idle driver
Ashish Kumar (1):
arm64: dts: ls1028a: Add esdhc node in dts
Chuanhua Han (7):
arm64: dts: ls1088a: Revise gpio registers to little-endian
arm64: dts: ls1088a: Fix incorrect I2C clock divider
arm64: dts: ls1012a: Fix incorrect I2C clock divider
arm64: dts: ls1028a: Fix incorrect I2C clock divider
arm64: dts: lx2160a: Fix incorrect I2C clock divider
arm64: dts: ls1088a: Add the DSPI controller node
arm64: dts: ls1088a-qds: Add the spi-flash nodes under the DSPI controller
Daniel Baluta (1):
arm64: dts: imx8mq-evk: Unbypass audio_pll1
Fabio Estevam (1):
arm64: dts: imx8mm-evk: Remove invalid properties
Fugang Duan (2):
arm64: dts: imx8qxp: add lpuart baud clock
arm64: dts: imx8qxp: add serial alias
Gary Bisson (1):
arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
Guido Günther (3):
arm64: dts: imx8mq: Add MIPI D-PHY
arm64: dts: imx8mq-librem5: Enable MIPI D-PHY
arm64: dts: imx8mq: Add mux controller to iomuxc_gpr
Ioana Ciornei (1):
arm64: dts: add the console node for DPAA2 platforms
Jon Nettleton (1):
arm64: dts: fsl: add support for Hummingboard Pulse
Leonard Crestez (1):
arm64: dts: imx8m: Add ddr-pmu nodes
Li Jun (3):
arm64: dts: imx8mm: Remove setting for IMX8MM_CLK_USB_CORE_REF
arm64: dts: imx8mm-evk: enable usb1 and typec support
arm64: dts: imx8mq: correct usb controller clocks
Lucas Stach (1):
arm64: dts: rdu3: add UCS1002 charge controller node
Manivannan Sadhasivam (1):
arm64: dts: freescale: Add support for i.MX8QXP AI_ML board
Pramod Kumar (1):
arm64: dts: nxp: add ls1046a-frwy board support
Richard Hu (1):
arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
Song Hui (2):
arm64: dts: ls1028a: fix gpio nodes
arm64: dts: ls1088a: update gpio compatible
Wen He (2):
arm64: dts: ls1028a: Add optional property node for Mali DP500
arm64: dts: ls1028a: Add properties node for Display output pixel clock
Yuantian Tang (1):
arm64: dts: ls1028a: Add Thermal Monitor Unit node
arch/arm64/boot/dts/freescale/Makefile | 5 +
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 +-
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 8 +
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 13 +
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 151 +++++++-
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts | 155 ++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 33 ++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 38 +-
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 +
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 21 +-
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 68 +++-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 61 ++-
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 6 +-
.../dts/freescale/imx8mq-hummingboard-pulse.dts | 256 +++++++++++++
.../boot/dts/freescale/imx8mq-librem5-devkit.dts | 4 +
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts | 405 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 413 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 309 +++++++++++++++
.../arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 46 ++-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 52 ++-
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 249 +++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 23 +-
22 files changed, 2241 insertions(+), 84 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
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^ permalink raw reply
* [GIT PULL 5/7] i.MX arm32 device tree changes for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt-5.4
for you to fetch changes up to b04f537caab4deae1b839438e8fd5ed4bc598b43:
ARM: dts: vf610-zii-scu4-aib: Configure IRQ line for GPIO expander (2019-08-25 09:15:17 +0200)
----------------------------------------------------------------
i.MX arm32 device tree changes for 5.4:
- New board support: ZII i.MX7 RMU2, Kontron i.MX6UL N6310, and
PHYTEC phyBOARD-Segin based on i.MX6ULL.
- A series from Andrey Smirnov to update vf610-zii boards on I2C
pinmux, switch watchdog, GPIO expander IRQ.
- Move GIC node into soc node for i.MX6 SoCs.
- Add OV5645 camera support for imx6qdl-wandboard board.
- Drop unneeded snvs_pwrkey node for imx7d-zii-rpu2 and imx7-colibri.
- Use simple-mfd instead of simple-bus for i.MX6 ANATOP.
- Move the native-mode property inside the display-timings node for
various i.MX25 and i.MX27 boards.
- Add EDMA devices for i.MX7ULP SoC.
- A series from Stefan Riedmueller to update imx6ul-phytec-segin board
on various devices.
- Use OF graph to describe the display for opos6uldev board.
- Misc random updates on i.MX7/6 boards.
----------------------------------------------------------------
Alexandre Belloni (1):
ARM: dts: pbab01: correct rtc vendor
Andrey Smirnov (7):
ARM: dts: Add ZII support for ZII i.MX7 RMU2 board
ARM: dts: vf610-zii-spb4: Drop unused pinctrl_i2c1 pinmux config
ARM: dts: vf610-zii-scu4-aib: Fix pinctrl_i2c1's identation
ARM: dts: vf610-zii-scu4-aib: Drop unused pinctrl_i2c3 pinmux config
ARM: vf610-zii-cfu1: Add node for switch watchdog
ARM: dts: vf610-zii-cfu1: Slow I2C0 down to 100 kHz
ARM: dts: vf610-zii-scu4-aib: Configure IRQ line for GPIO expander
André Draszik (2):
ARM: dts: imx7d: cl-som-imx7: make ethernet work again
ARM: dts: imx7d: cl-som-imx7: add compatible for phy
Anson Huang (4):
ARM: dts: imx6sx: move GIC to right location in DT
ARM: dts: imx6sl: move GIC to right location in DT
ARM: dts: imx6ul: move GIC to right location in DT
ARM: dts: imx6sll: move GIC to right location in DT
Ezequiel Garcia (1):
ARM: dts: imx6qdl-wandboard: Add OV5645 camera support
Fabio Estevam (3):
ARM: dts: imx7d-zii-rpu2: Remove unneeded snvs_pwrkey node
ARM: dts: imx7-colibri: Remove unneeded snvs_pwrkey node
ARM: dts: imx6qdl-nit6xlite: Remove invalid properties
Krzysztof Kozlowski (2):
ARM: dts: imx: Cleanup style around assignment operator
ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards
Marcel Ziswiler (1):
ARM: dts: imx7-colibri: make sure module supplies are always on
Marco Felsch (2):
ARM: dts: imx6: replace simple-bus by simple-mfd for anatop
ARM: dts: imx6: drop gpmi-nand address and size cells
Marek Vasut (1):
ARM: dts: imx53: Update LCD panel node on M53Menlo
Martin Kaiser (9):
ARM: dts: imx25-pdk: native-mode is part of display-timings
ARM: dts: imx27 phyCARD-S: native-mode is part of display-timings
ARM: dts: imx25: mbimxsd25: native-mode is part of display-timings
ARM: dts: eukrea-mbimxsd27: native-mode is part of display-timings
ARM: dts: mbimxsd25: native-mode is part of display-timings
ARM: dts: imx27-phytec-phycore-rdk: native-mode is part of display-timings
ARM: dts: edb7211: native-mode is part of display-timings
ARM: dts: apf27dev: native-mode is part of display-timings
ARM: dts: imx25: mbimxsd25: native-mode is part of display-timings
Oleksandr Suvorov (1):
ARM: dts: imx7-colibri: add recovery for I2C for iMX7
Philippe Schenker (3):
ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
ARM: dts: imx7-colibri: Add sleep pinctrl to ethernet
ARM: dts: imx6qdl-colibri: add phy to fec
Robin Gong (3):
ARM: dts: imx6ul: add dma support on ecspi
ARM: dts: imx6sll: correct sdma compatible
ARM: dts: imx7ulp: add edma device node
Stefan Agner (1):
ARM: dts: imx7-colibri: disable HS400
Stefan Riedmueller (10):
ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme
ARM: dts: imx6ul: segin: Add boot media to dts filename
ARM: dts: imx6ul: segin: Reduce eth drive strength
ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01
ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dts
ARM: dts: imx6ul: segin: Only enable NAND if it is populated
ARM: dts: imx6ul: phycore: Add eMMC at usdhc2
ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
ARM: dts: imx6ul: segin: Move machine include to dts files
ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX 6ULL
Sébastien Szymanski (2):
ARM: dts: opos6uldev: use OF graph to describe the display
ARM: dts: imx6ul: Add csi node
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/ep7211-edb7211.dts | 2 +-
.../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 2 +-
.../imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 2 +-
.../imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 2 +-
arch/arm/boot/dts/imx25-pdk.dts | 2 +-
arch/arm/boot/dts/imx27-apf27dev.dts | 2 +-
.../boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts | 2 +-
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 2 +-
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +-
arch/arm/boot/dts/imx53-m53menlo.dts | 3 +-
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 11 +
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 2 -
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 73 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 4 +-
arch/arm/boot/dts/imx6sl.dtsi | 18 +-
arch/arm/boot/dts/imx6sll.dtsi | 24 +-
arch/arm/boot/dts/imx6sx.dtsi | 22 +-
arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts | 102 +++++
arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts | 420 +++++++++++++++++++++
arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi | 134 +++++++
arch/arm/boot/dts/imx6ul-opos6uldev.dts | 37 +-
...-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} | 53 ++-
...ull.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} | 42 ++-
...1.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} | 16 +-
...hyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} | 31 +-
arch/arm/boot/dts/imx6ul.dtsi | 53 ++-
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 +++++
.../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 93 +++++
.../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 45 +++
.../boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 38 ++
arch/arm/boot/dts/imx7-colibri.dtsi | 86 ++++-
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 6 +-
arch/arm/boot/dts/imx7d-zii-rmu2.dts | 357 ++++++++++++++++++
arch/arm/boot/dts/imx7d-zii-rpu2.dts | 4 -
arch/arm/boot/dts/imx7d.dtsi | 4 +-
arch/arm/boot/dts/imx7s.dtsi | 6 +-
arch/arm/boot/dts/imx7ulp.dtsi | 36 +-
arch/arm/boot/dts/vf610-zii-cfu1.dts | 21 +-
arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 12 +-
arch/arm/boot/dts/vf610-zii-spb4.dts | 7 -
44 files changed, 1741 insertions(+), 183 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
rename arch/arm/boot/dts/{imx6ul-phytec-pcl063.dtsi => imx6ul-phytec-phycore-som.dtsi} (71%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin-full.dts => imx6ul-phytec-segin-ff-rdk-nand.dts} (51%)
rename arch/arm/boot/dts/{imx6ul-phytec-peb-eval-01.dtsi => imx6ul-phytec-segin-peb-eval-01.dtsi} (84%)
rename arch/arm/boot/dts/{imx6ul-phytec-phyboard-segin.dtsi => imx6ul-phytec-segin.dtsi} (91%)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
create mode 100644 arch/arm/boot/dts/imx7d-zii-rmu2.dts
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* [GIT PULL 4/7] i.MX device tree update with new clocks
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Stephen Boyd, Fabio Estevam, Stefan Agner, Li Yang, linux-imx,
kernel, Shawn Guo, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
Hi,
This is the device tree update with new clocks, so clock commit
6ad7cb7122ce ("clk: imx8: Add DSP related clocks") gets pulled in here
as dependency, from i.MX clock branch I sent to Stephen. Please
consider to pull, thanks!
Shawn
The following changes since commit 6ad7cb7122cee4d3e672e58bf542b070b9363c15:
clk: imx8: Add DSP related clocks (2019-08-03 09:16:02 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt-clkdep-5.4
for you to fetch changes up to cd42fa171d913627acb631ddf8b2a5d3a3d7e6ee:
arm64: dts: imx8qxp: Add DSP DT node (2019-08-19 16:16:02 +0200)
----------------------------------------------------------------
i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
----------------------------------------------------------------
Anson Huang (6):
arm64: dts: freescale: Add i.MX8MN dtsi support
arm64: dts: imx8mn: Add gpio-ranges property
arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
arm64: dts: imx8mn: Add cpu-freq support
Daniel Baluta (1):
arm64: dts: imx8qxp: Add DSP DT node
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 348 ++++++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 758 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 32 +
5 files changed, 1143 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
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* [GIT PULL 3/7] i.MX DT bindings update for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-bindings-5.4
for you to fetch changes up to 8d5fc0b95fd1542c575ac64457bd17d74a206497:
dt-bindings: arm: fsl: Add Kontron i.MX6UL N6310 compatibles (2019-08-24 22:44:48 +0200)
----------------------------------------------------------------
i.MX DT bindings update for 5.4
- Add SoC bindings for i.MX8MN.
- Add board bindings for pico-pi-imx8m, Hummingboard Pulse, imx8mq
nitrogen, i.MX8QXP AI_ML, ls1046a-frwy etc.
- Add vendor prefix for Anvo-Systems and Einfochips.
- Update LPUART bindings for i.MX8QXP clock requirement.
- Update imx-weim bindings for optional burst clock mode support.
- Update EEPROM bindings for Anvo ANV32E61W device support.
----------------------------------------------------------------
Andra Danciu (1):
dt-bindings: arm: fsl: Add the pico-pi-imx8m board
Andrey Smirnov (1):
dt-bindings: arm: fsl: Add support for ZII i.MX7 RMU2 board
Anson Huang (1):
dt-bindings: arm: imx: Add the soc binding for i.MX8MN
Baruch Siach (1):
dt-bindings: arm: fsl: add Hummingboard Pulse
Chuanhua Han (1):
dt-bindings: fsl: dspi: Add fsl,ls1088a-dspi compatible string
Fugang Duan (1):
dt-bindings: serial: lpuart: add the clock requirement for imx8qxp
Gary Bisson (1):
dt-bindings: arm: imx: add imx8mq nitrogen support
Krzysztof Kozlowski (3):
dt-bindings: vendor-prefixes: Add Anvo-Systems
dt-bindings: eeprom: at25: Add Anvo ANV32E61W
dt-bindings: arm: fsl: Add Kontron i.MX6UL N6310 compatibles
Manivannan Sadhasivam (2):
dt-bindings: Add Vendor prefix for Einfochips
dt-bindings: arm: Document i.MX8QXP AI_ML board binding
Pramod Kumar (1):
dt-bindings: arm: nxp: Add device tree binding for ls1046a-frwy board
Sven Van Asbroeck (1):
dt-bindings: bus: imx-weim: document optional burst clock mode
Documentation/devicetree/bindings/arm/fsl.yaml | 26 ++++++++++++++++++++++
Documentation/devicetree/bindings/bus/imx-weim.txt | 4 ++++
Documentation/devicetree/bindings/eeprom/at25.txt | 1 +
.../devicetree/bindings/serial/fsl-lpuart.txt | 5 ++++-
.../devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 4 ++++
6 files changed, 40 insertions(+), 1 deletion(-)
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* [GIT PULL 2/7] i.MX SoC changes for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190825153237.28829-1-shawnguo@kernel.org>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-soc-5.4
for you to fetch changes up to acf993a0f22215dbc1d39f974e3053d6b4f4e594:
ARM: imx: stop adjusting ar8031 phy tx delay (2019-08-24 20:30:22 +0200)
----------------------------------------------------------------
i.MX SoC changes for 5.4:
- Drop AR8031 PHY TX delay adjusting from i.MX7D machine code, as
it's superfluous due to the recent changes to Atheros AT803X driver.
- Select TIMER_IMX_SYS_CTR for arm64 ARCH_MXC platform, since the
system counter is needed as broadcast timer for cpuidle support.
----------------------------------------------------------------
André Draszik (1):
ARM: imx: stop adjusting ar8031 phy tx delay
Anson Huang (1):
arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms
arch/arm/mach-imx/mach-imx7d.c | 6 ------
arch/arm64/Kconfig.platforms | 1 +
2 files changed, 1 insertion(+), 6 deletions(-)
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* [GIT PULL 1/7] i.MX drivers update for 5.4
From: Shawn Guo @ 2019-08-25 15:32 UTC (permalink / raw)
To: soc, arm
Cc: Shawn Guo, Stefan Agner, Li Yang, linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-drivers-5.4
for you to fetch changes up to 968c6f4b3c21e9fae9b49cc91214a01b4827625d:
soc: imx: gpcv2: Print the correct error code (2019-08-24 22:41:08 +0200)
----------------------------------------------------------------
i.MX drivers update for 5.4:
- A series from Anson Huang to add UID support for i.MX8 SoC and SCU
drivers.
- A series from Daniel Baluta to add DSP IPC driver for communication
between host AP (Linux) and the firmware running on DSP embedded in
i.MX8 SoCs.
- A small fix for GPCv2 error code printing.
- Switch from module_platform_driver_probe() to module_platform_driver()
for imx-weim driver, as we need the driver to probe again when device
is present later.
- Add optional burst clock mode support for imx-weim driver.
----------------------------------------------------------------
Anson Huang (3):
soc: imx8: Add i.MX8MQ UID(unique identifier) support
soc: imx8: Add i.MX8MM UID(unique identifier) support
soc: imx-scu: Add SoC UID(unique identifier) support
Daniel Baluta (4):
firmware: imx: scu-pd: Rename mu PD range to mu_a
firmware: imx: scu-pd: Add mu13 b side PD range
firmware: imx: scu-pd: Add IRQSTR_DSP PD range
firmware: imx: Add DSP IPC protocol interface
Guido Günther (1):
soc: imx: gpcv2: Print the correct error code
Sascha Hauer (1):
bus: imx-weim: use module_platform_driver()
Sven Van Asbroeck (1):
bus: imx-weim: optionally enable burst clock mode
drivers/bus/imx-weim.c | 24 +++++-
drivers/firmware/imx/Kconfig | 11 +++
drivers/firmware/imx/Makefile | 1 +
drivers/firmware/imx/imx-dsp.c | 155 +++++++++++++++++++++++++++++++++++++++
drivers/firmware/imx/scu-pd.c | 4 +-
drivers/soc/imx/gpcv2.c | 2 +-
drivers/soc/imx/soc-imx-scu.c | 39 ++++++++++
drivers/soc/imx/soc-imx8.c | 45 ++++++++++++
include/linux/firmware/imx/dsp.h | 67 +++++++++++++++++
9 files changed, 342 insertions(+), 6 deletions(-)
create mode 100644 drivers/firmware/imx/imx-dsp.c
create mode 100644 include/linux/firmware/imx/dsp.h
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* [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling DDR
From: Alejandro González @ 2019-08-25 15:05 UTC (permalink / raw)
To: ulf.hansson, maxime.ripard, wens, linus.walleij, gregkh, tglx,
linux-mmc, linux-arm-kernel, linux-kernel
Cc: linux-sunxi, Alejandro González
Some Allwinner H6 boards have timing problems when dealing with
DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6.
These timing problems result in out of sync communication between the
driver and the eMMC, which renders the memory unsuable for every
operation but some basic commmands, like reading the status register.
The cause of these timing problems is not yet well known, but they go
away by disabling DDR mode operation in the driver. Like on some H5
boards, it might be that the traces are not precise enough to support
these speeds. However, Jernej Skrabec compared the BSP driver with this
driver, and found that the BSP driver configures pinctrl to operate at
1.8 V when entering DDR mode (although 3.3 V operation is supported), while
the mainline kernel lacks any mechanism to switch voltages dynamically.
Finally, other possible cause might be some timing parameter that is
different on the H6 with respect to other SoCs.
Therefore, as this fix works reliably, the kernel lacks the required
dynamic pinctrl control for now and a slow eMMC is better than a not
working eMMC, just disable DDR operation for now on H6-compatible
devices.
Signed-off-by: Alejandro González <alejandro.gonzalez.correo@gmail.com>
---
drivers/mmc/host/sunxi-mmc.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d577a6b0ceae..dac57d76d009 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1395,14 +1395,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
/*
* Some H5 devices do not have signal traces precise enough to
- * use HS DDR mode for their eMMC chips.
+ * use HS DDR mode for their eMMC chips. Other H6 devices operate
+ * unreliably on HS DDR mode, too.
*
* We still enable HS DDR modes for all the other controller
- * variants that support them.
+ * variants that support them properly.
*/
if ((host->cfg->clk_delays || host->use_new_timings) &&
!of_device_is_compatible(pdev->dev.of_node,
- "allwinner,sun50i-h5-emmc"))
+ "allwinner,sun50i-h5-emmc") &&
+ !of_device_is_compatible(pdev->dev.of_node,
+ "allwinner,sun50i-h6-emmc"))
mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
ret = mmc_of_parse(mmc);
--
2.20.1
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