* [PATCH net-next] dt-bindings: net: ti: icssg_prueth: Add documentation for PA_STATS support
From: MD Danish Anwar @ 2024-04-30 12:24 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Paolo Abeni,
Jakub Kicinski, Eric Dumazet, David S. Miller
Cc: linux-kernel, devicetree, netdev, linux-arm-kernel, srk,
Vignesh Raghavendra, r-gunasekaran, Roger Quadros,
MD Danish Anwar
Add documentation for ti,pa-stats property which is syscon regmap for
PA_STATS register. This will be used to dump statistics maintained by
ICSSG firmware.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
index e253fa786092..abf372f7191b 100644
--- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
+++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
@@ -55,6 +55,11 @@ properties:
description:
phandle to MII_RT module's syscon regmap
+ ti,pa-stats:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to PA_STATS module's syscon regmap
+
ti,iep:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 2
@@ -194,6 +199,7 @@ examples:
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,pa-stats = <&icssg2_pa_stats>;
ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
interrupt-parent = <&icssg2_intc>;
interrupts = <24 0 2>, <25 1 3>;
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH 0/4] arm64/sysreg: Add registers for FEAT_Debugv8p9
From: Will Deacon @ 2024-04-30 12:27 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linux-arm-kernel, catalin.marinas
In-Reply-To: <a8a15178-35ee-4c77-aa1b-09c56bde37b2@arm.com>
On Mon, Apr 29, 2024 at 07:26:34AM +0530, Anshuman Khandual wrote:
> On 4/17/24 07:47, Anshuman Khandual wrote:
> > This series adds relevant registers and their fields which are required for
> > enabling FEAT_Debugv8p9. These patches have been split out from the earlier
> > series discussed below. This series applies on v6.9-rc4
> >
> > https://lore.kernel.org/all/20240405080008.1225223-1-anshuman.khandual@arm.com/
> >
> > Changes from RFC:
> >
> > - Updated the document number from DDI0601 2023-12 to 2024-03
> >
> > Anshuman Khandual (4):
> > arm64/sysreg: Add register fields for MDSELR_EL1
> > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > arm64/sysreg: Update ID_AA64MMFR0_EL1 register
> >
> > arch/arm64/tools/sysreg | 68 +++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> >
>
> Gentle ping, any updates on this series ?
Not sure why you dropped me from cc but, as with your other change [1],
I don't see the point in taking these on their own. Just keep them with
your hw_breakpoint series [2] when you post a new version taking into
account the feedback from Marc.
Will
[1] https://lore.kernel.org/all/20240419021325.2880384-1-anshuman.khandual@arm.com/
[2] https://lore.kernel.org/all/20240405080008.1225223-1-anshuman.khandual@arm.com/
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* Re: [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops()
From: Robin Murphy @ 2024-04-30 12:33 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov,
open list:DRM DRIVER FOR MSM ADRENO GPU, Bjorn Andersson
Cc: Joerg Roedel, Christoph Hellwig, Vineet Gupta, Russell King,
Catalin Marinas, Will Deacon, Huacai Chen, WANG Xuerui,
Thomas Bogendoerfer, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, K. Y. Srinivasan,
Haiyang Zhang, Wei Liu, Dexuan Cui, Suravee Suthikulpanit,
David Woodhouse, Lu Baolu, Niklas Schnelle, Matthew Rosato,
Gerald Schaefer, Jean-Philippe Brucker, Rob Herring, Frank Rowand,
Marek Szyprowski, Jason Gunthorpe, linux-kernel, linux-arm-kernel,
linux-acpi, iommu, devicetree, Jason Gunthorpe
In-Reply-To: <ebc8813c-74eb-49d1-b8d0-a6f1821f711a@linaro.org>
On 30/04/2024 1:23 pm, Konrad Dybcio wrote:
> On 29.04.2024 11:26 PM, Dmitry Baryshkov wrote:
>> On Mon, 29 Apr 2024 at 19:31, Dmitry Baryshkov
>> <dmitry.baryshkov@linaro.org> wrote:
>>>
>>> On Fri, Apr 19, 2024 at 05:54:45PM +0100, Robin Murphy wrote:
>>>> It's somewhat hard to see, but arm64's arch_setup_dma_ops() should only
>>>> ever call iommu_setup_dma_ops() after a successful iommu_probe_device(),
>>>> which means there should be no harm in achieving the same order of
>>>> operations by running it off the back of iommu_probe_device() itself.
>>>> This then puts it in line with the x86 and s390 .probe_finalize bodges,
>>>> letting us pull it all into the main flow properly. As a bonus this lets
>>>> us fold in and de-scope the PCI workaround setup as well.
>>>>
>>>> At this point we can also then pull the call up inside the group mutex,
>>>> and avoid having to think about whether iommu_group_store_type() could
>>>> theoretically race and free the domain if iommu_setup_dma_ops() ran just
>>>> *before* iommu_device_use_default_domain() claims it... Furthermore we
>>>> replace one .probe_finalize call completely, since the only remaining
>>>> implementations are now one which only needs to run once for the initial
>>>> boot-time probe, and two which themselves render that path unreachable.
>>>>
>>>> This leaves us a big step closer to realistically being able to unpick
>>>> the variety of different things that iommu_setup_dma_ops() has been
>>>> muddling together, and further streamline iommu-dma into core API flows
>>>> in future.
>>>>
>>>> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> # For Intel IOMMU
>>>> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
>>>> Tested-by: Hanjun Guo <guohanjun@huawei.com>
>>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>>> ---
>>>> v2: Shuffle around to make sure the iommu_group_do_probe_finalize() case
>>>> is covered as well, with bonus side-effects as above.
>>>> v3: *Really* do that, remembering the other two probe_finalize sites too.
>>>> ---
>>>> arch/arm64/mm/dma-mapping.c | 2 --
>>>> drivers/iommu/amd/iommu.c | 8 --------
>>>> drivers/iommu/dma-iommu.c | 18 ++++++------------
>>>> drivers/iommu/dma-iommu.h | 14 ++++++--------
>>>> drivers/iommu/intel/iommu.c | 7 -------
>>>> drivers/iommu/iommu.c | 20 +++++++-------------
>>>> drivers/iommu/s390-iommu.c | 6 ------
>>>> drivers/iommu/virtio-iommu.c | 10 ----------
>>>> include/linux/iommu.h | 7 -------
>>>> 9 files changed, 19 insertions(+), 73 deletions(-)
>>>
>>> This patch breaks UFS on Qualcomm SC8180X Primus platform:
>>>
>>>
>>> [ 3.846856] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x1032db3e0, fsynr=0x130000, cbfrsynra=0x300, cb=4
>>> [ 3.846880] ufshcd-qcom 1d84000.ufshc: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
>>> [ 3.846929] host_regs: 00000000: 1587031f 00000000 00000300 00000000
>>> [ 3.846935] host_regs: 00000010: 01000000 00010217 00000000 00000000
>>> [ 3.846941] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
>>> [ 3.846946] host_regs: 00000030: 0000000f 00000001 00000000 00000000
>>> [ 3.846951] host_regs: 00000040: 00000000 00000000 00000000 00000000
>>> [ 3.846956] host_regs: 00000050: 032db000 00000001 00000000 00000000
>>> [ 3.846962] host_regs: 00000060: 00000000 80000000 00000000 00000000
>>> [ 3.846967] host_regs: 00000070: 032dd000 00000001 00000000 00000000
>>> [ 3.846972] host_regs: 00000080: 00000000 00000000 00000000 00000000
>>> [ 3.846977] host_regs: 00000090: 00000016 00000000 00000000 0000000c
>>> [ 3.847074] ufshcd-qcom 1d84000.ufshc: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
>>> [ 4.406550] ufshcd-qcom 1d84000.ufshc: ufshcd_verify_dev_init: NOP OUT failed -11
>>> [ 4.417953] ufshcd-qcom 1d84000.ufshc: ufshcd_async_scan failed: -11
>>
>> Just to confirm: reverting f091e93306e0 ("dma-mapping: Simplify
>> arch_setup_dma_ops()") and b67483b3c44e ("iommu/dma: Centralise
>> iommu_setup_dma_ops()" fixes the issue for me. Please ping me if you'd
>> like me to test a fix.
>
> This also triggers a different issue (that also comes down to "ufs bad") on
> another QC platform (SM8550):
>
> [ 4.282098] scsi host0: ufshcd
> [ 4.315970] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
> [ 4.330155] host_regs: 00000000: 3587031f 00000000 00000400 00000000
> [ 4.343955] host_regs: 00000010: 01000000 00010217 00000000 00000000
> [ 4.356027] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
> [ 4.370136] host_regs: 00000030: 0000000f 00000003 00000000 00000000
> [ 4.376662] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 4.383192] host_regs: 00000050: 85109000 00000008 00000000 00000000
> [ 4.389719] host_regs: 00000060: 00000000 80000000 00000000 00000000
> [ 4.396245] host_regs: 00000070: 8510a000 00000008 00000000 00000000
> [ 4.402773] host_regs: 00000080: 00000000 00000000 00000000 00000000
> [ 4.409298] host_regs: 00000090: 00000016 00000000 00000000 0000000c
> [ 4.415900] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x8851093e0, fsynr=0x3b0001, cbfrsynra=0x60, cb=2
> [ 4.416135] ufshcd-qcom 1d84000.ufs: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
> [ 4.951750] ufshcd-qcom 1d84000.ufs: ufshcd_verify_dev_init: NOP OUT failed -11
> [ 4.960644] ufshcd-qcom 1d84000.ufs: ufshcd_async_scan failed: -11
>
> Reverting the commits Dmitry mentioned also fixes this.
Yeah, It'll be the same thing - doesn't really matter exactly *how* the
UFS goes wrong due to the SMMU blocking it, the issue is that the SMMU
is erroneously blocking it in the first place due to a DMA ops mixup.
Fix is now here:
https://lore.kernel.org/linux-iommu/d4cc20cbb0c45175e98dd76bf187e2ad6421296d.1714472573.git.robin.murphy@arm.com/
Thanks,
Robin.
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^ permalink raw reply
* Re: [PATCH 0/4] arm64/sysreg: Add registers for FEAT_Debugv8p9
From: Anshuman Khandual @ 2024-04-30 12:38 UTC (permalink / raw)
To: Will Deacon; +Cc: linux-arm-kernel, catalin.marinas
In-Reply-To: <20240430122738.GB13690@willie-the-truck>
On 4/30/24 17:57, Will Deacon wrote:
> On Mon, Apr 29, 2024 at 07:26:34AM +0530, Anshuman Khandual wrote:
>> On 4/17/24 07:47, Anshuman Khandual wrote:
>>> This series adds relevant registers and their fields which are required for
>>> enabling FEAT_Debugv8p9. These patches have been split out from the earlier
>>> series discussed below. This series applies on v6.9-rc4
>>>
>>> https://lore.kernel.org/all/20240405080008.1225223-1-anshuman.khandual@arm.com/
>>>
>>> Changes from RFC:
>>>
>>> - Updated the document number from DDI0601 2023-12 to 2024-03
>>>
>>> Anshuman Khandual (4):
>>> arm64/sysreg: Add register fields for MDSELR_EL1
>>> arm64/sysreg: Add register fields for HDFGRTR2_EL2
>>> arm64/sysreg: Add register fields for HDFGWTR2_EL2
>>> arm64/sysreg: Update ID_AA64MMFR0_EL1 register
>>>
>>> arch/arm64/tools/sysreg | 68 +++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 68 insertions(+)
>>>
>>
>> Gentle ping, any updates on this series ?
>
> Not sure why you dropped me from cc but, as with your other change [1],
Ahh that was my bad ! All individual patches here have your email marked in
their CC but then forgot to add the combined email set (what I normally do),
in the cover letter itself, making original --cc-cover pointless. This email
was in response to the cover-letter email thread, thus repeating the same
problem all over again. Apologies for the same.
> I don't see the point in taking these on their own. Just keep them with
> your hw_breakpoint series [2] when you post a new version taking into
> account the feedback from Marc.
Sure, will do that.
>
> Will
>
> [1] https://lore.kernel.org/all/20240419021325.2880384-1-anshuman.khandual@arm.com/
> [2] https://lore.kernel.org/all/20240405080008.1225223-1-anshuman.khandual@arm.com/
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^ permalink raw reply
* Re: [PATCH v7 05/16] module: make module_memory_{alloc,free} more self-contained
From: Philippe Mathieu-Daudé @ 2024-04-30 12:41 UTC (permalink / raw)
To: Mike Rapoport, linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Luis Chamberlain, Mark Rutland,
Masami Hiramatsu, Michael Ellerman, Nadav Amit, Palmer Dabbelt,
Peter Zijlstra, Rick Edgecombe, Russell King, Sam Ravnborg,
Song Liu, Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
In-Reply-To: <20240429121620.1186447-6-rppt@kernel.org>
On 29/4/24 14:16, Mike Rapoport wrote:
> From: "Mike Rapoport (IBM)" <rppt@kernel.org>
>
> Move the logic related to the memory allocation and freeing into
> module_memory_alloc() and module_memory_free().
>
> Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
> ---
> kernel/module/main.c | 64 +++++++++++++++++++++++++++-----------------
> 1 file changed, 39 insertions(+), 25 deletions(-)
Nice code simplification.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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* Re: [PATCH] arm64: Properly clean up iommu-dma remnants
From: Konrad Dybcio @ 2024-04-30 12:51 UTC (permalink / raw)
To: Robin Murphy, joro
Cc: will, catalin.marinas, linux-arm-kernel, iommu, Dmitry Baryshkov
In-Reply-To: <d4cc20cbb0c45175e98dd76bf187e2ad6421296d.1714472573.git.robin.murphy@arm.com>
On 30.04.2024 12:22 PM, Robin Murphy wrote:
> Thanks to the somewhat asymmetrical nature, while removing
> iommu_setup_dma_ops() from the arch_setup_dma_ops() flow, I managed to
> forget that arm64's teardown path was also specific to iommu-dma. Clean
> that up to match, otherwise probe deferral will lead to the arch code
> erroneously removing DMA ops set elsewhere.
>
> Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Link: https://lore.kernel.org/linux-iommu/Zi_LV28TR-P-PzXi@eriador.lumag.spb.ru/
> Fixes: b67483b3c44e ("iommu/dma: Centralise iommu_setup_dma_ops()")
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
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* Re: [PATCH v2 1/3] arm64/mm: Refactor PMD_PRESENT_INVALID and PTE_PROT_NONE bits
From: Ryan Roberts @ 2024-04-30 12:53 UTC (permalink / raw)
To: David Hildenbrand, Catalin Marinas
Cc: Will Deacon, Joey Gouly, Ard Biesheuvel, Mark Rutland,
Anshuman Khandual, Peter Xu, Mike Rapoport, Shivansh Vij,
linux-arm-kernel, linux-kernel
In-Reply-To: <29fd6909-73d2-4b7e-99ef-0101cde1ba8a@redhat.com>
On 30/04/2024 12:37, David Hildenbrand wrote:
> On 30.04.24 13:11, Catalin Marinas wrote:
>> On Mon, Apr 29, 2024 at 06:15:45PM +0100, Ryan Roberts wrote:
>>> On 29/04/2024 17:20, Catalin Marinas wrote:
>>>> On Mon, Apr 29, 2024 at 03:02:05PM +0100, Ryan Roberts wrote:
>>>>> diff --git a/arch/arm64/include/asm/pgtable-prot.h
>>>>> b/arch/arm64/include/asm/pgtable-prot.h
>>>>> index dd9ee67d1d87..de62e6881154 100644
>>>>> --- a/arch/arm64/include/asm/pgtable-prot.h
>>>>> +++ b/arch/arm64/include/asm/pgtable-prot.h
>>>>> @@ -18,14 +18,7 @@
>>>>> #define PTE_DIRTY (_AT(pteval_t, 1) << 55)
>>>>> #define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
>>>>> #define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
>>>>> -#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when
>>>>> !PTE_VALID */
>>>>> -
>>>>> -/*
>>>>> - * This bit indicates that the entry is present i.e. pmd_page()
>>>>> - * still points to a valid huge page in memory even if the pmd
>>>>> - * has been invalidated.
>>>>> - */
>>>>> -#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59) /* only when
>>>>> !PMD_SECT_VALID */
>>>>> +#define PTE_INVALID (_AT(pteval_t, 1) << 59) /* only when
>>>>> !PTE_VALID */
>>>>
>>>> Nitpick - I prefer the PTE_PRESENT_INVALID name as it makes it clearer
>>>> it's a present pte. We already have PTE_VALID, calling it PTE_INVALID
>>>> looks like a negation only.
>>>
>>> Meh, for me the pte can only be valid or invalid if it is present. So it's
>>> implicit. And if you have PTE_PRESENT_INVALID you should also have
>>> PTE_PRESENT_VALID.
>>>
>>> We also have pte_mkinvalid(), which is core-mm-defined. In your scheme, surely
>>> it should be pte_mkpresent_invalid()?
>>>
>>> But you're the boss, I'll change this to PTE_PRESENT_INVALID. :-(
>>
>> TBH, I don't have a strong opinion but best to avoid the bikeshedding.
>> I'll leave the decision to you ;). It would match the pmd_mkinvalid()
>> core code. But if you drop 'present' make sure you add a comment above
>> that it's meant for present ptes.
>
> FWIW, I was confused by
>
> present = valid | invalid
OK fair enough.
>
> Something like
>
> present = present_valid | present_invalid
I don't want to change pte_valid() to pte_present_valid(); that would also be a
fair bit of churn.
I'll take Catalin's suggestion and make this PTE_PRESENT_INVALID and
pte_present_invalid(). And obviously leave pmd_mkinvalid() as it is.
(Conversation in the other thread has concluded that it's ok to invalidate a
non-present pmd afterall).
>
> would be more obvious at least to me ;)
>
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^ permalink raw reply
* [PATCH 0/4] media: Fix compilations with !ACPI !PM and !OF
From: Ricardo Ribalda @ 2024-04-30 12:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Sakari Ailus, Bingbu Cao,
Tianshu Qiu
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
The current media-stating has some errors when configurations are
missing. Fix that.
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
Ricardo Ribalda (4):
media: bcm2835-unicam: Fix build with !PM
media: intel/ipu6: Switch to RUNTIME_PM_OPS() and SYSTEM_SLEEP_PM_OPS
media: intel/ipu6: Fix direct dependency Kconfig error
media: intel/ipu6: Fix build with !ACPI
drivers/media/pci/intel/Kconfig | 3 +-
drivers/media/pci/intel/ipu-bridge.c | 66 +++++++++++++++++-------
drivers/media/pci/intel/ipu6/ipu6.c | 6 +--
drivers/media/platform/broadcom/bcm2835-unicam.c | 2 +-
4 files changed, 53 insertions(+), 24 deletions(-)
---
base-commit: 1c73d0b29d04bf4082e7beb6a508895e118ee30d
change-id: 20240430-fix-ipu6-84d4d5515452
Best regards,
--
Ricardo Ribalda <ribalda@chromium.org>
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* [PATCH 2/4] media: intel/ipu6: Switch to RUNTIME_PM_OPS() and SYSTEM_SLEEP_PM_OPS
From: Ricardo Ribalda @ 2024-04-30 12:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Sakari Ailus, Bingbu Cao,
Tianshu Qiu
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
In-Reply-To: <20240430-fix-ipu6-v1-0-9b31fbbce6e4@chromium.org>
Replace the old helpers with its modern alternative.
Now we do not need to set '__maybe_unused' annotations when we are not
enabling the PM configurations.
Fixes:
drivers/media/pci/intel/ipu6/ipu6.c:841:12: warning: ‘ipu6_runtime_resume’ defined but not used [-Wunused-function]
drivers/media/pci/intel/ipu6/ipu6.c:806:12: warning: ‘ipu6_resume’ defined but not used [-Wunused-function]
drivers/media/pci/intel/ipu6/ipu6.c:801:12: warning: ‘ipu6_suspend’ defined but not used [-Wunused-function]
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/pci/intel/ipu6/ipu6.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/media/pci/intel/ipu6/ipu6.c b/drivers/media/pci/intel/ipu6/ipu6.c
index 4b1f69d14d71..ff5ca0c52781 100644
--- a/drivers/media/pci/intel/ipu6/ipu6.c
+++ b/drivers/media/pci/intel/ipu6/ipu6.c
@@ -803,7 +803,7 @@ static int ipu6_suspend(struct device *dev)
return 0;
}
-static int ipu6_resume(struct device *dev)
+static int __maybe_unused ipu6_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ipu6_device *isp = pci_get_drvdata(pdev);
@@ -860,8 +860,8 @@ static int ipu6_runtime_resume(struct device *dev)
}
static const struct dev_pm_ops ipu6_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(&ipu6_suspend, &ipu6_resume)
- SET_RUNTIME_PM_OPS(&ipu6_suspend, &ipu6_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(&ipu6_suspend, &ipu6_resume)
+ RUNTIME_PM_OPS(&ipu6_suspend, &ipu6_runtime_resume, NULL)
};
MODULE_DEVICE_TABLE(pci, ipu6_pci_tbl);
--
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* [PATCH 1/4] media: bcm2835-unicam: Fix build with !PM
From: Ricardo Ribalda @ 2024-04-30 12:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Sakari Ailus, Bingbu Cao,
Tianshu Qiu
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
In-Reply-To: <20240430-fix-ipu6-v1-0-9b31fbbce6e4@chromium.org>
The driver can only match the device vide the DT table, so the table
should always be used, of_match_ptr does not make sense here.
Fixes:
drivers/media/platform/broadcom/bcm2835-unicam.c:2724:34: warning: ‘unicam_of_match’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/platform/broadcom/bcm2835-unicam.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
index bd2bbb53070e..c590e26fe2cf 100644
--- a/drivers/media/platform/broadcom/bcm2835-unicam.c
+++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
@@ -2733,7 +2733,7 @@ static struct platform_driver unicam_driver = {
.driver = {
.name = UNICAM_MODULE_NAME,
.pm = pm_ptr(&unicam_pm_ops),
- .of_match_table = of_match_ptr(unicam_of_match),
+ .of_match_table = unicam_of_match,
},
};
--
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* [PATCH 4/4] media: intel/ipu6: Fix build with !ACPI
From: Ricardo Ribalda @ 2024-04-30 12:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Sakari Ailus, Bingbu Cao,
Tianshu Qiu
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
In-Reply-To: <20240430-fix-ipu6-v1-0-9b31fbbce6e4@chromium.org>
Modify the code so it can be compiled tested in configurations that do
not have ACPI enabled.
Fixes:
drivers/media/pci/intel/ipu-bridge.c:103:30: error: implicit declaration of function ‘acpi_device_handle’; did you mean ‘acpi_fwnode_handle’? [-Werror=implicit-function-declaration]
drivers/media/pci/intel/ipu-bridge.c:103:30: warning: initialization of ‘acpi_handle’ {aka ‘void *’} from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
drivers/media/pci/intel/ipu-bridge.c:110:17: error: implicit declaration of function ‘for_each_acpi_dev_match’ [-Werror=implicit-function-declaration]
drivers/media/pci/intel/ipu-bridge.c:110:74: error: expected ‘;’ before ‘for_each_acpi_consumer_dev’
drivers/media/pci/intel/ipu-bridge.c:104:29: warning: unused variable ‘consumer’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:103:21: warning: unused variable ‘handle’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:166:38: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:185:43: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:191:30: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:196:30: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:202:30: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:223:31: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:236:18: error: implicit declaration of function ‘acpi_get_physical_device_location’ [-Werror=implicit-function-declaration]
drivers/media/pci/intel/ipu-bridge.c:236:56: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:238:31: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:256:31: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:275:31: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:280:30: error: invalid use of undefined type ‘struct acpi_device’
drivers/media/pci/intel/ipu-bridge.c:469:26: error: implicit declaration of function ‘acpi_device_hid’; did you mean ‘dmi_device_id’? [-Werror=implicit-function-declaration]
drivers/media/pci/intel/ipu-bridge.c:468:74: warning: format ‘%s’ expects argument of type ‘char *’, but argument 4 has type ‘int’ [-Wformat=]
drivers/media/pci/intel/ipu-bridge.c:637:58: error: expected ‘;’ before ‘{’ token
drivers/media/pci/intel/ipu-bridge.c:696:1: warning: label ‘err_put_adev’ defined but not used [-Wunused-label]
drivers/media/pci/intel/ipu-bridge.c:693:1: warning: label ‘err_put_ivsc’ defined but not used [-Wunused-label]
drivers/media/pci/intel/ipu-bridge.c:691:1: warning: label ‘err_free_swnodes’ defined but not used [-Wunused-label]
drivers/media/pci/intel/ipu-bridge.c:632:40: warning: unused variable ‘primary’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:632:31: warning: unused variable ‘fwnode’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:733:73: error: expected ‘;’ before ‘{’ token
drivers/media/pci/intel/ipu-bridge.c:725:24: warning: unused variable ‘csi_dev’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:724:43: warning: unused variable ‘adev’ [-Wunused-variable]
drivers/media/pci/intel/ipu-bridge.c:599:12: warning: ‘ipu_bridge_instantiate_ivsc’ defined but not used [-Wunused-function]
drivers/media/pci/intel/ipu-bridge.c:444:13: warning: ‘ipu_bridge_create_connection_swnodes’ defined but not used [-Wunused-function]
drivers/media/pci/intel/ipu-bridge.c:297:13: warning: ‘ipu_bridge_create_fwnode_properties’ defined but not used [-Wunused-function]
drivers/media/pci/intel/ipu-bridge.c:155:12: warning: ‘ipu_bridge_check_ivsc_dev’ defined but not used [-Wunused-function]
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/pci/intel/ipu-bridge.c | 66 +++++++++++++++++++++++++-----------
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel/ipu-bridge.c
index e994db4f4d91..61750cc98d70 100644
--- a/drivers/media/pci/intel/ipu-bridge.c
+++ b/drivers/media/pci/intel/ipu-bridge.c
@@ -15,6 +15,8 @@
#include <media/ipu-bridge.h>
#include <media/v4l2-fwnode.h>
+#define ADEV_DEV(adev) ACPI_PTR(&((adev)->dev))
+
/*
* 92335fcf-3203-4472-af93-7b4453ac29da
*
@@ -87,6 +89,7 @@ static const char * const ipu_vcm_types[] = {
"lc898212axb",
};
+#if IS_ENABLED(CONFIG_ACPI)
/*
* Used to figure out IVSC acpi device by ipu_bridge_get_ivsc_acpi_dev()
* instead of device and driver match to probe IVSC device.
@@ -100,13 +103,13 @@ static const struct acpi_device_id ivsc_acpi_ids[] = {
static struct acpi_device *ipu_bridge_get_ivsc_acpi_dev(struct acpi_device *adev)
{
- acpi_handle handle = acpi_device_handle(adev);
- struct acpi_device *consumer, *ivsc_adev;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ivsc_acpi_ids); i++) {
const struct acpi_device_id *acpi_id = &ivsc_acpi_ids[i];
+ struct acpi_device *consumer, *ivsc_adev;
+ acpi_handle handle = acpi_device_handle(adev);
for_each_acpi_dev_match(ivsc_adev, acpi_id->id, NULL, -1)
/* camera sensor depends on IVSC in DSDT if exist */
for_each_acpi_consumer_dev(ivsc_adev, consumer)
@@ -118,6 +121,12 @@ static struct acpi_device *ipu_bridge_get_ivsc_acpi_dev(struct acpi_device *adev
return NULL;
}
+#else
+static struct acpi_device *ipu_bridge_get_ivsc_acpi_dev(struct acpi_device *adev)
+{
+ return NULL;
+}
+#endif
static int ipu_bridge_match_ivsc_dev(struct device *dev, const void *adev)
{
@@ -163,7 +172,7 @@ static int ipu_bridge_check_ivsc_dev(struct ipu_sensor *sensor,
csi_dev = ipu_bridge_get_ivsc_csi_dev(adev);
if (!csi_dev) {
acpi_dev_put(adev);
- dev_err(&adev->dev, "Failed to find MEI CSI dev\n");
+ dev_err(ADEV_DEV(adev), "Failed to find MEI CSI dev\n");
return -ENODEV;
}
@@ -182,24 +191,25 @@ static int ipu_bridge_read_acpi_buffer(struct acpi_device *adev, char *id,
acpi_status status;
int ret = 0;
- status = acpi_evaluate_object(adev->handle, id, NULL, &buffer);
+ status = acpi_evaluate_object(ACPI_PTR(adev->handle),
+ id, NULL, &buffer);
if (ACPI_FAILURE(status))
return -ENODEV;
obj = buffer.pointer;
if (!obj) {
- dev_err(&adev->dev, "Couldn't locate ACPI buffer\n");
+ dev_err(ADEV_DEV(adev), "Couldn't locate ACPI buffer\n");
return -ENODEV;
}
if (obj->type != ACPI_TYPE_BUFFER) {
- dev_err(&adev->dev, "Not an ACPI buffer\n");
+ dev_err(ADEV_DEV(adev), "Not an ACPI buffer\n");
ret = -ENODEV;
goto out_free_buff;
}
if (obj->buffer.length > size) {
- dev_err(&adev->dev, "Given buffer is too small\n");
+ dev_err(ADEV_DEV(adev), "Given buffer is too small\n");
ret = -EINVAL;
goto out_free_buff;
}
@@ -220,7 +230,7 @@ static u32 ipu_bridge_parse_rotation(struct acpi_device *adev,
case IPU_SENSOR_ROTATION_INVERTED:
return 180;
default:
- dev_warn(&adev->dev,
+ dev_warn(ADEV_DEV(adev),
"Unknown rotation %d. Assume 0 degree rotation\n",
ssdb->degree);
return 0;
@@ -230,12 +240,14 @@ static u32 ipu_bridge_parse_rotation(struct acpi_device *adev,
static enum v4l2_fwnode_orientation ipu_bridge_parse_orientation(struct acpi_device *adev)
{
enum v4l2_fwnode_orientation orientation;
- struct acpi_pld_info *pld;
- acpi_status status;
+ struct acpi_pld_info *pld = NULL;
+ acpi_status status = AE_ERROR;
+#if IS_ENABLED(CONFIG_ACPI)
status = acpi_get_physical_device_location(adev->handle, &pld);
+#endif
if (ACPI_FAILURE(status)) {
- dev_warn(&adev->dev, "_PLD call failed, using default orientation\n");
+ dev_warn(ADEV_DEV(adev), "_PLD call failed, using default orientation\n");
return V4L2_FWNODE_ORIENTATION_EXTERNAL;
}
@@ -253,7 +265,8 @@ static enum v4l2_fwnode_orientation ipu_bridge_parse_orientation(struct acpi_dev
orientation = V4L2_FWNODE_ORIENTATION_EXTERNAL;
break;
default:
- dev_warn(&adev->dev, "Unknown _PLD panel val %d\n", pld->panel);
+ dev_warn(ADEV_DEV(adev), "Unknown _PLD panel val %d\n",
+ pld->panel);
orientation = V4L2_FWNODE_ORIENTATION_EXTERNAL;
break;
}
@@ -272,12 +285,12 @@ int ipu_bridge_parse_ssdb(struct acpi_device *adev, struct ipu_sensor *sensor)
return ret;
if (ssdb.vcmtype > ARRAY_SIZE(ipu_vcm_types)) {
- dev_warn(&adev->dev, "Unknown VCM type %d\n", ssdb.vcmtype);
+ dev_warn(ADEV_DEV(adev), "Unknown VCM type %d\n", ssdb.vcmtype);
ssdb.vcmtype = 0;
}
if (ssdb.lanes > IPU_MAX_LANES) {
- dev_err(&adev->dev, "Number of lanes in SSDB is invalid\n");
+ dev_err(ADEV_DEV(adev), "Number of lanes in SSDB is invalid\n");
return -EINVAL;
}
@@ -465,8 +478,14 @@ static void ipu_bridge_create_connection_swnodes(struct ipu_bridge *bridge,
sensor->ipu_properties);
if (sensor->csi_dev) {
+ const char *device_hid = "";
+
+#if IS_ENABLED(CONFIG_ACPI)
+ device_hid = acpi_device_hid(sensor->ivsc_adev);
+#endif
+
snprintf(sensor->ivsc_name, sizeof(sensor->ivsc_name), "%s-%u",
- acpi_device_hid(sensor->ivsc_adev), sensor->link);
+ device_hid, sensor->link);
nodes[SWNODE_IVSC_HID] = NODE_SENSOR(sensor->ivsc_name,
sensor->ivsc_properties);
@@ -631,11 +650,15 @@ static int ipu_bridge_connect_sensor(const struct ipu_sensor_config *cfg,
{
struct fwnode_handle *fwnode, *primary;
struct ipu_sensor *sensor;
- struct acpi_device *adev;
+ struct acpi_device *adev = NULL;
int ret;
+#if IS_ENABLED(CONFIG_ACPI)
for_each_acpi_dev_match(adev, cfg->hid, NULL, -1) {
- if (!adev->status.enabled)
+#else
+ while (true) {
+#endif
+ if (!ACPI_PTR(adev->status.enabled))
continue;
if (bridge->n_sensors >= IPU_MAX_PORTS) {
@@ -671,7 +694,7 @@ static int ipu_bridge_connect_sensor(const struct ipu_sensor_config *cfg,
goto err_free_swnodes;
}
- sensor->adev = acpi_dev_get(adev);
+ sensor->adev = ACPI_PTR(acpi_dev_get(adev));
primary = acpi_fwnode_handle(adev);
primary->secondary = fwnode;
@@ -727,11 +750,16 @@ static int ipu_bridge_ivsc_is_ready(void)
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ipu_supported_sensors); i++) {
+#if IS_ENABLED(CONFIG_ACPI)
const struct ipu_sensor_config *cfg =
&ipu_supported_sensors[i];
for_each_acpi_dev_match(sensor_adev, cfg->hid, NULL, -1) {
- if (!sensor_adev->status.enabled)
+#else
+ while (true) {
+ sensor_adev = NULL;
+#endif
+ if (!ACPI_PTR(sensor_adev->status.enabled))
continue;
adev = ipu_bridge_get_ivsc_acpi_dev(sensor_adev);
--
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* [PATCH 3/4] media: intel/ipu6: Fix direct dependency Kconfig error
From: Ricardo Ribalda @ 2024-04-30 12:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Sakari Ailus, Bingbu Cao,
Tianshu Qiu
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
In-Reply-To: <20240430-fix-ipu6-v1-0-9b31fbbce6e4@chromium.org>
VIDEO_INTEL_IPU6 selects IPU6_BRIDGE, but they have different set of
dependencies.
Fixes:
WARNING: unmet direct dependencies detected for IPU_BRIDGE
Depends on [n]: MEDIA_SUPPORT [=y] && PCI [=y] && MEDIA_PCI_SUPPORT [=y] && I2C [=y] && ACPI [=n]
Selected by [y]:
- VIDEO_INTEL_IPU6 [=y] && MEDIA_SUPPORT [=y] && PCI [=y] && MEDIA_PCI_SUPPORT [=y] && (ACPI [=n] || COMPILE_TEST [=y]) && VIDEO_DEV [=y] && X86 [=y] && X86_64 [=y] && HAS_DMA [=y]
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/pci/intel/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/pci/intel/Kconfig b/drivers/media/pci/intel/Kconfig
index 04cb3d253486..d9fcddce028b 100644
--- a/drivers/media/pci/intel/Kconfig
+++ b/drivers/media/pci/intel/Kconfig
@@ -6,7 +6,8 @@ source "drivers/media/pci/intel/ivsc/Kconfig"
config IPU_BRIDGE
tristate "Intel IPU Bridge"
- depends on I2C && ACPI
+ depends on ACPI || COMPILE_TEST
+ depends on I2C
help
The IPU bridge is a helper library for Intel IPU drivers to
function on systems shipped with Windows.
--
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* Re: [PATCH v2 1/3] arm64/mm: Refactor PMD_PRESENT_INVALID and PTE_PROT_NONE bits
From: David Hildenbrand @ 2024-04-30 12:58 UTC (permalink / raw)
To: Ryan Roberts, Catalin Marinas
Cc: Will Deacon, Joey Gouly, Ard Biesheuvel, Mark Rutland,
Anshuman Khandual, Peter Xu, Mike Rapoport, Shivansh Vij,
linux-arm-kernel, linux-kernel
In-Reply-To: <e842963b-e682-4923-a1cc-c8b2abd6afee@arm.com>
On 30.04.24 14:53, Ryan Roberts wrote:
> On 30/04/2024 12:37, David Hildenbrand wrote:
>> On 30.04.24 13:11, Catalin Marinas wrote:
>>> On Mon, Apr 29, 2024 at 06:15:45PM +0100, Ryan Roberts wrote:
>>>> On 29/04/2024 17:20, Catalin Marinas wrote:
>>>>> On Mon, Apr 29, 2024 at 03:02:05PM +0100, Ryan Roberts wrote:
>>>>>> diff --git a/arch/arm64/include/asm/pgtable-prot.h
>>>>>> b/arch/arm64/include/asm/pgtable-prot.h
>>>>>> index dd9ee67d1d87..de62e6881154 100644
>>>>>> --- a/arch/arm64/include/asm/pgtable-prot.h
>>>>>> +++ b/arch/arm64/include/asm/pgtable-prot.h
>>>>>> @@ -18,14 +18,7 @@
>>>>>> #define PTE_DIRTY (_AT(pteval_t, 1) << 55)
>>>>>> #define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
>>>>>> #define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
>>>>>> -#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when
>>>>>> !PTE_VALID */
>>>>>> -
>>>>>> -/*
>>>>>> - * This bit indicates that the entry is present i.e. pmd_page()
>>>>>> - * still points to a valid huge page in memory even if the pmd
>>>>>> - * has been invalidated.
>>>>>> - */
>>>>>> -#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59) /* only when
>>>>>> !PMD_SECT_VALID */
>>>>>> +#define PTE_INVALID (_AT(pteval_t, 1) << 59) /* only when
>>>>>> !PTE_VALID */
>>>>>
>>>>> Nitpick - I prefer the PTE_PRESENT_INVALID name as it makes it clearer
>>>>> it's a present pte. We already have PTE_VALID, calling it PTE_INVALID
>>>>> looks like a negation only.
>>>>
>>>> Meh, for me the pte can only be valid or invalid if it is present. So it's
>>>> implicit. And if you have PTE_PRESENT_INVALID you should also have
>>>> PTE_PRESENT_VALID.
>>>>
>>>> We also have pte_mkinvalid(), which is core-mm-defined. In your scheme, surely
>>>> it should be pte_mkpresent_invalid()?
>>>>
>>>> But you're the boss, I'll change this to PTE_PRESENT_INVALID. :-(
>>>
>>> TBH, I don't have a strong opinion but best to avoid the bikeshedding.
>>> I'll leave the decision to you ;). It would match the pmd_mkinvalid()
>>> core code. But if you drop 'present' make sure you add a comment above
>>> that it's meant for present ptes.
>>
>> FWIW, I was confused by
>>
>> present = valid | invalid
>
> OK fair enough.
>
>>
>> Something like
>>
>> present = present_valid | present_invalid
>
> I don't want to change pte_valid() to pte_present_valid(); that would also be a
> fair bit of churn.
Yes.
>
> I'll take Catalin's suggestion and make this PTE_PRESENT_INVALID and
> pte_present_invalid(). And obviously leave pmd_mkinvalid() as it is.
> (Conversation in the other thread has concluded that it's ok to invalidate a
> non-present pmd afterall).
Works for me.
--
Cheers,
David / dhildenb
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^ permalink raw reply
* Re: [PATCH v7 08/10] regulator: tps6594-regulator: Add TI TPS65224 PMIC regulators
From: Bhargav Raviprakash @ 2024-04-30 13:05 UTC (permalink / raw)
To: dan.carpenter
Cc: arnd, bhargav.r, broonie, conor+dt, devicetree, eblanc, gregkh,
jpanis, kristo, krzysztof.kozlowski+dt, lee, lgirdwood,
linus.walleij, linux-arm-kernel, linux-gpio, linux-kernel,
m.nirmaladevi, nm, robh+dt, vigneshr
In-Reply-To: <54eca1ac-288c-4f88-8c06-f5859bfa715c@moroto.mountain>
Hello,
On Thu, 25 Apr 2024 10:59:22 +0300, Dan Carpenter wrote:
> On Wed, Apr 17, 2024 at 11:49:59AM +0000, Bhargav Raviprakash wrote:
> > From: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
> >
> > Add support for TPS65224 regulators (bucks and LDOs) to TPS6594 driver as
> > they have significant functional overlap. TPS65224 PMIC has 4 buck
> > regulators and 3 LDOs. BUCK12 can operate in dual phase.
> > The output voltages are configurable and are meant to supply power to the
> > main processor and other components.
> >
> > Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
> > Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
> > Reviewed-by: Mark Brown <broonie@kernel.org>
> > ---
> > drivers/regulator/Kconfig | 4 +-
> > drivers/regulator/tps6594-regulator.c | 243 +++++++++++++++++++++++---
> > 2 files changed, 222 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> > index 7db0a29b5..1e4119f00 100644
> > --- a/drivers/regulator/Kconfig
> > +++ b/drivers/regulator/Kconfig
> > @@ -1563,13 +1563,15 @@ config REGULATOR_TPS6594
> > depends on MFD_TPS6594 && OF
> > default MFD_TPS6594
> > help
> > - This driver supports TPS6594 voltage regulator chips.
> > + This driver supports TPS6594 series and TPS65224 voltage regulator chips.
> > TPS6594 series of PMICs have 5 BUCKs and 4 LDOs
> > voltage regulators.
> > BUCKs 1,2,3,4 can be used in single phase or multiphase mode.
> > Part number defines which single or multiphase mode is i used.
> > It supports software based voltage control
> > for different voltage domains.
> > + TPS65224 PMIC has 4 BUCKs and 3 LDOs. BUCK12 can be used in dual phase.
> > + All BUCKs and LDOs volatge can be controlled through software.
> >
> > config REGULATOR_TPS6524X
> > tristate "TI TPS6524X Power regulators"
> > diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6594-regulator.c
> > index b7f0c8779..3c8e0b1cd 100644
> > --- a/drivers/regulator/tps6594-regulator.c
> > +++ b/drivers/regulator/tps6594-regulator.c
> > @@ -66,6 +66,15 @@ static struct tps6594_regulator_irq_type tps6594_ext_regulator_irq_types[] = {
> > REGULATOR_EVENT_OVER_VOLTAGE_WARN },
> > };
> >
> > +static struct tps6594_regulator_irq_type tps65224_ext_regulator_irq_types[] = {
> > + { TPS65224_IRQ_NAME_VCCA_UVOV, "VCCA", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > + { TPS65224_IRQ_NAME_VMON1_UVOV, "VMON1", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > + { TPS65224_IRQ_NAME_VMON2_UVOV, "VMON2", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > struct tps6594_regulator_irq_data {
> > struct device *dev;
> > struct tps6594_regulator_irq_type *type;
> > @@ -122,6 +131,27 @@ static const struct linear_range ldos_4_ranges[] = {
> > REGULATOR_LINEAR_RANGE(1200000, 0x20, 0x74, 25000),
> > };
> >
> > +/* Voltage range for TPS65224 Bucks and LDOs */
> > +static const struct linear_range tps65224_bucks_1_ranges[] = {
> > + REGULATOR_LINEAR_RANGE(500000, 0x0a, 0x0e, 20000),
> > + REGULATOR_LINEAR_RANGE(600000, 0x0f, 0x72, 5000),
> > + REGULATOR_LINEAR_RANGE(1100000, 0x73, 0xaa, 10000),
> > + REGULATOR_LINEAR_RANGE(1660000, 0xab, 0xfd, 20000),
> > +};
> > +
> > +static const struct linear_range tps65224_bucks_2_3_4_ranges[] = {
> > + REGULATOR_LINEAR_RANGE(500000, 0x0, 0x1a, 25000),
> > + REGULATOR_LINEAR_RANGE(1200000, 0x1b, 0x45, 50000),
> > +};
> > +
> > +static const struct linear_range tps65224_ldos_1_ranges[] = {
> > + REGULATOR_LINEAR_RANGE(1200000, 0xC, 0x36, 50000),
> > +};
> > +
> > +static const struct linear_range tps65224_ldos_2_3_ranges[] = {
> > + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x38, 50000),
> > +};
> > +
> > /* Operations permitted on BUCK1/2/3/4/5 */
> > static const struct regulator_ops tps6594_bucks_ops = {
> > .is_enabled = regulator_is_enabled_regmap,
> > @@ -197,6 +227,38 @@ static const struct regulator_desc buck_regs[] = {
> > 4, 0, 0, NULL, 0, 0),
> > };
> >
> > +/* Buck configuration for TPS65224 */
> > +static const struct regulator_desc tps65224_buck_regs[] = {
> > + TPS6594_REGULATOR("BUCK1", "buck1", TPS6594_BUCK_1,
> > + REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS65224_MASK_BUCK1_VSET,
> > + TPS6594_REG_BUCKX_VOUT_1(0),
> > + TPS65224_MASK_BUCK1_VSET,
> > + TPS6594_REG_BUCKX_CTRL(0),
> > + TPS6594_BIT_BUCK_EN, 0, 0, tps65224_bucks_1_ranges,
> > + 4, 0, 0, NULL, 0, 0),
> > + TPS6594_REGULATOR("BUCK2", "buck2", TPS6594_BUCK_2,
> > + REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_VOUT_1(1),
> > + TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_CTRL(1),
> > + TPS6594_BIT_BUCK_EN, 0, 0, tps65224_bucks_2_3_4_ranges,
> > + 4, 0, 0, NULL, 0, 0),
> > + TPS6594_REGULATOR("BUCK3", "buck3", TPS6594_BUCK_3,
> > + REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_VOUT_1(2),
> > + TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_CTRL(2),
> > + TPS6594_BIT_BUCK_EN, 0, 0, tps65224_bucks_2_3_4_ranges,
> > + 4, 0, 0, NULL, 0, 0),
> > + TPS6594_REGULATOR("BUCK4", "buck4", TPS6594_BUCK_4,
> > + REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_VOUT_1(3),
> > + TPS65224_MASK_BUCKS_VSET,
> > + TPS6594_REG_BUCKX_CTRL(3),
> > + TPS6594_BIT_BUCK_EN, 0, 0, tps65224_bucks_2_3_4_ranges,
> > + 4, 0, 0, NULL, 0, 0),
> > +};
> > +
> > static struct tps6594_regulator_irq_type tps6594_buck1_irq_types[] = {
> > { TPS6594_IRQ_NAME_BUCK1_OV, "BUCK1", "overvoltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN },
> > { TPS6594_IRQ_NAME_BUCK1_UV, "BUCK1", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE },
> > @@ -269,6 +331,41 @@ static struct tps6594_regulator_irq_type tps6594_ldo4_irq_types[] = {
> > REGULATOR_EVENT_OVER_CURRENT },
> > };
> >
> > +static struct tps6594_regulator_irq_type tps65224_buck1_irq_types[] = {
> > + { TPS65224_IRQ_NAME_BUCK1_UVOV, "BUCK1", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_buck2_irq_types[] = {
> > + { TPS65224_IRQ_NAME_BUCK2_UVOV, "BUCK2", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_buck3_irq_types[] = {
> > + { TPS65224_IRQ_NAME_BUCK3_UVOV, "BUCK3", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_buck4_irq_types[] = {
> > + { TPS65224_IRQ_NAME_BUCK4_UVOV, "BUCK4", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_ldo1_irq_types[] = {
> > + { TPS65224_IRQ_NAME_LDO1_UVOV, "LDO1", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_ldo2_irq_types[] = {
> > + { TPS65224_IRQ_NAME_LDO2_UVOV, "LDO2", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > +static struct tps6594_regulator_irq_type tps65224_ldo3_irq_types[] = {
> > + { TPS65224_IRQ_NAME_LDO3_UVOV, "LDO3", "voltage out of range",
> > + REGULATOR_EVENT_REGULATION_OUT },
> > +};
> > +
> > static struct tps6594_regulator_irq_type *tps6594_bucks_irq_types[] = {
> > tps6594_buck1_irq_types,
> > tps6594_buck2_irq_types,
> > @@ -284,7 +381,20 @@ static struct tps6594_regulator_irq_type *tps6594_ldos_irq_types[] = {
> > tps6594_ldo4_irq_types,
> > };
> >
> > -static const struct regulator_desc multi_regs[] = {
> > +static struct tps6594_regulator_irq_type *tps65224_bucks_irq_types[] = {
> > + tps65224_buck1_irq_types,
> > + tps65224_buck2_irq_types,
> > + tps65224_buck3_irq_types,
> > + tps65224_buck4_irq_types,
> > +};
> > +
> > +static struct tps6594_regulator_irq_type *tps65224_ldos_irq_types[] = {
> > + tps65224_ldo1_irq_types,
> > + tps65224_ldo2_irq_types,
> > + tps65224_ldo3_irq_types,
> > +};
> > +
> > +static const struct regulator_desc tps6594_multi_regs[] = {
> > TPS6594_REGULATOR("BUCK12", "buck12", TPS6594_BUCK_1,
> > REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS6594_MASK_BUCKS_VSET,
> > TPS6594_REG_BUCKX_VOUT_1(1),
> > @@ -315,7 +425,17 @@ static const struct regulator_desc multi_regs[] = {
> > 4, 4000, 0, NULL, 0, 0),
> > };
> >
> > -static const struct regulator_desc ldo_regs[] = {
> > +static const struct regulator_desc tps65224_multi_regs[] = {
> > + TPS6594_REGULATOR("BUCK12", "buck12", TPS6594_BUCK_1,
> > + REGULATOR_VOLTAGE, tps6594_bucks_ops, TPS65224_MASK_BUCK1_VSET,
> > + TPS6594_REG_BUCKX_VOUT_1(0),
> > + TPS65224_MASK_BUCK1_VSET,
> > + TPS6594_REG_BUCKX_CTRL(0),
> > + TPS6594_BIT_BUCK_EN, 0, 0, tps65224_bucks_1_ranges,
> > + 4, 4000, 0, NULL, 0, 0),
> > +};
> > +
> > +static const struct regulator_desc tps6594_ldo_regs[] = {
> > TPS6594_REGULATOR("LDO1", "ldo1", TPS6594_LDO_1,
> > REGULATOR_VOLTAGE, tps6594_ldos_1_2_3_ops, TPS6594_MASK_LDO123_VSET,
> > TPS6594_REG_LDOX_VOUT(0),
> > @@ -346,6 +466,30 @@ static const struct regulator_desc ldo_regs[] = {
> > 1, 0, 0, NULL, 0, 0),
> > };
> >
> > +static const struct regulator_desc tps65224_ldo_regs[] = {
> > + TPS6594_REGULATOR("LDO1", "ldo1", TPS6594_LDO_1,
> > + REGULATOR_VOLTAGE, tps6594_ldos_1_2_3_ops, TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_VOUT(0),
> > + TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_CTRL(0),
> > + TPS6594_BIT_LDO_EN, 0, 0, tps65224_ldos_1_ranges,
> > + 1, 0, 0, NULL, 0, TPS6594_BIT_LDO_BYPASS),
> > + TPS6594_REGULATOR("LDO2", "ldo2", TPS6594_LDO_2,
> > + REGULATOR_VOLTAGE, tps6594_ldos_1_2_3_ops, TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_VOUT(1),
> > + TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_CTRL(1),
> > + TPS6594_BIT_LDO_EN, 0, 0, tps65224_ldos_2_3_ranges,
> > + 1, 0, 0, NULL, 0, TPS6594_BIT_LDO_BYPASS),
> > + TPS6594_REGULATOR("LDO3", "ldo3", TPS6594_LDO_3,
> > + REGULATOR_VOLTAGE, tps6594_ldos_1_2_3_ops, TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_VOUT(2),
> > + TPS6594_MASK_LDO123_VSET,
> > + TPS6594_REG_LDOX_CTRL(2),
> > + TPS6594_BIT_LDO_EN, 0, 0, tps65224_ldos_2_3_ranges,
> > + 1, 0, 0, NULL, 0, TPS6594_BIT_LDO_BYPASS),
> > +};
> > +
> > static irqreturn_t tps6594_regulator_irq_handler(int irq, void *data)
> > {
> > struct tps6594_regulator_irq_data *irq_data = data;
> > @@ -369,17 +513,18 @@ static irqreturn_t tps6594_regulator_irq_handler(int irq, void *data)
> > static int tps6594_request_reg_irqs(struct platform_device *pdev,
> > struct regulator_dev *rdev,
> > struct tps6594_regulator_irq_data *irq_data,
> > - struct tps6594_regulator_irq_type *tps6594_regs_irq_types,
> > + struct tps6594_regulator_irq_type *regs_irq_types,
> > + size_t interrupt_cnt,
> > int *irq_idx)
> > {
> > struct tps6594_regulator_irq_type *irq_type;
> > struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
> > - int j;
> > + size_t j;
> > int irq;
> > int error;
> >
> > - for (j = 0; j < REGS_INT_NB; j++) {
> > - irq_type = &tps6594_regs_irq_types[j];
> > + for (j = 0; j < interrupt_cnt; j++) {
> > + irq_type = ®s_irq_types[j];
> > irq = platform_get_irq_byname(pdev, irq_type->irq_name);
> > if (irq < 0)
> > return -EINVAL;
> > @@ -412,14 +557,38 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > struct tps6594_ext_regulator_irq_data *irq_ext_reg_data;
> > struct tps6594_regulator_irq_type *irq_type;
> > u8 buck_configured[BUCK_NB] = { 0 };
> > + u8 ldo_configured[LDO_NB] = { 0 };
>
> This should be bool and the related changes like using true/false.
>
> Actually, on reviewing this code even more, I really suggest you first
> do some clean up to this driver and then just change this to:
>
> int nr_ldo;
>
> Then use that instead of LDO_NB.
>
> buck_configured[] should be bool as well.
>
> > u8 buck_multi[MULTI_PHASE_NB] = { 0 };
> > - static const char * const multiphases[] = {"buck12", "buck123", "buck1234", "buck34"};
> > + static const char * const tps6594_multiphases[] = {"buck12", "buck123",
> > + "buck1234", "buck34"};
> > + static const char * const tps65224_multiphases[] = {"buck12"};
>
> The tps65224_multiphases[] array is never used except to get the
> ARRAY_SIZE(). Neither of these are necessary. Just use
> multi_regs[multi].supply_name instead.
>
>
> > static const char *npname;
> > int error, i, irq, multi, delta;
> > int irq_idx = 0;
> > int buck_idx = 0;
> > + unsigned int multi_phase_cnt = 0;
>
> No need to initialize this here.
>
> > size_t ext_reg_irq_nb = 2;
> > size_t reg_irq_nb;
> > + struct tps6594_regulator_irq_type **bucks_irq_types;
> > + const struct regulator_desc *multi_regs;
> > + struct tps6594_regulator_irq_type **ldos_irq_types;
> > + const struct regulator_desc *ldo_regs;
> > + size_t interrupt_count;
> > +
> > + if (tps->chip_id == TPS65224) {
> > + bucks_irq_types = tps65224_bucks_irq_types;
> > + interrupt_count = ARRAY_SIZE(tps65224_buck1_irq_types);
> > + multi_regs = tps65224_multi_regs;
> > + ldos_irq_types = tps65224_ldos_irq_types;
> > + ldo_regs = tps65224_ldo_regs;
> > + } else {
> > + bucks_irq_types = tps6594_bucks_irq_types;
> > + interrupt_count = ARRAY_SIZE(tps6594_buck1_irq_types);
> > + multi_regs = tps6594_multi_regs;
> > + ldos_irq_types = tps6594_ldos_irq_types;
> > + ldo_regs = tps6594_ldo_regs;
>
>
> Initialize multi_phase_cnt in this block with all the other variables
> instead of below.
>
> > + }
> > +
> > enum {
> > MULTI_BUCK12,
> > MULTI_BUCK123,
> > @@ -434,6 +603,10 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > config.driver_data = tps;
> > config.regmap = tps->regmap;
> >
> > + multi_phase_cnt = (tps->chip_id == TPS65224) ?
> > + ARRAY_SIZE(tps65224_multiphases) :
> > + ARRAY_SIZE(tps6594_multiphases);
> > +
> > /*
> > * Switch case defines different possible multi phase config
> > * This is based on dts buck node name.
> > @@ -442,13 +615,13 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > * In case of Multiphase configuration, value should be defined for
> > * buck_configured to avoid creating bucks for every buck in multiphase
> > */
> > - for (multi = MULTI_FIRST; multi < MULTI_NUM; multi++) {
> > - np = of_find_node_by_name(tps->dev->of_node, multiphases[multi]);
> > + for (multi = MULTI_FIRST; multi < multi_phase_cnt; multi++) {
> > + np = of_find_node_by_name(tps->dev->of_node, tps6594_multiphases[multi]);
>
> Use multi_regs[multi].supply_name here.
>
> > npname = of_node_full_name(np);
> > np_pmic_parent = of_get_parent(of_get_parent(np));
> > if (of_node_cmp(of_node_full_name(np_pmic_parent), tps->dev->of_node->full_name))
> > continue;
> > - delta = strcmp(npname, multiphases[multi]);
> > + delta = strcmp(npname, tps6594_multiphases[multi]);
> > if (!delta) {
>
> Unrelated to your patch but this should be:
>
> if (strcmp(npname, tps6594_multiphases[multi]) == 0) {
>
> The == means that the strings are equal. No need for a delta variable.
>
> > switch (multi) {
> > case MULTI_BUCK12:
> > @@ -486,6 +659,11 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > /* There is only 4 buck on LP8764 */
> > buck_configured[4] = 1;
> > reg_irq_nb = size_mul(REGS_INT_NB, (BUCK_NB - 1));
> > + } else if (tps->chip_id == TPS65224) {
> > + /* TPS65224 has 4 bucks and 3 LDOs. 1 Interrupt for each buck and ldo */
> > + buck_configured[4] = 1;
> > + ldo_configured[3] = 1;
> > + reg_irq_nb = size_mul(1, (size_add((BUCK_NB - 1), (LDO_NB - 1))));
> > } else {
> > reg_irq_nb = size_mul(REGS_INT_NB, (size_add(BUCK_NB, LDO_NB)));
>
> No need for size_add/mul(). These are small constants so it's not
> going to integer overflow.
>
> The other suggestion here would be to do a clean up of the driver first
> so instead of marking the last buck_configured[4] = 1; we would instead
> say "nr_buck = 4;" Then the math become easier and we can remove the
> comments and the confusing subtractions.
>
> if (tps->chip_id == LP8764) {
> nr_buck = 4;
> nr_ldo = 0;
> } else if (tps->chip_id == TPS65224) {
> nr_buck = ARRAY_SIZE(tps65224_buck_regs);
> nr_ldo = ARRAY_SIZE(tps65224_ldo_regs);
> } else {
> nr_buck = BUCK_NB; // FIXME. ARRAY_SIZE()
> nr_ldo = ARRAY_SIZE(tps6594_ldo_regs);
> }
>
> reg_irq_nb = multi_regs * (nr_buck + nr_ldo);
>
> > }
> > @@ -495,7 +673,7 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > if (!irq_data)
> > return -ENOMEM;
> >
> > - for (i = 0; i < MULTI_PHASE_NB; i++) {
> > + for (i = 0; i < multi_phase_cnt; i++) {
> > if (buck_multi[i] == 0)
> > continue;
> >
> > @@ -508,18 +686,23 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > /* config multiphase buck12+buck34 */
> > if (i == 1)
> > buck_idx = 2;
> > +
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > - tps6594_bucks_irq_types[buck_idx], &irq_idx);
> > + bucks_irq_types[buck_idx],
> > + interrupt_count, &irq_idx);
> > if (error)
> > return error;
> > +
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > - tps6594_bucks_irq_types[buck_idx + 1], &irq_idx);
> > + bucks_irq_types[buck_idx + 1],
> > + interrupt_count, &irq_idx);
> > if (error)
> > return error;
> >
> > if (i == 2 || i == 3) {
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > tps6594_bucks_irq_types[buck_idx + 2],
> > + interrupt_count,
> > &irq_idx);
> > if (error)
> > return error;
> > @@ -527,6 +710,7 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > if (i == 3) {
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > tps6594_bucks_irq_types[buck_idx + 3],
> > + interrupt_count,
> > &irq_idx);
> > if (error)
> > return error;
> > @@ -537,21 +721,26 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > if (buck_configured[i] == 1)
> > continue;
> >
> > - rdev = devm_regulator_register(&pdev->dev, &buck_regs[i], &config);
> > + const struct regulator_desc *buck_cfg = (tps->chip_id == TPS65224) ?
> > + tps65224_buck_regs : buck_regs;
> > +
> > + rdev = devm_regulator_register(&pdev->dev, &buck_cfg[i], &config);
> > if (IS_ERR(rdev))
> > return dev_err_probe(tps->dev, PTR_ERR(rdev),
> > - "failed to register %s regulator\n",
> > - pdev->name);
> > + "failed to register %s regulator\n", pdev->name);
>
> There are too many unrelated white space changes in this patch.
>
> >
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > - tps6594_bucks_irq_types[i], &irq_idx);
> > + bucks_irq_types[i], interrupt_count, &irq_idx);
> > if (error)
> > return error;
> > }
> >
> > - /* LP8764 dosen't have LDO */
> > + /* LP8764 doesn't have LDO */
> > if (tps->chip_id != LP8764) {
> > - for (i = 0; i < ARRAY_SIZE(ldo_regs); i++) {
> > + for (i = 0; i < LDO_NB; i++) {
> > + if (ldo_configured[i] == 1)
> > + continue;
> > +
>
> Now that we have introduced a nr_ldo variable we can delete the
> /* LP8764 doesn't have LDO */ comment and the if LP8764 statement and
> the if (ldo_configured[i] == 1) condition.
>
> for (i = 0; i < nr_ldo; i++) {
> rdev = devm_regulator_register(&pdev->dev, &ldo_regs[i], &config);
>
> The BUCK loop would only loop nr_buck times as well.
>
> > rdev = devm_regulator_register(&pdev->dev, &ldo_regs[i], &config);
> > if (IS_ERR(rdev))
> > return dev_err_probe(tps->dev, PTR_ERR(rdev),
> > @@ -559,7 +748,7 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> > pdev->name);
> >
> > error = tps6594_request_reg_irqs(pdev, rdev, irq_data,
> > - tps6594_ldos_irq_types[i],
> > + ldos_irq_types[i], interrupt_count,
> > &irq_idx);
> > if (error)
> > return error;
> > @@ -568,16 +757,21 @@ static int tps6594_regulator_probe(struct platform_device *pdev)
> >
> > if (tps->chip_id == LP8764)
> > ext_reg_irq_nb = ARRAY_SIZE(tps6594_ext_regulator_irq_types);
> > + else if (tps->chip_id == TPS65224)
> > + ext_reg_irq_nb = ARRAY_SIZE(tps65224_ext_regulator_irq_types);
>
> Declare an irq_types pointer.
>
> if (tps->chip_id == TPS65224) {
> irq_types = tps65224_ext_regulator_irq_types;
> irq_count = ARRAY_SIZE(tps65224_ext_regulator_irq_types);
> } else {
> irq_types = tps6594_ext_regulator_irq_types;
> if (tps->chip_id == LP8764)
> irq_count = ARRAY_SIZE(tps6594_ext_regulator_irq_types);
> else
> irq_count = 2;
> }
>
> >
> > irq_ext_reg_data = devm_kmalloc_array(tps->dev,
> > - ext_reg_irq_nb,
> > - sizeof(struct tps6594_ext_regulator_irq_data),
> > - GFP_KERNEL);
> > + ext_reg_irq_nb,
> > + sizeof(struct tps6594_ext_regulator_irq_data),
> > + GFP_KERNEL);
>
> Unrelated.
>
> > if (!irq_ext_reg_data)
> > return -ENOMEM;
> >
> > for (i = 0; i < ext_reg_irq_nb; ++i) {
> > - irq_type = &tps6594_ext_regulator_irq_types[i];
> > + if (tps->chip_id == TPS65224)
> > + irq_type = &tps65224_ext_regulator_irq_types[i];
> > + else
> > + irq_type = &tps6594_ext_regulator_irq_types[i];
> >
> > irq = platform_get_irq_byname(pdev, irq_type->irq_name);
> > if (irq < 0)
>
> regards,
> dan carpenter
Thanks for all the feedback and suggestions.
We will modify accordingly in the next version.
Regards,
Bhargav
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* [PATCH v8 00/10] Add support for TI TPS65224 PMIC
From: Bhargav Raviprakash @ 2024-04-30 13:14 UTC (permalink / raw)
To: linux-kernel
Cc: m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
jpanis, devicetree, arnd, gregkh, lgirdwood, broonie,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc, Bhargav Raviprakash
This series modifies the existing TPS6594 drivers to add support for the
TPS65224 PMIC device that is a derivative of TPS6594. TPS65224 has a
similar register map to TPS6594 with a few differences. SPI, I2C, ESM,
PFSM, Regulators and GPIO features overlap between the two devices.
TPS65224 is a Power Management IC (PMIC) which provides regulators and
other features like GPIOs, Watchdog, Error Signal Monitor (ESM) and
Pre-configurable Finite State Machine (PFSM). The SoC and the PMIC can
communicate through the I2C or SPI interfaces. The PMIC TPS65224
additionally has a 12-bit ADC.
Data Sheet for TPS65224: https://www.ti.com/product/TPS65224-Q1
Driver re-use is applied following the advice of the following series:
https://lore.kernel.org/lkml/2f467b0a-1d11-4ec7-8ca6-6c4ba66e5887@baylibre.com/
The features implemented in this series are:
- TPS65224 Register definitions
- Core (MFD I2C and SPI entry points)
- PFSM
- Regulators
- Pinctrl
TPS65224 Register definitions:
This patch adds macros for register field definitions of TPS65224
to the existing TPS6594 driver.
Core description:
I2C and SPI interface protocols are implemented, with and without
the bit-integrity error detection feature (CRC mode).
PFSM description:
Strictly speaking, PFSM is not hardware. It is a piece of code.
PMIC integrates a state machine which manages operational modes.
Depending on the current operational mode, some voltage domains
remain energized while others can be off.
PFSM driver can be used to trigger transitions between configured
states.
Regulators description:
4 BUCKs and 3 LDOs.
BUCK12 can be used in dual-phase mode.
Pinctrl description:
TPS65224 family has 6 GPIOs. Those GPIOs can also serve different
functions such as I2C or SPI interface or watchdog disable functions.
The driver provides both pinmuxing for the functions and GPIO capability.
This series was tested on linux-next tag: next-20240118
Test logs can be found here:
https://gist.github.com/LeonardMH/58ec135921fb1062ffd4a8b384831eb0
Changelog v7 -> v8:
- Refactoring regulator driver
Bhargav Raviprakash (7):
mfd: tps6594: use volatile_table instead of volatile_reg
dt-bindings: mfd: ti,tps6594: Add TI TPS65224 PMIC
mfd: tps6594-i2c: Add TI TPS65224 PMIC I2C
mfd: tps6594-spi: Add TI TPS65224 PMIC SPI
mfd: tps6594-core: Add TI TPS65224 PMIC core
misc: tps6594-pfsm: Add TI TPS65224 PMIC PFSM
arch: arm64: dts: ti: k3-am62p5-sk: Add TPS65224 PMIC support in AM62P
dts
Nirmala Devi Mal Nadar (3):
mfd: tps6594: Add register definitions for TI TPS65224 PMIC
regulator: tps6594-regulator: Add TI TPS65224 PMIC regulators
pinctrl: pinctrl-tps6594: Add TPS65224 PMIC pinctrl and GPIO
.../devicetree/bindings/mfd/ti,tps6594.yaml | 1 +
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 95 +++++
drivers/mfd/tps6594-core.c | 253 +++++++++++--
drivers/mfd/tps6594-i2c.c | 20 +-
drivers/mfd/tps6594-spi.c | 20 +-
drivers/misc/tps6594-pfsm.c | 48 ++-
drivers/pinctrl/pinctrl-tps6594.c | 277 +++++++++++---
drivers/regulator/Kconfig | 4 +-
drivers/regulator/tps6594-regulator.c | 334 +++++++++++++----
include/linux/mfd/tps6594.h | 351 +++++++++++++++++-
10 files changed, 1215 insertions(+), 188 deletions(-)
base-commit: 2863b714f3ad0a9686f2de1b779228ad8c7a8052
--
2.25.1
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* [PATCH v4] arm64: dts: ti: k3-j721e-sk: Add support for multiple CAN instances
From: Beleswar Padhi @ 2024-04-30 13:15 UTC (permalink / raw)
To: nm
Cc: vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel, b-kapoor, u-kumar1
CAN instance 0 in the mcu domain is brought on the J721E-SK board
through header J1. Thus, add its respective transceiver 1 dt node to add
support for this CAN instance.
CAN instances 0, 5 and 9 in the main domain are brought on the J721E-SK
board through headers J5, J6 and J2 respectively. Thus, add their
respective transceivers 2, 3 and 4 dt nodes to add support for these CAN
instances.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
---
Test logs: https://gist.github.com/3V3RYONE/2144fa883bf3a390981d25572971fcf3
v4: Changelog:
1) Made transceiver ID and can-phy ID in sync for all applicable nodes
Link to v3:
https://lore.kernel.org/all/20240412112025.201639-1-b-padhi@ti.com/
v3: Changelog:
1) Updated board name in capital letters in commit message description
2) Updated test logs to include communication between all applicable CAN
instances
Link to v2:
https://lore.kernel.org/linux-arm-kernel/20240325103405.182692-1-b-padhi@ti.com/
v2: Changelog:
1) Re-ordered status = "okay" property to the end of all applicable dt
nodes following kernel documentation
Link to v1:
https://lore.kernel.org/linux-arm-kernel/20240315124728.490331-1-b-padhi@ti.com/
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 116 +++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 0c4575ad8d7c..02e6c49b7090 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -210,6 +210,42 @@ vdd_sd_dv_alt: gpio-regulator-tps659411 {
<3300000 0x1>;
};
+ transceiver1: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver4: can-phy4 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan9_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
+ };
+
dp_pwr_3v3: fixedregulator-dp-prw {
compatible = "regulator-fixed";
regulator-name = "dp-pwr";
@@ -367,6 +403,45 @@ J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
>;
};
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
+ >;
+ };
+
+ main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
+ >;
+ };
+
+ main_mcan5_pins_default: main-mcan5-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
+ J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
+ >;
+ };
+
+ main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
+ >;
+ };
+
+ main_mcan9_pins_default: main-mcan9-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
+ J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
+ >;
+ };
+
+ main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
+ >;
+ };
+
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
@@ -555,6 +630,19 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+ J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
+ >;
+ };
+
/* Reset for M.2 M Key slot on PCIe1 */
mkey_reset_pins_default: mkey-reset-pns-default-pins {
pinctrl-single,pins = <
@@ -1108,6 +1196,34 @@ &pcie1_rc {
num-lanes = <2>;
};
+&mcu_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
+ status = "okay";
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&transceiver2>;
+ status = "okay";
+};
+
+&main_mcan5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_pins_default>;
+ phys = <&transceiver3>;
+ status = "okay";
+};
+
+&main_mcan9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan9_pins_default>;
+ phys = <&transceiver4>;
+ status = "okay";
+};
+
&ufs_wrapper {
status = "disabled";
};
--
2.34.1
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* [PATCH v8 01/10] mfd: tps6594: Add register definitions for TI TPS65224 PMIC
From: Bhargav Raviprakash @ 2024-04-30 13:16 UTC (permalink / raw)
To: linux-kernel
Cc: m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
jpanis, devicetree, arnd, gregkh, lgirdwood, broonie,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc, Bhargav Raviprakash
In-Reply-To: <0109018f2f24c15e-c50bfc29-5f1d-4368-a4b8-2c9f1d398abb-000000@ap-south-1.amazonses.com>
From: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
Extend TPS6594 PMIC register and field definitions to support TPS65224
power management IC.
TPS65224 is software compatible to TPS6594 and can re-use many of the
same definitions, new definitions are added to support additional
controls available on TPS65224.
Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
---
include/linux/mfd/tps6594.h | 347 ++++++++++++++++++++++++++++++++++--
1 file changed, 335 insertions(+), 12 deletions(-)
diff --git a/include/linux/mfd/tps6594.h b/include/linux/mfd/tps6594.h
index 3f7c5e23c..e754c01ac 100644
--- a/include/linux/mfd/tps6594.h
+++ b/include/linux/mfd/tps6594.h
@@ -18,12 +18,13 @@ enum pmic_id {
TPS6594,
TPS6593,
LP8764,
+ TPS65224,
};
/* Macro to get page index from register address */
#define TPS6594_REG_TO_PAGE(reg) ((reg) >> 8)
-/* Registers for page 0 of TPS6594 */
+/* Registers for page 0 */
#define TPS6594_REG_DEV_REV 0x01
#define TPS6594_REG_NVM_CODE_1 0x02
@@ -56,9 +57,6 @@ enum pmic_id {
#define TPS6594_REG_GPIOX_OUT(gpio_inst) (TPS6594_REG_GPIO_OUT_1 + (gpio_inst) / 8)
#define TPS6594_REG_GPIOX_IN(gpio_inst) (TPS6594_REG_GPIO_IN_1 + (gpio_inst) / 8)
-#define TPS6594_REG_GPIO_IN_1 0x3f
-#define TPS6594_REG_GPIO_IN_2 0x40
-
#define TPS6594_REG_RAIL_SEL_1 0x41
#define TPS6594_REG_RAIL_SEL_2 0x42
#define TPS6594_REG_RAIL_SEL_3 0x43
@@ -70,13 +68,15 @@ enum pmic_id {
#define TPS6594_REG_FSM_TRIG_MASK_3 0x48
#define TPS6594_REG_MASK_BUCK1_2 0x49
+#define TPS65224_REG_MASK_BUCKS 0x49
#define TPS6594_REG_MASK_BUCK3_4 0x4a
#define TPS6594_REG_MASK_BUCK5 0x4b
#define TPS6594_REG_MASK_LDO1_2 0x4c
+#define TPS65224_REG_MASK_LDOS 0x4c
#define TPS6594_REG_MASK_LDO3_4 0x4d
#define TPS6594_REG_MASK_VMON 0x4e
-#define TPS6594_REG_MASK_GPIO1_8_FALL 0x4f
-#define TPS6594_REG_MASK_GPIO1_8_RISE 0x50
+#define TPS6594_REG_MASK_GPIO_FALL 0x4f
+#define TPS6594_REG_MASK_GPIO_RISE 0x50
#define TPS6594_REG_MASK_GPIO9_11 0x51
#define TPS6594_REG_MASK_STARTUP 0x52
#define TPS6594_REG_MASK_MISC 0x53
@@ -174,6 +174,10 @@ enum pmic_id {
#define TPS6594_REG_REGISTER_LOCK 0xa1
+#define TPS65224_REG_SRAM_ACCESS_1 0xa2
+#define TPS65224_REG_SRAM_ACCESS_2 0xa3
+#define TPS65224_REG_SRAM_ADDR_CTRL 0xa4
+#define TPS65224_REG_RECOV_CNT_PFSM_INCR 0xa5
#define TPS6594_REG_MANUFACTURING_VER 0xa6
#define TPS6594_REG_CUSTOMER_NVM_ID_REG 0xa7
@@ -182,6 +186,9 @@ enum pmic_id {
#define TPS6594_REG_SOFT_REBOOT_REG 0xab
+#define TPS65224_REG_ADC_CTRL 0xac
+#define TPS65224_REG_ADC_RESULT_REG_1 0xad
+#define TPS65224_REG_ADC_RESULT_REG_2 0xae
#define TPS6594_REG_RTC_SECONDS 0xb5
#define TPS6594_REG_RTC_MINUTES 0xb6
#define TPS6594_REG_RTC_HOURS 0xb7
@@ -199,6 +206,7 @@ enum pmic_id {
#define TPS6594_REG_RTC_CTRL_1 0xc2
#define TPS6594_REG_RTC_CTRL_2 0xc3
+#define TPS65224_REG_STARTUP_CTRL 0xc3
#define TPS6594_REG_RTC_STATUS 0xc4
#define TPS6594_REG_RTC_INTERRUPTS 0xc5
#define TPS6594_REG_RTC_COMP_LSB 0xc6
@@ -214,13 +222,17 @@ enum pmic_id {
#define TPS6594_REG_PFSM_DELAY_REG_2 0xce
#define TPS6594_REG_PFSM_DELAY_REG_3 0xcf
#define TPS6594_REG_PFSM_DELAY_REG_4 0xd0
+#define TPS65224_REG_ADC_GAIN_COMP_REG 0xd0
+#define TPS65224_REG_CRC_CALC_CONTROL 0xef
+#define TPS65224_REG_REGMAP_USER_CRC_LOW 0xf0
+#define TPS65224_REG_REGMAP_USER_CRC_HIGH 0xf1
-/* Registers for page 1 of TPS6594 */
+/* Registers for page 1 */
#define TPS6594_REG_SERIAL_IF_CONFIG 0x11a
#define TPS6594_REG_I2C1_ID 0x122
#define TPS6594_REG_I2C2_ID 0x123
-/* Registers for page 4 of TPS6594 */
+/* Registers for page 4 */
#define TPS6594_REG_WD_ANSWER_REG 0x401
#define TPS6594_REG_WD_QUESTION_ANSW_CNT 0x402
#define TPS6594_REG_WD_WIN1_CFG 0x403
@@ -241,16 +253,26 @@ enum pmic_id {
#define TPS6594_BIT_BUCK_PLDN BIT(5)
#define TPS6594_BIT_BUCK_RV_SEL BIT(7)
-/* BUCKX_CONF register field definition */
+/* TPS6594 BUCKX_CONF register field definition */
#define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)
#define TPS6594_MASK_BUCK_ILIM GENMASK(5, 3)
-/* BUCKX_PG_WINDOW register field definition */
+/* TPS65224 BUCKX_CONF register field definition */
+#define TPS65224_MASK_BUCK_SLEW_RATE GENMASK(1, 0)
+
+/* TPS6594 BUCKX_PG_WINDOW register field definition */
#define TPS6594_MASK_BUCK_OV_THR GENMASK(2, 0)
#define TPS6594_MASK_BUCK_UV_THR GENMASK(5, 3)
-/* BUCKX VSET */
-#define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
+/* TPS65224 BUCKX_PG_WINDOW register field definition */
+#define TPS65224_MASK_BUCK_VMON_THR GENMASK(1, 0)
+
+/* TPS6594 BUCKX_VOUT register field definition */
+#define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
+
+/* TPS65224 BUCKX_VOUT register field definition */
+#define TPS65224_MASK_BUCK1_VSET GENMASK(7, 0)
+#define TPS65224_MASK_BUCKS_VSET GENMASK(6, 0)
/* LDOX_CTRL register field definition */
#define TPS6594_BIT_LDO_EN BIT(0)
@@ -258,6 +280,7 @@ enum pmic_id {
#define TPS6594_BIT_LDO_VMON_EN BIT(4)
#define TPS6594_MASK_LDO_PLDN GENMASK(6, 5)
#define TPS6594_BIT_LDO_RV_SEL BIT(7)
+#define TPS65224_BIT_LDO_DISCHARGE_EN BIT(5)
/* LDORTC_CTRL register field definition */
#define TPS6594_BIT_LDORTC_DIS BIT(0)
@@ -271,6 +294,9 @@ enum pmic_id {
#define TPS6594_MASK_LDO_OV_THR GENMASK(2, 0)
#define TPS6594_MASK_LDO_UV_THR GENMASK(5, 3)
+/* LDOX_PG_WINDOW register field definition */
+#define TPS65224_MASK_LDO_VMON_THR GENMASK(1, 0)
+
/* VCCA_VMON_CTRL register field definition */
#define TPS6594_BIT_VMON_EN BIT(0)
#define TPS6594_BIT_VMON1_EN BIT(1)
@@ -278,10 +304,12 @@ enum pmic_id {
#define TPS6594_BIT_VMON2_EN BIT(3)
#define TPS6594_BIT_VMON2_RV_SEL BIT(4)
#define TPS6594_BIT_VMON_DEGLITCH_SEL BIT(5)
+#define TPS65224_BIT_VMON_DEGLITCH_SEL GENMASK(7, 5)
/* VCCA_PG_WINDOW register field definition */
#define TPS6594_MASK_VCCA_OV_THR GENMASK(2, 0)
#define TPS6594_MASK_VCCA_UV_THR GENMASK(5, 3)
+#define TPS65224_MASK_VCCA_VMON_THR GENMASK(1, 0)
#define TPS6594_BIT_VCCA_PG_SET BIT(6)
/* VMONX_PG_WINDOW register field definition */
@@ -289,6 +317,9 @@ enum pmic_id {
#define TPS6594_MASK_VMONX_UV_THR GENMASK(5, 3)
#define TPS6594_BIT_VMONX_RANGE BIT(6)
+/* VMONX_PG_WINDOW register field definition */
+#define TPS65224_MASK_VMONX_THR GENMASK(1, 0)
+
/* GPIOX_CONF register field definition */
#define TPS6594_BIT_GPIO_DIR BIT(0)
#define TPS6594_BIT_GPIO_OD BIT(1)
@@ -296,6 +327,8 @@ enum pmic_id {
#define TPS6594_BIT_GPIO_PU_PD_EN BIT(3)
#define TPS6594_BIT_GPIO_DEGLITCH_EN BIT(4)
#define TPS6594_MASK_GPIO_SEL GENMASK(7, 5)
+#define TPS65224_MASK_GPIO_SEL GENMASK(6, 5)
+#define TPS65224_MASK_GPIO_SEL_GPIO6 GENMASK(7, 5)
/* NPWRON_CONF register field definition */
#define TPS6594_BIT_NRSTOUT_OD BIT(0)
@@ -305,6 +338,12 @@ enum pmic_id {
#define TPS6594_BIT_ENABLE_POL BIT(5)
#define TPS6594_MASK_NPWRON_SEL GENMASK(7, 6)
+/* POWER_ON_CONFIG register field definition */
+#define TPS65224_BIT_NINT_ENDRV_PU_SEL BIT(0)
+#define TPS65224_BIT_NINT_ENDRV_SEL BIT(1)
+#define TPS65224_BIT_EN_PB_DEGL BIT(5)
+#define TPS65224_MASK_EN_PB_VSENSE_CONFIG GENMASK(7, 6)
+
/* GPIO_OUT_X register field definition */
#define TPS6594_BIT_GPIOX_OUT(gpio_inst) BIT((gpio_inst) % 8)
@@ -312,6 +351,12 @@ enum pmic_id {
#define TPS6594_BIT_GPIOX_IN(gpio_inst) BIT((gpio_inst) % 8)
#define TPS6594_BIT_NPWRON_IN BIT(3)
+/* GPIO_OUT_X register field definition */
+#define TPS65224_BIT_GPIOX_OUT(gpio_inst) BIT((gpio_inst))
+
+/* GPIO_IN_X register field definition */
+#define TPS65224_BIT_GPIOX_IN(gpio_inst) BIT((gpio_inst))
+
/* RAIL_SEL_1 register field definition */
#define TPS6594_MASK_BUCK1_GRP_SEL GENMASK(1, 0)
#define TPS6594_MASK_BUCK2_GRP_SEL GENMASK(3, 2)
@@ -343,6 +388,9 @@ enum pmic_id {
#define TPS6594_BIT_GPIOX_FSM_MASK(gpio_inst) BIT(((gpio_inst) << 1) % 8)
#define TPS6594_BIT_GPIOX_FSM_MASK_POL(gpio_inst) BIT(((gpio_inst) << 1) % 8 + 1)
+#define TPS65224_BIT_GPIOX_FSM_MASK(gpio_inst) BIT(((gpio_inst) << 1) % 6)
+#define TPS65224_BIT_GPIOX_FSM_MASK_POL(gpio_inst) BIT(((gpio_inst) << 1) % 6 + 1)
+
/* MASK_BUCKX register field definition */
#define TPS6594_BIT_BUCKX_OV_MASK(buck_inst) BIT(((buck_inst) << 2) % 8)
#define TPS6594_BIT_BUCKX_UV_MASK(buck_inst) BIT(((buck_inst) << 2) % 8 + 1)
@@ -361,22 +409,46 @@ enum pmic_id {
#define TPS6594_BIT_VMON2_OV_MASK BIT(5)
#define TPS6594_BIT_VMON2_UV_MASK BIT(6)
+/* MASK_BUCK Register field definition */
+#define TPS65224_BIT_BUCK1_UVOV_MASK BIT(0)
+#define TPS65224_BIT_BUCK2_UVOV_MASK BIT(1)
+#define TPS65224_BIT_BUCK3_UVOV_MASK BIT(2)
+#define TPS65224_BIT_BUCK4_UVOV_MASK BIT(4)
+
+/* MASK_LDO_VMON register field definition */
+#define TPS65224_BIT_LDO1_UVOV_MASK BIT(0)
+#define TPS65224_BIT_LDO2_UVOV_MASK BIT(1)
+#define TPS65224_BIT_LDO3_UVOV_MASK BIT(2)
+#define TPS65224_BIT_VCCA_UVOV_MASK BIT(4)
+#define TPS65224_BIT_VMON1_UVOV_MASK BIT(5)
+#define TPS65224_BIT_VMON2_UVOV_MASK BIT(6)
+
/* MASK_GPIOX register field definition */
#define TPS6594_BIT_GPIOX_FALL_MASK(gpio_inst) BIT((gpio_inst) < 8 ? \
(gpio_inst) : (gpio_inst) % 8)
#define TPS6594_BIT_GPIOX_RISE_MASK(gpio_inst) BIT((gpio_inst) < 8 ? \
(gpio_inst) : (gpio_inst) % 8 + 3)
+/* MASK_GPIOX register field definition */
+#define TPS65224_BIT_GPIOX_FALL_MASK(gpio_inst) BIT((gpio_inst))
+#define TPS65224_BIT_GPIOX_RISE_MASK(gpio_inst) BIT((gpio_inst))
/* MASK_STARTUP register field definition */
#define TPS6594_BIT_NPWRON_START_MASK BIT(0)
#define TPS6594_BIT_ENABLE_MASK BIT(1)
#define TPS6594_BIT_FSD_MASK BIT(4)
#define TPS6594_BIT_SOFT_REBOOT_MASK BIT(5)
+#define TPS65224_BIT_VSENSE_MASK BIT(0)
+#define TPS65224_BIT_PB_SHORT_MASK BIT(2)
/* MASK_MISC register field definition */
#define TPS6594_BIT_BIST_PASS_MASK BIT(0)
#define TPS6594_BIT_EXT_CLK_MASK BIT(1)
+#define TPS65224_BIT_REG_UNLOCK_MASK BIT(2)
#define TPS6594_BIT_TWARN_MASK BIT(3)
+#define TPS65224_BIT_PB_LONG_MASK BIT(4)
+#define TPS65224_BIT_PB_FALL_MASK BIT(5)
+#define TPS65224_BIT_PB_RISE_MASK BIT(6)
+#define TPS65224_BIT_ADC_CONV_READY_MASK BIT(7)
/* MASK_MODERATE_ERR register field definition */
#define TPS6594_BIT_BIST_FAIL_MASK BIT(1)
@@ -391,6 +463,8 @@ enum pmic_id {
#define TPS6594_BIT_ORD_SHUTDOWN_MASK BIT(1)
#define TPS6594_BIT_MCU_PWR_ERR_MASK BIT(2)
#define TPS6594_BIT_SOC_PWR_ERR_MASK BIT(3)
+#define TPS65224_BIT_COMM_ERR_MASK BIT(4)
+#define TPS65224_BIT_I2C2_ERR_MASK BIT(5)
/* MASK_COMM_ERR register field definition */
#define TPS6594_BIT_COMM_FRM_ERR_MASK BIT(0)
@@ -426,6 +500,12 @@ enum pmic_id {
#define TPS6594_BIT_BUCK3_4_INT BIT(1)
#define TPS6594_BIT_BUCK5_INT BIT(2)
+/* INT_BUCK register field definition */
+#define TPS65224_BIT_BUCK1_UVOV_INT BIT(0)
+#define TPS65224_BIT_BUCK2_UVOV_INT BIT(1)
+#define TPS65224_BIT_BUCK3_UVOV_INT BIT(2)
+#define TPS65224_BIT_BUCK4_UVOV_INT BIT(3)
+
/* INT_BUCKX register field definition */
#define TPS6594_BIT_BUCKX_OV_INT(buck_inst) BIT(((buck_inst) << 2) % 8)
#define TPS6594_BIT_BUCKX_UV_INT(buck_inst) BIT(((buck_inst) << 2) % 8 + 1)
@@ -437,6 +517,14 @@ enum pmic_id {
#define TPS6594_BIT_LDO3_4_INT BIT(1)
#define TPS6594_BIT_VCCA_INT BIT(4)
+/* INT_LDO_VMON register field definition */
+#define TPS65224_BIT_LDO1_UVOV_INT BIT(0)
+#define TPS65224_BIT_LDO2_UVOV_INT BIT(1)
+#define TPS65224_BIT_LDO3_UVOV_INT BIT(2)
+#define TPS65224_BIT_VCCA_UVOV_INT BIT(4)
+#define TPS65224_BIT_VMON1_UVOV_INT BIT(5)
+#define TPS65224_BIT_VMON2_UVOV_INT BIT(6)
+
/* INT_LDOX register field definition */
#define TPS6594_BIT_LDOX_OV_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8)
#define TPS6594_BIT_LDOX_UV_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 1)
@@ -462,17 +550,32 @@ enum pmic_id {
/* INT_GPIOX register field definition */
#define TPS6594_BIT_GPIOX_INT(gpio_inst) BIT(gpio_inst)
+/* INT_GPIO register field definition */
+#define TPS65224_BIT_GPIO1_INT BIT(0)
+#define TPS65224_BIT_GPIO2_INT BIT(1)
+#define TPS65224_BIT_GPIO3_INT BIT(2)
+#define TPS65224_BIT_GPIO4_INT BIT(3)
+#define TPS65224_BIT_GPIO5_INT BIT(4)
+#define TPS65224_BIT_GPIO6_INT BIT(5)
+
/* INT_STARTUP register field definition */
#define TPS6594_BIT_NPWRON_START_INT BIT(0)
+#define TPS65224_BIT_VSENSE_INT BIT(0)
#define TPS6594_BIT_ENABLE_INT BIT(1)
#define TPS6594_BIT_RTC_INT BIT(2)
+#define TPS65224_BIT_PB_SHORT_INT BIT(2)
#define TPS6594_BIT_FSD_INT BIT(4)
#define TPS6594_BIT_SOFT_REBOOT_INT BIT(5)
/* INT_MISC register field definition */
#define TPS6594_BIT_BIST_PASS_INT BIT(0)
#define TPS6594_BIT_EXT_CLK_INT BIT(1)
+#define TPS65224_BIT_REG_UNLOCK_INT BIT(2)
#define TPS6594_BIT_TWARN_INT BIT(3)
+#define TPS65224_BIT_PB_LONG_INT BIT(4)
+#define TPS65224_BIT_PB_FALL_INT BIT(5)
+#define TPS65224_BIT_PB_RISE_INT BIT(6)
+#define TPS65224_BIT_ADC_CONV_READY_INT BIT(7)
/* INT_MODERATE_ERR register field definition */
#define TPS6594_BIT_TSD_ORD_INT BIT(0)
@@ -488,6 +591,7 @@ enum pmic_id {
#define TPS6594_BIT_TSD_IMM_INT BIT(0)
#define TPS6594_BIT_VCCA_OVP_INT BIT(1)
#define TPS6594_BIT_PFSM_ERR_INT BIT(2)
+#define TPS65224_BIT_BG_XMON_INT BIT(3)
/* INT_FSM_ERR register field definition */
#define TPS6594_BIT_IMM_SHUTDOWN_INT BIT(0)
@@ -496,6 +600,7 @@ enum pmic_id {
#define TPS6594_BIT_SOC_PWR_ERR_INT BIT(3)
#define TPS6594_BIT_COMM_ERR_INT BIT(4)
#define TPS6594_BIT_READBACK_ERR_INT BIT(5)
+#define TPS65224_BIT_I2C2_ERR_INT BIT(5)
#define TPS6594_BIT_ESM_INT BIT(6)
#define TPS6594_BIT_WD_INT BIT(7)
@@ -536,8 +641,18 @@ enum pmic_id {
#define TPS6594_BIT_VMON2_OV_STAT BIT(5)
#define TPS6594_BIT_VMON2_UV_STAT BIT(6)
+/* STAT_LDO_VMON register field definition */
+#define TPS65224_BIT_LDO1_UVOV_STAT BIT(0)
+#define TPS65224_BIT_LDO2_UVOV_STAT BIT(1)
+#define TPS65224_BIT_LDO3_UVOV_STAT BIT(2)
+#define TPS65224_BIT_VCCA_UVOV_STAT BIT(4)
+#define TPS65224_BIT_VMON1_UVOV_STAT BIT(5)
+#define TPS65224_BIT_VMON2_UVOV_STAT BIT(6)
+
/* STAT_STARTUP register field definition */
+#define TPS65224_BIT_VSENSE_STAT BIT(0)
#define TPS6594_BIT_ENABLE_STAT BIT(1)
+#define TPS65224_BIT_PB_LEVEL_STAT BIT(2)
/* STAT_MISC register field definition */
#define TPS6594_BIT_EXT_CLK_STAT BIT(1)
@@ -549,6 +664,7 @@ enum pmic_id {
/* STAT_SEVERE_ERR register field definition */
#define TPS6594_BIT_TSD_IMM_STAT BIT(0)
#define TPS6594_BIT_VCCA_OVP_STAT BIT(1)
+#define TPS65224_BIT_BG_XMON_STAT BIT(3)
/* STAT_READBACK_ERR register field definition */
#define TPS6594_BIT_EN_DRV_READBACK_STAT BIT(0)
@@ -597,6 +713,8 @@ enum pmic_id {
#define TPS6594_BIT_BB_CHARGER_EN BIT(0)
#define TPS6594_BIT_BB_ICHR BIT(1)
#define TPS6594_MASK_BB_VEOC GENMASK(3, 2)
+#define TPS65224_BIT_I2C1_SPI_CRC_EN BIT(4)
+#define TPS65224_BIT_I2C2_CRC_EN BIT(5)
#define TPS6594_BB_EOC_RDY BIT(7)
/* ENABLE_DRV_REG register field definition */
@@ -617,6 +735,7 @@ enum pmic_id {
#define TPS6594_BIT_NRSTOUT_SOC_IN BIT(2)
#define TPS6594_BIT_FORCE_EN_DRV_LOW BIT(3)
#define TPS6594_BIT_SPMI_LPM_EN BIT(4)
+#define TPS65224_BIT_TSD_DISABLE BIT(5)
/* RECOV_CNT_REG_1 register field definition */
#define TPS6594_MASK_RECOV_CNT GENMASK(3, 0)
@@ -671,15 +790,27 @@ enum pmic_id {
/* ESM_SOC_START_REG register field definition */
#define TPS6594_BIT_ESM_SOC_START BIT(0)
+/* ESM_MCU_START_REG register field definition */
+#define TPS65224_BIT_ESM_MCU_START BIT(0)
+
/* ESM_SOC_MODE_CFG register field definition */
#define TPS6594_MASK_ESM_SOC_ERR_CNT_TH GENMASK(3, 0)
#define TPS6594_BIT_ESM_SOC_ENDRV BIT(5)
#define TPS6594_BIT_ESM_SOC_EN BIT(6)
#define TPS6594_BIT_ESM_SOC_MODE BIT(7)
+/* ESM_MCU_MODE_CFG register field definition */
+#define TPS65224_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)
+#define TPS65224_BIT_ESM_MCU_ENDRV BIT(5)
+#define TPS65224_BIT_ESM_MCU_EN BIT(6)
+#define TPS65224_BIT_ESM_MCU_MODE BIT(7)
+
/* ESM_SOC_ERR_CNT_REG register field definition */
#define TPS6594_MASK_ESM_SOC_ERR_CNT GENMASK(4, 0)
+/* ESM_MCU_ERR_CNT_REG register field definition */
+#define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)
+
/* REGISTER_LOCK register field definition */
#define TPS6594_BIT_REGISTER_LOCK_STATUS BIT(0)
@@ -687,6 +818,29 @@ enum pmic_id {
#define TPS6594_MASK_VMON1_SLEW_RATE GENMASK(2, 0)
#define TPS6594_MASK_VMON2_SLEW_RATE GENMASK(5, 3)
+/* SRAM_ACCESS_1 Register field definition */
+#define TPS65224_MASk_SRAM_UNLOCK_SEQ GENMASK(7, 0)
+
+/* SRAM_ACCESS_2 Register field definition */
+#define TPS65224_BIT_SRAM_WRITE_MODE BIT(0)
+#define TPS65224_BIT_OTP_PROG_USER BIT(1)
+#define TPS65224_BIT_OTP_PROG_PFSM BIT(2)
+#define TPS65224_BIT_OTP_PROG_STATUS BIT(3)
+#define TPS65224_BIT_SRAM_UNLOCKED BIT(6)
+#define TPS65224_USER_PROG_ALLOWED BIT(7)
+
+/* SRAM_ADDR_CTRL Register field definition */
+#define TPS65224_MASk_SRAM_SEL GENMASK(1, 0)
+
+/* RECOV_CNT_PFSM_INCR Register field definition */
+#define TPS65224_BIT_INCREMENT_RECOV_CNT BIT(0)
+
+/* MANUFACTURING_VER Register field definition */
+#define TPS65224_MASK_SILICON_REV GENMASK(7, 0)
+
+/* CUSTOMER_NVM_ID_REG Register field definition */
+#define TPS65224_MASK_CUSTOMER_NVM_ID GENMASK(7, 0)
+
/* SOFT_REBOOT_REG register field definition */
#define TPS6594_BIT_SOFT_REBOOT BIT(0)
@@ -755,14 +909,83 @@ enum pmic_id {
#define TPS6594_BIT_I2C2_CRC_EN BIT(2)
#define TPS6594_MASK_T_CRC GENMASK(7, 3)
+/* ADC_CTRL Register field definition */
+#define TPS65224_BIT_ADC_START BIT(0)
+#define TPS65224_BIT_ADC_CONT_CONV BIT(1)
+#define TPS65224_BIT_ADC_THERMAL_SEL BIT(2)
+#define TPS65224_BIT_ADC_RDIV_EN BIT(3)
+#define TPS65224_BIT_ADC_STATUS BIT(7)
+
+/* ADC_RESULT_REG_1 Register field definition */
+#define TPS65224_MASK_ADC_RESULT_11_4 GENMASK(7, 0)
+
+/* ADC_RESULT_REG_2 Register field definition */
+#define TPS65224_MASK_ADC_RESULT_3_0 GENMASK(7, 4)
+
+/* STARTUP_CTRL Register field definition */
+#define TPS65224_MASK_STARTUP_DEST GENMASK(6, 5)
+#define TPS65224_BIT_FIRST_STARTUP_DONE BIT(7)
+
+/* SCRATCH_PAD_REG_1 Register field definition */
+#define TPS6594_MASK_SCRATCH_PAD_1 GENMASK(7, 0)
+
+/* SCRATCH_PAD_REG_2 Register field definition */
+#define TPS6594_MASK_SCRATCH_PAD_2 GENMASK(7, 0)
+
+/* SCRATCH_PAD_REG_3 Register field definition */
+#define TPS6594_MASK_SCRATCH_PAD_3 GENMASK(7, 0)
+
+/* SCRATCH_PAD_REG_4 Register field definition */
+#define TPS6594_MASK_SCRATCH_PAD_4 GENMASK(7, 0)
+
+/* PFSM_DELAY_REG_1 Register field definition */
+#define TPS6594_MASK_PFSM_DELAY1 GENMASK(7, 0)
+
+/* PFSM_DELAY_REG_2 Register field definition */
+#define TPS6594_MASK_PFSM_DELAY2 GENMASK(7, 0)
+
+/* PFSM_DELAY_REG_3 Register field definition */
+#define TPS6594_MASK_PFSM_DELAY3 GENMASK(7, 0)
+
+/* PFSM_DELAY_REG_4 Register field definition */
+#define TPS6594_MASK_PFSM_DELAY4 GENMASK(7, 0)
+
+/* CRC_CALC_CONTROL Register field definition */
+#define TPS65224_BIT_RUN_CRC_BIST BIT(0)
+#define TPS65224_BIT_RUN_CRC_UPDATE BIT(1)
+
+/* ADC_GAIN_COMP_REG Register field definition */
+#define TPS65224_MASK_ADC_GAIN_COMP GENMASK(7, 0)
+
+/* REGMAP_USER_CRC_LOW Register field definition */
+#define TPS65224_MASK_REGMAP_USER_CRC16_LOW GENMASK(7, 0)
+
+/* REGMAP_USER_CRC_HIGH Register field definition */
+#define TPS65224_MASK_REGMAP_USER_CRC16_HIGH GENMASK(7, 0)
+
+/* WD_ANSWER_REG Register field definition */
+#define TPS6594_MASK_WD_ANSWER GENMASK(7, 0)
+
/* WD_QUESTION_ANSW_CNT register field definition */
#define TPS6594_MASK_WD_QUESTION GENMASK(3, 0)
#define TPS6594_MASK_WD_ANSW_CNT GENMASK(5, 4)
+#define TPS65224_BIT_INT_TOP_STATUS BIT(7)
+
+/* WD WIN1_CFG register field definition */
+#define TPS6594_MASK_WD_WIN1_CFG GENMASK(6, 0)
+
+/* WD WIN2_CFG register field definition */
+#define TPS6594_MASK_WD_WIN2_CFG GENMASK(6, 0)
+
+/* WD LongWin register field definition */
+#define TPS6594_MASK_WD_LONGWIN_CFG GENMASK(7, 0)
/* WD_MODE_REG register field definition */
#define TPS6594_BIT_WD_RETURN_LONGWIN BIT(0)
#define TPS6594_BIT_WD_MODE_SELECT BIT(1)
#define TPS6594_BIT_WD_PWRHOLD BIT(2)
+#define TPS65224_BIT_WD_ENDRV_SEL BIT(6)
+#define TPS65224_BIT_WD_CNT_SEL BIT(7)
/* WD_QA_CFG register field definition */
#define TPS6594_MASK_WD_QUESTION_SEED GENMASK(3, 0)
@@ -993,6 +1216,106 @@ enum tps6594_irqs {
#define TPS6594_IRQ_NAME_ALARM "alarm"
#define TPS6594_IRQ_NAME_POWERUP "powerup"
+/* IRQs */
+enum tps65224_irqs {
+ /* INT_BUCK register */
+ TPS65224_IRQ_BUCK1_UVOV,
+ TPS65224_IRQ_BUCK2_UVOV,
+ TPS65224_IRQ_BUCK3_UVOV,
+ TPS65224_IRQ_BUCK4_UVOV,
+ /* INT_LDO_VMON register */
+ TPS65224_IRQ_LDO1_UVOV,
+ TPS65224_IRQ_LDO2_UVOV,
+ TPS65224_IRQ_LDO3_UVOV,
+ TPS65224_IRQ_VCCA_UVOV,
+ TPS65224_IRQ_VMON1_UVOV,
+ TPS65224_IRQ_VMON2_UVOV,
+ /* INT_GPIO register */
+ TPS65224_IRQ_GPIO1,
+ TPS65224_IRQ_GPIO2,
+ TPS65224_IRQ_GPIO3,
+ TPS65224_IRQ_GPIO4,
+ TPS65224_IRQ_GPIO5,
+ TPS65224_IRQ_GPIO6,
+ /* INT_STARTUP register */
+ TPS65224_IRQ_VSENSE,
+ TPS65224_IRQ_ENABLE,
+ TPS65224_IRQ_PB_SHORT,
+ TPS65224_IRQ_FSD,
+ TPS65224_IRQ_SOFT_REBOOT,
+ /* INT_MISC register */
+ TPS65224_IRQ_BIST_PASS,
+ TPS65224_IRQ_EXT_CLK,
+ TPS65224_IRQ_REG_UNLOCK,
+ TPS65224_IRQ_TWARN,
+ TPS65224_IRQ_PB_LONG,
+ TPS65224_IRQ_PB_FALL,
+ TPS65224_IRQ_PB_RISE,
+ TPS65224_IRQ_ADC_CONV_READY,
+ /* INT_MODERATE_ERR register */
+ TPS65224_IRQ_TSD_ORD,
+ TPS65224_IRQ_BIST_FAIL,
+ TPS65224_IRQ_REG_CRC_ERR,
+ TPS65224_IRQ_RECOV_CNT,
+ /* INT_SEVERE_ERR register */
+ TPS65224_IRQ_TSD_IMM,
+ TPS65224_IRQ_VCCA_OVP,
+ TPS65224_IRQ_PFSM_ERR,
+ TPS65224_IRQ_BG_XMON,
+ /* INT_FSM_ERR register */
+ TPS65224_IRQ_IMM_SHUTDOWN,
+ TPS65224_IRQ_ORD_SHUTDOWN,
+ TPS65224_IRQ_MCU_PWR_ERR,
+ TPS65224_IRQ_SOC_PWR_ERR,
+ TPS65224_IRQ_COMM_ERR,
+ TPS65224_IRQ_I2C2_ERR,
+};
+
+#define TPS65224_IRQ_NAME_BUCK1_UVOV "buck1_uvov"
+#define TPS65224_IRQ_NAME_BUCK2_UVOV "buck2_uvov"
+#define TPS65224_IRQ_NAME_BUCK3_UVOV "buck3_uvov"
+#define TPS65224_IRQ_NAME_BUCK4_UVOV "buck4_uvov"
+#define TPS65224_IRQ_NAME_LDO1_UVOV "ldo1_uvov"
+#define TPS65224_IRQ_NAME_LDO2_UVOV "ldo2_uvov"
+#define TPS65224_IRQ_NAME_LDO3_UVOV "ldo3_uvov"
+#define TPS65224_IRQ_NAME_VCCA_UVOV "vcca_uvov"
+#define TPS65224_IRQ_NAME_VMON1_UVOV "vmon1_uvov"
+#define TPS65224_IRQ_NAME_VMON2_UVOV "vmon2_uvov"
+#define TPS65224_IRQ_NAME_GPIO1 "gpio1"
+#define TPS65224_IRQ_NAME_GPIO2 "gpio2"
+#define TPS65224_IRQ_NAME_GPIO3 "gpio3"
+#define TPS65224_IRQ_NAME_GPIO4 "gpio4"
+#define TPS65224_IRQ_NAME_GPIO5 "gpio5"
+#define TPS65224_IRQ_NAME_GPIO6 "gpio6"
+#define TPS65224_IRQ_NAME_VSENSE "vsense"
+#define TPS65224_IRQ_NAME_ENABLE "enable"
+#define TPS65224_IRQ_NAME_PB_SHORT "pb_short"
+#define TPS65224_IRQ_NAME_FSD "fsd"
+#define TPS65224_IRQ_NAME_SOFT_REBOOT "soft_reboot"
+#define TPS65224_IRQ_NAME_BIST_PASS "bist_pass"
+#define TPS65224_IRQ_NAME_EXT_CLK "ext_clk"
+#define TPS65224_IRQ_NAME_REG_UNLOCK "reg_unlock"
+#define TPS65224_IRQ_NAME_TWARN "twarn"
+#define TPS65224_IRQ_NAME_PB_LONG "pb_long"
+#define TPS65224_IRQ_NAME_PB_FALL "pb_fall"
+#define TPS65224_IRQ_NAME_PB_RISE "pb_rise"
+#define TPS65224_IRQ_NAME_ADC_CONV_READY "adc_conv_ready"
+#define TPS65224_IRQ_NAME_TSD_ORD "tsd_ord"
+#define TPS65224_IRQ_NAME_BIST_FAIL "bist_fail"
+#define TPS65224_IRQ_NAME_REG_CRC_ERR "reg_crc_err"
+#define TPS65224_IRQ_NAME_RECOV_CNT "recov_cnt"
+#define TPS65224_IRQ_NAME_TSD_IMM "tsd_imm"
+#define TPS65224_IRQ_NAME_VCCA_OVP "vcca_ovp"
+#define TPS65224_IRQ_NAME_PFSM_ERR "pfsm_err"
+#define TPS65224_IRQ_NAME_BG_XMON "bg_xmon"
+#define TPS65224_IRQ_NAME_IMM_SHUTDOWN "imm_shutdown"
+#define TPS65224_IRQ_NAME_ORD_SHUTDOWN "ord_shutdown"
+#define TPS65224_IRQ_NAME_MCU_PWR_ERR "mcu_pwr_err"
+#define TPS65224_IRQ_NAME_SOC_PWR_ERR "soc_pwr_err"
+#define TPS65224_IRQ_NAME_COMM_ERR "comm_err"
+#define TPS65224_IRQ_NAME_I2C2_ERR "i2c2_err"
+#define TPS65224_IRQ_NAME_POWERUP "powerup"
+
/**
* struct tps6594 - device private data structure
*
--
2.25.1
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^ permalink raw reply related
* [PATCH v8 02/10] mfd: tps6594: use volatile_table instead of volatile_reg
From: Bhargav Raviprakash @ 2024-04-30 13:16 UTC (permalink / raw)
To: linux-kernel
Cc: m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
jpanis, devicetree, arnd, gregkh, lgirdwood, broonie,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc, Bhargav Raviprakash
In-Reply-To: <0109018f2f24c15e-c50bfc29-5f1d-4368-a4b8-2c9f1d398abb-000000@ap-south-1.amazonses.com>
In regmap_config use volatile_table instead of volatile_reg. This change
makes it easier to add support for TPS65224 PMIC.
Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
Acked-by: Julien Panis <jpanis@baylibre.com>
---
drivers/mfd/tps6594-core.c | 16 ++++++++++------
drivers/mfd/tps6594-i2c.c | 2 +-
drivers/mfd/tps6594-spi.c | 2 +-
include/linux/mfd/tps6594.h | 4 +++-
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/mfd/tps6594-core.c b/drivers/mfd/tps6594-core.c
index 783ee5990..089ab8cc8 100644
--- a/drivers/mfd/tps6594-core.c
+++ b/drivers/mfd/tps6594-core.c
@@ -319,12 +319,16 @@ static struct regmap_irq_chip tps6594_irq_chip = {
.handle_post_irq = tps6594_handle_post_irq,
};
-bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg)
-{
- return (reg >= TPS6594_REG_INT_TOP && reg <= TPS6594_REG_STAT_READBACK_ERR) ||
- reg == TPS6594_REG_RTC_STATUS;
-}
-EXPORT_SYMBOL_GPL(tps6594_is_volatile_reg);
+static const struct regmap_range tps6594_volatile_ranges[] = {
+ regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR),
+ regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS),
+};
+
+const struct regmap_access_table tps6594_volatile_table = {
+ .yes_ranges = tps6594_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(tps6594_volatile_ranges),
+};
+EXPORT_SYMBOL_GPL(tps6594_volatile_table);
static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic)
{
diff --git a/drivers/mfd/tps6594-i2c.c b/drivers/mfd/tps6594-i2c.c
index 899c88c0f..c125b474b 100644
--- a/drivers/mfd/tps6594-i2c.c
+++ b/drivers/mfd/tps6594-i2c.c
@@ -187,7 +187,7 @@ static const struct regmap_config tps6594_i2c_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
- .volatile_reg = tps6594_is_volatile_reg,
+ .volatile_table = &tps6594_volatile_table,
.read = tps6594_i2c_read,
.write = tps6594_i2c_write,
};
diff --git a/drivers/mfd/tps6594-spi.c b/drivers/mfd/tps6594-spi.c
index 24b72847e..5afb1736f 100644
--- a/drivers/mfd/tps6594-spi.c
+++ b/drivers/mfd/tps6594-spi.c
@@ -70,7 +70,7 @@ static const struct regmap_config tps6594_spi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
- .volatile_reg = tps6594_is_volatile_reg,
+ .volatile_table = &tps6594_volatile_table,
.reg_read = tps6594_spi_reg_read,
.reg_write = tps6594_spi_reg_write,
.use_single_read = true,
diff --git a/include/linux/mfd/tps6594.h b/include/linux/mfd/tps6594.h
index e754c01ac..16543fd4d 100644
--- a/include/linux/mfd/tps6594.h
+++ b/include/linux/mfd/tps6594.h
@@ -1337,7 +1337,9 @@ struct tps6594 {
struct regmap_irq_chip_data *irq_data;
};
-bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg);
+extern const struct regmap_access_table tps6594_volatile_table;
+extern const struct regmap_access_table tps65224_volatile_table;
+
int tps6594_device_init(struct tps6594 *tps, bool enable_crc);
#endif /* __LINUX_MFD_TPS6594_H */
--
2.25.1
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^ permalink raw reply related
* [PATCH v8 03/10] dt-bindings: mfd: ti,tps6594: Add TI TPS65224 PMIC
From: Bhargav Raviprakash @ 2024-04-30 13:16 UTC (permalink / raw)
To: linux-kernel
Cc: m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
jpanis, devicetree, arnd, gregkh, lgirdwood, broonie,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc, Bhargav Raviprakash, Conor Dooley
In-Reply-To: <0109018f2f24c15e-c50bfc29-5f1d-4368-a4b8-2c9f1d398abb-000000@ap-south-1.amazonses.com>
TPS65224 is a Power Management IC with 4 Buck regulators and 3 LDO
regulators, it includes additional features like GPIOs, watchdog, ESMs
(Error Signal Monitor), and PFSM (Pre-configurable Finite State Machine)
managing the state of the device.
In addition TPS65224 has support for 12-bit ADC and does not have RTC
unlike TPS6594.
Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml
index 9d43376be..6341b6070 100644
--- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml
@@ -21,6 +21,7 @@ properties:
- ti,lp8764-q1
- ti,tps6593-q1
- ti,tps6594-q1
+ - ti,tps65224-q1
reg:
description: I2C slave address or SPI chip select number.
--
2.25.1
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^ permalink raw reply related
* Re: [PATCH v2] arm64: dts: ti: Fix csi2-dual-imx219 dtb names
From: Devarsh Thakkar @ 2024-04-30 13:17 UTC (permalink / raw)
To: Jai Luthra, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vaishnav Achath
Cc: linux-arm-kernel, devicetree, linux-kernel, Aradhya Bhatia
In-Reply-To: <20240429-dtb_name_fix-v2-1-414fb8b7262d@ti.com>
On 29/04/24 12:13, Jai Luthra wrote:
> Fix the output filenames of the combined device tree blobs generated by
> applying *-csi2-dual-imx219-* overlays on the base dtbs during compile
> test.
>
> Fixes: f767eb918096 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219")
> Signed-off-by: Jai Luthra <j-luthra@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Regards
Devarsh
> ---
> Changes in v2:
> - Rebase to latest ti-k3-dts-next branch
> - Link to v1: https://lore.kernel.org/r/20240425-dtb_name_fix-v1-1-f3d0d7709be8@ti.com
> ---
> arch/arm64/boot/dts/ti/Makefile | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 48fb19a523bd..9c536d4902f4 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -170,10 +170,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
> k3-am642-evm-icssg1-dualemac.dtb \
> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
> k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
> - k3-am68-sk-base-board-csi2-dual-imx219-dtbs \
> - k3-am69-sk-csi2-dual-imx219-dtbs \
> + k3-am68-sk-base-board-csi2-dual-imx219.dtb \
> + k3-am69-sk-csi2-dual-imx219.dtb \
> k3-j721e-evm-pcie0-ep.dtb \
> - k3-j721e-sk-csi2-dual-imx219-dtbs \
> + k3-j721e-sk-csi2-dual-imx219.dtb \
> k3-j721s2-evm-pcie1-ep.dtb \
> k3-j784s4-evm-quad-port-eth-exp1.dtb \
> k3-j784s4-evm-usxgmii-exp1-exp2.dtb
>
> ---
> base-commit: 3454b58dd9d99e317871e9abd57f589ae7580642
> change-id: 20240425-dtb_name_fix-350eab4dd8ab
>
> Best regards,
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^ permalink raw reply
* [soc:mediatek/drivers] BUILD SUCCESS 8a87e1d21ef84fe68913aeba9838222422eef4d7
From: kernel test robot @ 2024-04-30 13:20 UTC (permalink / raw)
To: AngeloGioacchino Del Regno; +Cc: linux-arm-kernel, arm
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git mediatek/drivers
branch HEAD: 8a87e1d21ef84fe68913aeba9838222422eef4d7 soc: mediatek: mtk-socinfo: Correct the marketing name for MT8188GV
elapsed time: 1399m
configs tested: 165
configs skipped: 3
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc
alpha allyesconfig gcc
alpha defconfig gcc
arc allmodconfig gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc haps_hs_defconfig gcc
arc randconfig-001-20240430 gcc
arc randconfig-002-20240430 gcc
arm allmodconfig gcc
arm allnoconfig clang
arm allyesconfig gcc
arm defconfig clang
arm neponset_defconfig gcc
arm64 allmodconfig clang
arm64 allnoconfig gcc
arm64 allyesconfig clang
arm64 defconfig gcc
arm64 randconfig-002-20240430 gcc
arm64 randconfig-004-20240430 gcc
csky allmodconfig gcc
csky allnoconfig gcc
csky allyesconfig gcc
csky defconfig gcc
csky randconfig-001-20240430 gcc
csky randconfig-002-20240430 gcc
hexagon allmodconfig clang
hexagon allnoconfig clang
hexagon allyesconfig clang
hexagon defconfig clang
i386 allmodconfig gcc
i386 allnoconfig gcc
i386 allyesconfig gcc
i386 buildonly-randconfig-001-20240430 gcc
i386 buildonly-randconfig-003-20240430 gcc
i386 buildonly-randconfig-006-20240430 gcc
i386 defconfig clang
i386 randconfig-002-20240430 gcc
i386 randconfig-003-20240430 gcc
i386 randconfig-004-20240430 gcc
i386 randconfig-005-20240430 gcc
i386 randconfig-006-20240430 gcc
i386 randconfig-011-20240430 gcc
i386 randconfig-014-20240430 gcc
i386 randconfig-015-20240430 gcc
i386 randconfig-016-20240430 gcc
loongarch allmodconfig gcc
loongarch allnoconfig gcc
loongarch allyesconfig gcc
loongarch defconfig gcc
loongarch randconfig-001-20240430 gcc
loongarch randconfig-002-20240430 gcc
m68k allmodconfig gcc
m68k allnoconfig gcc
m68k allyesconfig gcc
m68k defconfig gcc
m68k m5208evb_defconfig gcc
m68k sun3_defconfig gcc
microblaze allmodconfig gcc
microblaze allnoconfig gcc
microblaze allyesconfig gcc
microblaze defconfig gcc
mips allmodconfig gcc
mips allnoconfig gcc
mips allyesconfig gcc
nios2 allmodconfig gcc
nios2 allnoconfig gcc
nios2 allyesconfig gcc
nios2 defconfig gcc
nios2 randconfig-001-20240430 gcc
nios2 randconfig-002-20240430 gcc
openrisc allmodconfig gcc
openrisc allnoconfig gcc
openrisc allyesconfig gcc
openrisc defconfig gcc
parisc allmodconfig gcc
parisc allnoconfig gcc
parisc allyesconfig gcc
parisc defconfig gcc
parisc randconfig-001-20240430 gcc
parisc randconfig-002-20240430 gcc
parisc64 defconfig gcc
powerpc allmodconfig gcc
powerpc allnoconfig gcc
powerpc allyesconfig clang
powerpc kmeter1_defconfig gcc
powerpc ppa8548_defconfig gcc
powerpc ppc64e_defconfig gcc
powerpc randconfig-001-20240430 gcc
powerpc randconfig-002-20240430 gcc
powerpc sam440ep_defconfig gcc
powerpc tqm5200_defconfig gcc
riscv allmodconfig clang
riscv allnoconfig gcc
riscv allyesconfig clang
riscv defconfig clang
riscv randconfig-001-20240430 gcc
s390 allmodconfig clang
s390 allnoconfig clang
s390 allyesconfig gcc
s390 defconfig clang
s390 randconfig-001-20240430 gcc
s390 randconfig-002-20240430 gcc
sh allmodconfig gcc
sh allnoconfig gcc
sh allyesconfig gcc
sh defconfig gcc
sh hp6xx_defconfig gcc
sh magicpanelr2_defconfig gcc
sh randconfig-001-20240430 gcc
sh randconfig-002-20240430 gcc
sh se7721_defconfig gcc
sh se7722_defconfig gcc
sh se7780_defconfig gcc
sh sh03_defconfig gcc
sh sh7710voipgw_defconfig gcc
sparc allmodconfig gcc
sparc allnoconfig gcc
sparc allyesconfig gcc
sparc defconfig gcc
sparc64 allmodconfig gcc
sparc64 allyesconfig gcc
sparc64 defconfig gcc
sparc64 randconfig-001-20240430 gcc
sparc64 randconfig-002-20240430 gcc
um allmodconfig clang
um allnoconfig clang
um allyesconfig gcc
um defconfig clang
um i386_defconfig gcc
um x86_64_defconfig clang
x86_64 allnoconfig clang
x86_64 allyesconfig clang
x86_64 buildonly-randconfig-001-20240430 gcc
x86_64 buildonly-randconfig-002-20240430 clang
x86_64 buildonly-randconfig-003-20240430 clang
x86_64 buildonly-randconfig-004-20240430 clang
x86_64 buildonly-randconfig-005-20240430 clang
x86_64 buildonly-randconfig-006-20240430 clang
x86_64 defconfig gcc
x86_64 randconfig-001-20240430 clang
x86_64 randconfig-002-20240430 clang
x86_64 randconfig-003-20240430 gcc
x86_64 randconfig-004-20240430 gcc
x86_64 randconfig-005-20240430 gcc
x86_64 randconfig-006-20240430 clang
x86_64 randconfig-011-20240430 clang
x86_64 randconfig-012-20240430 clang
x86_64 randconfig-013-20240430 gcc
x86_64 randconfig-014-20240430 clang
x86_64 randconfig-015-20240430 clang
x86_64 randconfig-016-20240430 clang
x86_64 randconfig-071-20240430 clang
x86_64 randconfig-072-20240430 clang
x86_64 randconfig-073-20240430 clang
x86_64 randconfig-074-20240430 clang
x86_64 randconfig-075-20240430 gcc
x86_64 randconfig-076-20240430 clang
x86_64 rhel-8.3-rust clang
x86_64 rhel-8.3 gcc
xtensa allnoconfig gcc
xtensa allyesconfig gcc
xtensa randconfig-001-20240430 gcc
xtensa randconfig-002-20240430 gcc
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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^ permalink raw reply
* Re: [PATCH net] net: dsa: mt7530: fix impossible MDIO address and issue warning
From: Andrew Lunn @ 2024-04-30 13:21 UTC (permalink / raw)
To: Daniel Golle
Cc: Arınç ÜNAL, Felix Fietkau, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, DENG Qingfang, Sean Wang,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Landen Chao, devicetree, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <e615351aefba25e990215845e4812e6cb8153b28.1714433716.git.daniel@makrotopia.org>
On Tue, Apr 30, 2024 at 12:45:46AM +0100, Daniel Golle wrote:
> The MDIO address of the MT7530 and MT7531 switch ICs can be configured
> using bootstrap pins. However, there are only 4 possible options for the
> switch itself: 7, 15, 23 and 31 (ie. only 3 and 4 can be configured, bit
> 0~2 are always 111). Practically all boards known as of today use the
> default setting which is to have the switch respond to address 31, while
> the built-in switch PHYs respond to address 0~4 in this case.
>
> However, even in MediaTek's SDK the address of the switch is wrongly
> stated in the device trees as 0 (while in reality it is 31), so warn the
> user about such broken device tree and make a good guess what was
> actually intended.
>
> This is imporant to not break compatibility with older Device Trees as
> with commit 868ff5f4944a ("net: dsa: mt7530-mdio: read PHY address of
> switch from device tree") the address in device tree will be taken into
> account. Doing so instead of assuming the switch is always at
> address 31 which was previously hard-coded will obviously break things
> for many existing downstream device trees as they contain the wrong
> address (0) which previously didn't matter.
>
> Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> drivers/net/dsa/mt7530-mdio.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
> index fa3ee85a99c1..119630fd9060 100644
> --- a/drivers/net/dsa/mt7530-mdio.c
> +++ b/drivers/net/dsa/mt7530-mdio.c
> @@ -193,6 +193,19 @@ mt7530_probe(struct mdio_device *mdiodev)
> return PTR_ERR(priv->io_pwr);
> }
>
> + /* Only MDIO bus address 7, 15, 23 and 31 are valid options */
> + if (~(priv->mdiodev->addr & 0x7) & 0x7) {
> + /* If the address in DT must be wrong, make a good guess about
> + * the most likely intention, and issue a warning.
> + */
> + int correct_addr = ((((priv->mdiodev->addr - 7) & ~0x7) % 0x20) + 7) & 0x1f;
> +
> + dev_warn(&mdiodev->dev,
> + "impossible switch MDIO address in device tree: %d, assuming %d\n",
> + priv->mdiodev->addr, correct_addr);
You could include FW_WARN in this, to indicate this is a firmware
issue. It is not used too much with DT, since it was originally
intended for ACPI issues, but a few ARM systems use it with DT.
Andrew
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^ permalink raw reply
* Re: [PATCH v2 1/3] arm64/mm: Refactor PMD_PRESENT_INVALID and PTE_PROT_NONE bits
From: Catalin Marinas @ 2024-04-30 13:28 UTC (permalink / raw)
To: Ryan Roberts
Cc: Will Deacon, Joey Gouly, Ard Biesheuvel, Mark Rutland,
Anshuman Khandual, David Hildenbrand, Peter Xu, Mike Rapoport,
Shivansh Vij, linux-arm-kernel, linux-kernel
In-Reply-To: <8cf74e5f-e6a5-465e-83b4-205233c78005@arm.com>
On Tue, Apr 30, 2024 at 12:35:49PM +0100, Ryan Roberts wrote:
> There is still one problem I need to resolve; During this work I discovered that
> core-mm can call pmd_mkinvalid() for swap pmds. On arm64 this will turn the swap
> pmd into a present pmd, and BadThings can happen in GUP-fast (and any other
> lockless SW table walkers). My original fix modified core-mm to only call
> pmd_mkinvalid() for present pmds. But discussion over there has shown that arm64
> is the only arch that cannot handle this. So I've been convinced that it's
> probably more robust to make arm64 handle it gracefully and add tests to
> debug_vm_pgtable.c to check for this. Patch incoming shortly, but it will cause
> a conflict with this series. So I'll send a v2 of this once that fix is accepted.
Sounds fine. I can queue the arm64 pmd_mkinvalid() fix for 6.9 and you
can base this series on top. But I have a preference for this patchset
to sit in -next for a bit anyway, so it might be 6.11 material.
--
Catalin
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^ permalink raw reply
* Re: [PATCH v2 1/3] arm64/mm: Refactor PMD_PRESENT_INVALID and PTE_PROT_NONE bits
From: Will Deacon @ 2024-04-30 13:30 UTC (permalink / raw)
To: Ryan Roberts
Cc: Catalin Marinas, Joey Gouly, Ard Biesheuvel, Mark Rutland,
Anshuman Khandual, David Hildenbrand, Peter Xu, Mike Rapoport,
Shivansh Vij, linux-arm-kernel, linux-kernel
In-Reply-To: <20240429140208.238056-2-ryan.roberts@arm.com>
Hey Ryan,
Just a couple of comments on this:
On Mon, Apr 29, 2024 at 03:02:05PM +0100, Ryan Roberts wrote:
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index dd9ee67d1d87..de62e6881154 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -18,14 +18,7 @@
> #define PTE_DIRTY (_AT(pteval_t, 1) << 55)
> #define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
> #define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
> -#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
> -
> -/*
> - * This bit indicates that the entry is present i.e. pmd_page()
> - * still points to a valid huge page in memory even if the pmd
> - * has been invalidated.
> - */
> -#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
> +#define PTE_INVALID (_AT(pteval_t, 1) << 59) /* only when !PTE_VALID */
So this now overlaps with AttrIndx[3] if FEAT_AIE is implemented. Although
this shouldn't matter on the face of things because it's only used for
invalid entries, we originally moved the PROT_NONE bit from 2 to 57 back
in 3676f9ef5481 ("arm64: Move PTE_PROT_NONE higher up") because it was
possible to change the memory type for PROT_NONE mappings via some
drivers.
Moving the field to the NS bit (as you do later in the series) resolves
this, but the architecture currently says that the NS bit is RES0. How
can we guarantee that it won't be repurposed by hardware in future?
> #define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
> #define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
> @@ -103,7 +96,7 @@ static inline bool __pure lpa2_is_enabled(void)
> __val; \
> })
>
> -#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> +#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_INVALID | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
> #define PAGE_SHARED __pgprot(_PAGE_SHARED)
> #define PAGE_SHARED_EXEC __pgprot(_PAGE_SHARED_EXEC)
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index afdd56d26ad7..8dd4637d6b56 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -105,7 +105,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
> /*
> * The following only work if pte_present(). Undefined behaviour otherwise.
> */
> -#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
> +#define pte_present(pte) (pte_valid(pte) || pte_invalid(pte))
> #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
> #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
> #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
> @@ -132,6 +132,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
> #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
>
> #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
> +#define pte_invalid(pte) ((pte_val(pte) & (PTE_VALID | PTE_INVALID)) == PTE_INVALID)
> /*
> * Execute-only user mappings do not have the PTE_USER bit set. All valid
> * kernel mappings have the PTE_UXN bit set.
> @@ -261,6 +262,13 @@ static inline pte_t pte_mkpresent(pte_t pte)
> return set_pte_bit(pte, __pgprot(PTE_VALID));
> }
>
> +static inline pte_t pte_mkinvalid(pte_t pte)
> +{
> + pte = set_pte_bit(pte, __pgprot(PTE_INVALID));
> + pte = clear_pte_bit(pte, __pgprot(PTE_VALID));
> + return pte;
> +}
> +
> static inline pmd_t pmd_mkcont(pmd_t pmd)
> {
> return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
> @@ -469,7 +477,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
> */
> static inline int pte_protnone(pte_t pte)
> {
> - return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
> + return pte_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte);
> }
Why do we need to check pte_user_*() here? Isn't PROT_NONE the only case
in which a pte will have PTE_INVALID set?
Will
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* [PATCH v2] arm64/mm: pmd_mkinvalid() must handle swap pmds
From: Ryan Roberts @ 2024-04-30 13:31 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Anshuman Khandual,
Andrew Morton, Zi Yan, Aneesh Kumar K.V
Cc: Ryan Roberts, linux-arm-kernel, linux-mm, linux-kernel, stable
__split_huge_pmd_locked() can be called for a present THP, devmap or
(non-present) migration entry. It calls pmdp_invalidate()
unconditionally on the pmdp and only determines if it is present or not
based on the returned old pmd.
But arm64's pmd_mkinvalid(), called by pmdp_invalidate(),
unconditionally sets the PMD_PRESENT_INVALID flag, which causes future
pmd_present() calls to return true - even for a swap pmd. Therefore any
lockless pgtable walker could see the migration entry pmd in this state
and start interpretting the fields (e.g. pmd_pfn()) as if it were
present, leading to BadThings (TM). GUP-fast appears to be one such
lockless pgtable walker.
While the obvious fix is for core-mm to avoid such calls for non-present
pmds (pmdp_invalidate() will also issue TLBI which is not necessary for
this case either), all other arches that implement pmd_mkinvalid() do it
in such a way that it is robust to being called with a non-present pmd.
So it is simpler and safer to make arm64 robust too. This approach means
we can even add tests to debug_vm_pgtable.c to validate the required
behaviour.
This is a theoretical bug found during code review. I don't have any
test case to trigger it in practice.
Cc: stable@vger.kernel.org
Fixes: 53fa117bb33c ("arm64/mm: Enable THP migration")
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
Hi all,
v1 of this fix [1] took the approach of fixing core-mm to never call
pmdp_invalidate() on a non-present pmd. But Zi Yan highlighted that only arm64
suffers this problem; all other arches are robust. So his suggestion was to
instead make arm64 robust in the same way and add tests to validate it. Despite
my stated reservations in the context of the v1 discussion, having thought on it
for a bit, I now agree with Zi Yan. Hence this post.
Andrew has v1 in mm-unstable at the moment, so probably the best thing to do is
remove it from there and have this go in through the arm64 tree? Assuming there
is agreement that this approach is right one.
This applies on top of v6.9-rc5. Passes all the mm selftests on arm64.
[1] https://lore.kernel.org/linux-mm/20240425170704.3379492-1-ryan.roberts@arm.com/
Thanks,
Ryan
arch/arm64/include/asm/pgtable.h | 12 +++++--
mm/debug_vm_pgtable.c | 61 ++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index afdd56d26ad7..7d580271a46d 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -511,8 +511,16 @@ static inline int pmd_trans_huge(pmd_t pmd)
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
{
- pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
- pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
+ /*
+ * If not valid then either we are already present-invalid or we are
+ * not-present (i.e. none or swap entry). We must not convert
+ * not-present to present-invalid. Unbelievably, the core-mm may call
+ * pmd_mkinvalid() for a swap entry and all other arches can handle it.
+ */
+ if (pmd_valid(pmd)) {
+ pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
+ pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
+ }
return pmd;
}
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 65c19025da3d..7e9c387d06b0 100644
--- a/mm/debug_vm_pgtable.c
+++ b/mm/debug_vm_pgtable.c
@@ -956,6 +956,65 @@ static void __init hugetlb_basic_tests(struct pgtable_debug_args *args) { }
#endif /* CONFIG_HUGETLB_PAGE */
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#if !defined(__HAVE_ARCH_PMDP_INVALIDATE) && defined(CONFIG_ARCH_ENABLE_THP_MIGRATION)
+static void __init swp_pmd_mkinvalid_tests(struct pgtable_debug_args *args)
+{
+ unsigned long max_swap_offset;
+ swp_entry_t swp_set, swp_clear, swp_convert;
+ pmd_t pmd_set, pmd_clear;
+
+ /*
+ * See generic_max_swapfile_size(): probe the maximum offset, then
+ * create swap entry will all possible bits set and a swap entry will
+ * all bits clear.
+ */
+ max_swap_offset = swp_offset(pmd_to_swp_entry(swp_entry_to_pmd(swp_entry(0, ~0UL))));
+ swp_set = swp_entry((1 << MAX_SWAPFILES_SHIFT) - 1, max_swap_offset);
+ swp_clear = swp_entry(0, 0);
+
+ /* Convert to pmd. */
+ pmd_set = swp_entry_to_pmd(swp_set);
+ pmd_clear = swp_entry_to_pmd(swp_clear);
+
+ /*
+ * Sanity check that the pmds are not-present, not-huge and swap entry
+ * is recoverable without corruption.
+ */
+ WARN_ON(pmd_present(pmd_set));
+ WARN_ON(pmd_trans_huge(pmd_set));
+ swp_convert = pmd_to_swp_entry(pmd_set);
+ WARN_ON(swp_type(swp_set) != swp_type(swp_convert));
+ WARN_ON(swp_offset(swp_set) != swp_offset(swp_convert));
+ WARN_ON(pmd_present(pmd_clear));
+ WARN_ON(pmd_trans_huge(pmd_clear));
+ swp_convert = pmd_to_swp_entry(pmd_clear);
+ WARN_ON(swp_type(swp_clear) != swp_type(swp_convert));
+ WARN_ON(swp_offset(swp_clear) != swp_offset(swp_convert));
+
+ /* Now invalidate the pmd. */
+ pmd_set = pmd_mkinvalid(pmd_set);
+ pmd_clear = pmd_mkinvalid(pmd_clear);
+
+ /*
+ * Since its a swap pmd, invalidation should effectively be a noop and
+ * the checks we already did should give the same answer. Check the
+ * invalidation didn't corrupt any fields.
+ */
+ WARN_ON(pmd_present(pmd_set));
+ WARN_ON(pmd_trans_huge(pmd_set));
+ swp_convert = pmd_to_swp_entry(pmd_set);
+ WARN_ON(swp_type(swp_set) != swp_type(swp_convert));
+ WARN_ON(swp_offset(swp_set) != swp_offset(swp_convert));
+ WARN_ON(pmd_present(pmd_clear));
+ WARN_ON(pmd_trans_huge(pmd_clear));
+ swp_convert = pmd_to_swp_entry(pmd_clear);
+ WARN_ON(swp_type(swp_clear) != swp_type(swp_convert));
+ WARN_ON(swp_offset(swp_clear) != swp_offset(swp_convert));
+}
+#else
+static void __init swp_pmd_mkinvalid_tests(struct pgtable_debug_args *args) { }
+#endif /* !__HAVE_ARCH_PMDP_INVALIDATE && CONFIG_ARCH_ENABLE_THP_MIGRATION */
+
static void __init pmd_thp_tests(struct pgtable_debug_args *args)
{
pmd_t pmd;
@@ -982,6 +1041,8 @@ static void __init pmd_thp_tests(struct pgtable_debug_args *args)
WARN_ON(!pmd_trans_huge(pmd_mkinvalid(pmd_mkhuge(pmd))));
WARN_ON(!pmd_present(pmd_mkinvalid(pmd_mkhuge(pmd))));
#endif /* __HAVE_ARCH_PMDP_INVALIDATE */
+
+ swp_pmd_mkinvalid_tests(args);
}
#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
--
2.25.1
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