* [PATCH 1/3] clk: imx8mm: remove SYS PLL 1/2 clock gates
2022-02-25 8:17 [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Peng Fan (OSS)
@ 2022-02-25 8:17 ` Peng Fan (OSS)
2022-02-25 8:17 ` [PATCH 2/3] clk: imx8mn: " Peng Fan (OSS)
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Peng Fan (OSS) @ 2022-02-25 8:17 UTC (permalink / raw)
To: sboyd, robh+dt, shawnguo, s.hauer, abel.vesa
Cc: kernel, festevam, linux-imx, linux-clk, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 49 ++++++++++++------------------------
1 file changed, 16 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index e92621fa8b9c..e8cbe181ec06 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -366,45 +366,28 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
/* SYS PLL1 fixed output */
- hws[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
- hws[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
- hws[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
- hws[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
- hws[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
- hws[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
- hws[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
- hws[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
- hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
- hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
- hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
- hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
- hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
- hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
- hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
- hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
+ hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
/* SYS PLL2 fixed output */
- hws[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
- hws[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
- hws[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
- hws[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
- hws[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
- hws[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
- hws[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
- hws[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
-
- hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
- hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
- hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
- hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
- hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
- hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
- hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
- hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
+ hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
--
2.25.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/3] clk: imx8mn: remove SYS PLL 1/2 clock gates
2022-02-25 8:17 [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Peng Fan (OSS)
2022-02-25 8:17 ` [PATCH 1/3] clk: imx8mm: remove SYS PLL 1/2 clock gates Peng Fan (OSS)
@ 2022-02-25 8:17 ` Peng Fan (OSS)
2022-02-25 8:17 ` [PATCH 3/3] clk: imx8mp: " Peng Fan (OSS)
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Peng Fan (OSS) @ 2022-02-25 8:17 UTC (permalink / raw)
To: sboyd, robh+dt, shawnguo, s.hauer, abel.vesa
Cc: kernel, festevam, linux-imx, linux-clk, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mn.c | 50 ++++++++++++------------------------
1 file changed, 16 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 021355a24708..92fcbab4f5be 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -364,45 +364,27 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
/* SYS PLL1 fixed output */
- hws[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
- hws[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
- hws[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
- hws[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
- hws[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
- hws[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
- hws[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
- hws[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
-
- hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
- hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
- hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
- hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
- hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
- hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
- hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
- hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
+ hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
/* SYS PLL2 fixed output */
- hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
- hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
- hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
- hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
- hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
- hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
- hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
- hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
-
- hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
- hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
- hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
- hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
- hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
- hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
- hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
- hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
+ hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
--
2.25.1
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
2022-02-25 8:17 [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Peng Fan (OSS)
2022-02-25 8:17 ` [PATCH 1/3] clk: imx8mm: remove SYS PLL 1/2 clock gates Peng Fan (OSS)
2022-02-25 8:17 ` [PATCH 2/3] clk: imx8mn: " Peng Fan (OSS)
@ 2022-02-25 8:17 ` Peng Fan (OSS)
2022-02-25 14:35 ` Abel Vesa
2022-02-28 12:23 ` [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Abel Vesa
2022-03-04 8:50 ` Abel Vesa
4 siblings, 1 reply; 9+ messages in thread
From: Peng Fan (OSS) @ 2022-02-25 8:17 UTC (permalink / raw)
To: sboyd, robh+dt, shawnguo, s.hauer, abel.vesa
Cc: kernel, festevam, linux-imx, linux-clk, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mp.c | 48 ++++++++++++------------------------
1 file changed, 16 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index f23b92906d3b..18f5b7c3ca9d 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
- hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
- hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
- hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
- hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
- hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
- hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
- hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
- hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
- hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
- hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
- hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
- hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
- hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
- hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
- hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
- hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
+ hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
- hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
- hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
- hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
- hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
- hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
- hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
- hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
- hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
- hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
- hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
- hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
- hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
- hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
- hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
- hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
- hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
+ hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
--
2.25.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
2022-02-25 8:17 ` [PATCH 3/3] clk: imx8mp: " Peng Fan (OSS)
@ 2022-02-25 14:35 ` Abel Vesa
2022-02-28 0:39 ` Peng Fan
0 siblings, 1 reply; 9+ messages in thread
From: Abel Vesa @ 2022-02-25 14:35 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: sboyd, robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
linux-clk, devicetree, linux-arm-kernel, linux-kernel, Peng Fan
On 22-02-25 16:17:33, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Remove the PLL 1/2 gates as it make AMP clock management harder without
> obvious benifit.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mp.c | 48 ++++++++++++------------------------
> 1 file changed, 16 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index f23b92906d3b..18f5b7c3ca9d 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
> hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
>
> - hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
Hmm, isn't there a chance that u-boot might gate these? Then, in kernel
you won't have a way to ungate them, leaving the consumers hanging.
> - hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
> - hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
> - hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
> - hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
> - hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
> - hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
> - hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
> hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
>
> - hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
> - hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
> - hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
> - hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
> - hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
> - hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
> - hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
> - hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
> + hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> + hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
> + hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
> + hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
> + hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
> + hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
> + hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
> + hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
> hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
>
> - hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
> - hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
> - hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
> - hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
> - hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
> - hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
> - hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
> - hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
> hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
>
> - hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
> - hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
> - hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
> - hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
> - hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
> - hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
> - hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
> - hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> + hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
> + hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
> + hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> + hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
> + hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
> + hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
> + hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
> + hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
> hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>
> hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 9+ messages in thread* RE: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
2022-02-25 14:35 ` Abel Vesa
@ 2022-02-28 0:39 ` Peng Fan
2022-02-28 12:23 ` Abel Vesa
0 siblings, 1 reply; 9+ messages in thread
From: Peng Fan @ 2022-02-28 0:39 UTC (permalink / raw)
To: Abel Vesa, Peng Fan (OSS)
Cc: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
dl-linux-imx, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Hi Abel,
> Subject: Re: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
>
> On 22-02-25 16:17:33, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Remove the PLL 1/2 gates as it make AMP clock management harder
> > without obvious benifit.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > drivers/clk/imx/clk-imx8mp.c | 48
> > ++++++++++++------------------------
> > 1 file changed, 16 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index f23b92906d3b..18f5b7c3ca9d
> 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
> > hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out",
> "arm_pll_bypass", anatop_base + 0x84, 11);
> > hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out",
> > "sys_pll3_bypass", anatop_base + 0x114, 11);
> >
> > - hws[IMX8MP_SYS_PLL1_40M_CG] =
> imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> 27);
>
> Hmm, isn't there a chance that u-boot might gate these? Then, in kernel you
> won't have a way to ungate them, leaving the consumers hanging.
Both NXP and Upstream U-Boot not touch these bits. With the CG managed
by Linux, it is hard to support AMP. This is same to Lucas's patch to
clk-imx8mq.c to drop the gate.
The other method to support AMP well, is to add the CGs clk in device tree node
for Mcore. But we still need a method to support M core booted in U-Boot, and
linux may gate off the clock.
Thanks,
Peng.
>
> > - hws[IMX8MP_SYS_PLL1_80M_CG] =
> imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> 25);
> > - hws[IMX8MP_SYS_PLL1_100M_CG] =
> imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 23);
> > - hws[IMX8MP_SYS_PLL1_133M_CG] =
> imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 21);
> > - hws[IMX8MP_SYS_PLL1_160M_CG] =
> imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 19);
> > - hws[IMX8MP_SYS_PLL1_200M_CG] =
> imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 17);
> > - hws[IMX8MP_SYS_PLL1_266M_CG] =
> imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 15);
> > - hws[IMX8MP_SYS_PLL1_400M_CG] =
> imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 13);
> > hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out",
> > "sys_pll1_bypass", anatop_base + 0x94, 11);
> >
> > - hws[IMX8MP_SYS_PLL1_40M] =
> imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
> > - hws[IMX8MP_SYS_PLL1_80M] =
> imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
> > - hws[IMX8MP_SYS_PLL1_100M] =
> imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
> > - hws[IMX8MP_SYS_PLL1_133M] =
> imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
> > - hws[IMX8MP_SYS_PLL1_160M] =
> imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
> > - hws[IMX8MP_SYS_PLL1_200M] =
> imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
> > - hws[IMX8MP_SYS_PLL1_266M] =
> imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
> > - hws[IMX8MP_SYS_PLL1_400M] =
> imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
> > + hws[IMX8MP_SYS_PLL1_40M] =
> imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> > + hws[IMX8MP_SYS_PLL1_80M] =
> imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
> > + hws[IMX8MP_SYS_PLL1_100M] =
> imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
> > + hws[IMX8MP_SYS_PLL1_133M] =
> imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
> > + hws[IMX8MP_SYS_PLL1_160M] =
> imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
> > + hws[IMX8MP_SYS_PLL1_200M] =
> imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
> > + hws[IMX8MP_SYS_PLL1_266M] =
> imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
> > + hws[IMX8MP_SYS_PLL1_400M] =
> imx_clk_hw_fixed_factor("sys_pll1_400m",
> > +"sys_pll1_out", 1, 2);
> > hws[IMX8MP_SYS_PLL1_800M] =
> imx_clk_hw_fixed_factor("sys_pll1_800m",
> > "sys_pll1_out", 1, 1);
> >
> > - hws[IMX8MP_SYS_PLL2_50M_CG] =
> imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 27);
> > - hws[IMX8MP_SYS_PLL2_100M_CG] =
> imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 25);
> > - hws[IMX8MP_SYS_PLL2_125M_CG] =
> imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 23);
> > - hws[IMX8MP_SYS_PLL2_166M_CG] =
> imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 21);
> > - hws[IMX8MP_SYS_PLL2_200M_CG] =
> imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 19);
> > - hws[IMX8MP_SYS_PLL2_250M_CG] =
> imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 17);
> > - hws[IMX8MP_SYS_PLL2_333M_CG] =
> imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 15);
> > - hws[IMX8MP_SYS_PLL2_500M_CG] =
> imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 13);
> > hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out",
> > "sys_pll2_bypass", anatop_base + 0x104, 11);
> >
> > - hws[IMX8MP_SYS_PLL2_50M] =
> imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
> > - hws[IMX8MP_SYS_PLL2_100M] =
> imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
> > - hws[IMX8MP_SYS_PLL2_125M] =
> imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
> > - hws[IMX8MP_SYS_PLL2_166M] =
> imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
> > - hws[IMX8MP_SYS_PLL2_200M] =
> imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
> > - hws[IMX8MP_SYS_PLL2_250M] =
> imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
> > - hws[IMX8MP_SYS_PLL2_333M] =
> imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
> > - hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> > + hws[IMX8MP_SYS_PLL2_50M] =
> imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
> > + hws[IMX8MP_SYS_PLL2_100M] =
> imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
> > + hws[IMX8MP_SYS_PLL2_125M] =
> imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> > + hws[IMX8MP_SYS_PLL2_166M] =
> imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
> > + hws[IMX8MP_SYS_PLL2_200M] =
> imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
> > + hws[IMX8MP_SYS_PLL2_250M] =
> imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
> > + hws[IMX8MP_SYS_PLL2_333M] =
> imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
> > + hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m",
> > +"sys_pll2_out", 1, 2);
> > hws[IMX8MP_SYS_PLL2_1000M] =
> > imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> >
> > hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div",
> > imx8mp_a53_sels, ccm_base + 0x8000);
> > --
> > 2.25.1
> >
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
2022-02-28 0:39 ` Peng Fan
@ 2022-02-28 12:23 ` Abel Vesa
0 siblings, 0 replies; 9+ messages in thread
From: Abel Vesa @ 2022-02-28 12:23 UTC (permalink / raw)
To: Peng Fan
Cc: Peng Fan (OSS), sboyd@kernel.org, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
On 22-02-28 02:39:45, Peng Fan wrote:
> Hi Abel,
>
> > Subject: Re: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
> >
> > On 22-02-25 16:17:33, Peng Fan (OSS) wrote:
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > Remove the PLL 1/2 gates as it make AMP clock management harder
> > > without obvious benifit.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > drivers/clk/imx/clk-imx8mp.c | 48
> > > ++++++++++++------------------------
> > > 1 file changed, 16 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > > b/drivers/clk/imx/clk-imx8mp.c index f23b92906d3b..18f5b7c3ca9d
> > 100644
> > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > @@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct
> > platform_device *pdev)
> > > hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out",
> > "arm_pll_bypass", anatop_base + 0x84, 11);
> > > hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out",
> > > "sys_pll3_bypass", anatop_base + 0x114, 11);
> > >
> > > - hws[IMX8MP_SYS_PLL1_40M_CG] =
> > imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> > 27);
> >
> > Hmm, isn't there a chance that u-boot might gate these? Then, in kernel you
> > won't have a way to ungate them, leaving the consumers hanging.
>
> Both NXP and Upstream U-Boot not touch these bits. With the CG managed
> by Linux, it is hard to support AMP. This is same to Lucas's patch to
> clk-imx8mq.c to drop the gate.
>
> The other method to support AMP well, is to add the CGs clk in device tree node
> for Mcore. But we still need a method to support M core booted in U-Boot, and
> linux may gate off the clock.
>
OK, thanks for clarifying that. Makes sense now.
> Thanks,
> Peng.
>
> >
> > > - hws[IMX8MP_SYS_PLL1_80M_CG] =
> > imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> > 25);
> > > - hws[IMX8MP_SYS_PLL1_100M_CG] =
> > imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 23);
> > > - hws[IMX8MP_SYS_PLL1_133M_CG] =
> > imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 21);
> > > - hws[IMX8MP_SYS_PLL1_160M_CG] =
> > imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 19);
> > > - hws[IMX8MP_SYS_PLL1_200M_CG] =
> > imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 17);
> > > - hws[IMX8MP_SYS_PLL1_266M_CG] =
> > imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 15);
> > > - hws[IMX8MP_SYS_PLL1_400M_CG] =
> > imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base +
> > 0x94, 13);
> > > hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out",
> > > "sys_pll1_bypass", anatop_base + 0x94, 11);
> > >
> > > - hws[IMX8MP_SYS_PLL1_40M] =
> > imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
> > > - hws[IMX8MP_SYS_PLL1_80M] =
> > imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
> > > - hws[IMX8MP_SYS_PLL1_100M] =
> > imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
> > > - hws[IMX8MP_SYS_PLL1_133M] =
> > imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
> > > - hws[IMX8MP_SYS_PLL1_160M] =
> > imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
> > > - hws[IMX8MP_SYS_PLL1_200M] =
> > imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
> > > - hws[IMX8MP_SYS_PLL1_266M] =
> > imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
> > > - hws[IMX8MP_SYS_PLL1_400M] =
> > imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
> > > + hws[IMX8MP_SYS_PLL1_40M] =
> > imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> > > + hws[IMX8MP_SYS_PLL1_80M] =
> > imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
> > > + hws[IMX8MP_SYS_PLL1_100M] =
> > imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
> > > + hws[IMX8MP_SYS_PLL1_133M] =
> > imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
> > > + hws[IMX8MP_SYS_PLL1_160M] =
> > imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
> > > + hws[IMX8MP_SYS_PLL1_200M] =
> > imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
> > > + hws[IMX8MP_SYS_PLL1_266M] =
> > imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
> > > + hws[IMX8MP_SYS_PLL1_400M] =
> > imx_clk_hw_fixed_factor("sys_pll1_400m",
> > > +"sys_pll1_out", 1, 2);
> > > hws[IMX8MP_SYS_PLL1_800M] =
> > imx_clk_hw_fixed_factor("sys_pll1_800m",
> > > "sys_pll1_out", 1, 1);
> > >
> > > - hws[IMX8MP_SYS_PLL2_50M_CG] =
> > imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 27);
> > > - hws[IMX8MP_SYS_PLL2_100M_CG] =
> > imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 25);
> > > - hws[IMX8MP_SYS_PLL2_125M_CG] =
> > imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 23);
> > > - hws[IMX8MP_SYS_PLL2_166M_CG] =
> > imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 21);
> > > - hws[IMX8MP_SYS_PLL2_200M_CG] =
> > imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 19);
> > > - hws[IMX8MP_SYS_PLL2_250M_CG] =
> > imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 17);
> > > - hws[IMX8MP_SYS_PLL2_333M_CG] =
> > imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 15);
> > > - hws[IMX8MP_SYS_PLL2_500M_CG] =
> > imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base +
> > 0x104, 13);
> > > hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out",
> > > "sys_pll2_bypass", anatop_base + 0x104, 11);
> > >
> > > - hws[IMX8MP_SYS_PLL2_50M] =
> > imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
> > > - hws[IMX8MP_SYS_PLL2_100M] =
> > imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
> > > - hws[IMX8MP_SYS_PLL2_125M] =
> > imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
> > > - hws[IMX8MP_SYS_PLL2_166M] =
> > imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
> > > - hws[IMX8MP_SYS_PLL2_200M] =
> > imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
> > > - hws[IMX8MP_SYS_PLL2_250M] =
> > imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
> > > - hws[IMX8MP_SYS_PLL2_333M] =
> > imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
> > > - hws[IMX8MP_SYS_PLL2_500M] =
> > imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> > > + hws[IMX8MP_SYS_PLL2_50M] =
> > imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
> > > + hws[IMX8MP_SYS_PLL2_100M] =
> > imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
> > > + hws[IMX8MP_SYS_PLL2_125M] =
> > imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> > > + hws[IMX8MP_SYS_PLL2_166M] =
> > imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
> > > + hws[IMX8MP_SYS_PLL2_200M] =
> > imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
> > > + hws[IMX8MP_SYS_PLL2_250M] =
> > imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
> > > + hws[IMX8MP_SYS_PLL2_333M] =
> > imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
> > > + hws[IMX8MP_SYS_PLL2_500M] =
> > imx_clk_hw_fixed_factor("sys_pll2_500m",
> > > +"sys_pll2_out", 1, 2);
> > > hws[IMX8MP_SYS_PLL2_1000M] =
> > > imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> > >
> > > hws[IMX8MP_CLK_A53_DIV] =
> > imx8m_clk_hw_composite_core("arm_a53_div",
> > > imx8mp_a53_sels, ccm_base + 0x8000);
> > > --
> > > 2.25.1
> > >
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates
2022-02-25 8:17 [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Peng Fan (OSS)
` (2 preceding siblings ...)
2022-02-25 8:17 ` [PATCH 3/3] clk: imx8mp: " Peng Fan (OSS)
@ 2022-02-28 12:23 ` Abel Vesa
2022-03-04 8:50 ` Abel Vesa
4 siblings, 0 replies; 9+ messages in thread
From: Abel Vesa @ 2022-02-28 12:23 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: sboyd, robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
linux-clk, devicetree, linux-arm-kernel, linux-kernel, Peng Fan
On 22-02-25 16:17:30, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Same to commit c586f53ae159c6c("clk: imx8mq: remove SYS PLL 1/2 clock gates"),
> This patchset is to remove the pll gate, but still keep the pll out gate
> following NXP vendor tree.
>
For the entire patchset:
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> Peng Fan (3):
> clk: imx8mm: remove SYS PLL 1/2 clock gates
> clk: imx8mn: remove SYS PLL 1/2 clock gates
> clk: imx8mp: remove SYS PLL 1/2 clock gates
>
> drivers/clk/imx/clk-imx8mm.c | 49 ++++++++++++-----------------------
> drivers/clk/imx/clk-imx8mn.c | 50 ++++++++++++------------------------
> drivers/clk/imx/clk-imx8mp.c | 48 ++++++++++++----------------------
> 3 files changed, 48 insertions(+), 99 deletions(-)
>
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates
2022-02-25 8:17 [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Peng Fan (OSS)
` (3 preceding siblings ...)
2022-02-28 12:23 ` [PATCH 0/3] clk: imx8m: remote sys pll1/2 clk gates Abel Vesa
@ 2022-03-04 8:50 ` Abel Vesa
4 siblings, 0 replies; 9+ messages in thread
From: Abel Vesa @ 2022-03-04 8:50 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: sboyd, robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
linux-clk, devicetree, linux-arm-kernel, linux-kernel, Peng Fan
On 22-02-25 16:17:30, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
Applied, thanks!
> Same to commit c586f53ae159c6c("clk: imx8mq: remove SYS PLL 1/2 clock gates"),
> This patchset is to remove the pll gate, but still keep the pll out gate
> following NXP vendor tree.
>
> Peng Fan (3):
> clk: imx8mm: remove SYS PLL 1/2 clock gates
> clk: imx8mn: remove SYS PLL 1/2 clock gates
> clk: imx8mp: remove SYS PLL 1/2 clock gates
>
> drivers/clk/imx/clk-imx8mm.c | 49 ++++++++++++-----------------------
> drivers/clk/imx/clk-imx8mn.c | 50 ++++++++++++------------------------
> drivers/clk/imx/clk-imx8mp.c | 48 ++++++++++++----------------------
> 3 files changed, 48 insertions(+), 99 deletions(-)
>
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 9+ messages in thread