[PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display

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* [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display
@ 2025-03-27 15:52 Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 1/8] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay
                   ` (7 more replies)
  0 siblings, 8 replies; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

Add inital support for 2 variants of the Moduline Display controller.
This system is powered by the Ka-Ro Electronics tx8p-ml81 COM, which
features an imx8mp SoC.

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
Changes in v3:
- Set regulator-boot-on and always-on on LDO5 of the pmic, after 20 ish
  seconds it auto disabled this LDO causing weird behaviour like
  ethernet droping out, wifi not working anymore. This LDO can control
  the IO voltage level of certain pins, just let it keep the u-boot
  value.
- Fix the comment style in imx8mp-pinfunc.h
- Rebase on newest next tag
- Link to v2: https://lore.kernel.org/r/20250226-initial_display-v2-0-23fafa130817@gocontroll.com

Changes in v2:
- Dropped the trivial-devices patch
- Added a patch with bindings for the gocontroll,moduline-module-slot
- Added a patch to spidev.c to enable the spidev driver for the module
  slot
- Added a missing usb-c connector in the av101hdt-a10 variant dts
- Switched to the new bindings for the module slots in the base dts
- Fixed some commit typos
- Link to v1: https://lore.kernel.org/r/20250224-initial_display-v1-0-5ccbbf613543@gocontroll.com

---
Maud Spierings (8):
      dt-bindings: arm: fsl: Add GOcontroll Moduline Display
      arm64: dts: imx8mp: Add pinctrl config definitions
      MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module
      MAINTAINERS: add maintainer for the GOcontroll Moduline controllers
      arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM
      arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard
      arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display
      arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display

 Documentation/devicetree/bindings/arm/fsl.yaml     |   1 +
 MAINTAINERS                                        |  12 +
 arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h     |  27 +
 ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 ++++
 ...tx8p-ml81-moduline-display-106-av123z7m-n17.dts | 133 +++++
 .../imx8mp-tx8p-ml81-moduline-display-106.dtsi     | 535 ++++++++++++++++++++
 .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
 7 files changed, 1357 insertions(+)
---
base-commit: db8da9da41bced445077925f8a886c776a47440c
change-id: 20250224-initial_display-fa82218e06e5

Best regards,
-- 
Maud Spierings <maudspierings@gocontroll.com>




^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 1/8] dt-bindings: arm: fsl: Add GOcontroll Moduline Display
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Maud Spierings via B4 Relay
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Document the compatible strings for the Moduline Display controller.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 1b90870958a22e49355dd1f932bf3d84cd864b5f..ecde2123ea0fae38ef233929c7ad343812851a58 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1095,6 +1095,7 @@ properties:
               - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
+              - gocontroll,moduline-display # GOcontroll Moduline Display controller
               - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
               - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
               - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 1/8] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 16:01   ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitionsy Frank Li
  2025-03-27 15:52 ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module Maud Spierings via B4 Relay
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this
register is written in the dts, these values are not obvious. Add defines
which describe the fields of this register which can be or-ed together to
produce readable settings.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
This patch has already been sent in a different group of patches: [1]
It was requested there to submit it along with a user, this series also
includes some users for it.

[1]: https://lore.kernel.org/all/20250218-pinctrl_defines-v2-2-c554cad0e1d2@gocontroll.com/
---
 arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 27 ++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
index 0fef066471ba607be02d0ab15da5a048a8a213a7..34a6d3090926b8d9d7c96d1b0b01be0ed05cbd27 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
@@ -6,6 +6,33 @@
 #ifndef __DTS_IMX8MP_PINFUNC_H
 #define __DTS_IMX8MP_PINFUNC_H
 
+/* Drive Strength */
+#define MX8MP_DSE_X1 0x0
+#define MX8MP_DSE_X2 0x4
+#define MX8MP_DSE_X4 0x2
+#define MX8MP_DSE_X6 0x6
+
+/* Slew Rate */
+#define MX8MP_FSEL_FAST 0x10
+#define MX8MP_FSEL_SLOW 0x0
+
+/* Open Drain */
+#define MX8MP_ODE_ENABLE 0x20
+#define MX8MP_ODE_DISABLE 0x0
+
+#define MX8MP_PULL_DOWN 0x0
+#define MX8MP_PULL_UP 0x40
+
+/* Hysteresis */
+#define MX8MP_HYS_CMOS 0x0
+#define MX8MP_HYS_SCHMITT 0x80
+
+#define MX8MP_PULL_ENABLE 0x100
+#define MX8MP_PULL_DISABLE 0x0
+
+/* SION force input mode */
+#define MX8MP_SION 0x40000000
+
 /*
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 1/8] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 16:03   ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM moduley Frank Li
  2025-03-27 15:52 ` [PATCH v3 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers Maud Spierings via B4 Relay
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Add GOcontroll as unofficial maintainers of the Ka-Ro tx8p-ml81 COM
module bindings.

This support is not officially done by Ka-Ro electronics, if they at
some point will supporting mainline, this should be changed to them.

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 322ee00547f6e494a96d2495092f72148da22bd0..f8ad2c1023016d7f72cccff880e3753d71d635b2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12752,6 +12752,12 @@ S:	Maintained
 F:	Documentation/hwmon/k8temp.rst
 F:	drivers/hwmon/k8temp.c
 
+KA-RO TX8P COM MODULE
+M:	Maud Spierings <maudspierings@gocontroll.com>
+L:	devicetree@vger.kernel.org
+S:	Maintained
+F:	arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
+
 KASAN
 M:	Andrey Ryabinin <ryabinin.a.a@gmail.com>
 R:	Alexander Potapenko <glider@google.com>

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
                   ` (2 preceding siblings ...)
  2025-03-27 15:52 ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Maud Spierings via B4 Relay
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Add a maintainer for the GOcontroll Moduline series of controllers.

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f8ad2c1023016d7f72cccff880e3753d71d635b2..123f03d8f8bdeec6bc947044a0c46b84764863ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10043,6 +10043,12 @@ L:	linux-media@vger.kernel.org
 S:	Maintained
 F:	drivers/media/usb/go7007/
 
+GOCONTROLL MODULINE CONTROLLERS
+M:	Maud Spierings <maudspierings@gocontroll.com>
+L:	devicetree@vger.kernel.org
+S:	Maintained
+F:	arch/arm64/boot/dts/freescale/*moduline*.dts*
+
 GOCONTROLL MODULINE MODULE SLOT
 M:	Maud Spierings <maudspierings@gocontroll.com>
 S:	Maintained

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
                   ` (3 preceding siblings ...)
  2025-03-27 15:52 ` [PATCH v3 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 16:18   ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy Frank Li
  2025-03-27 15:52 ` [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard Maud Spierings via B4 Relay
                   ` (2 subsequent siblings)
  7 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has
2 GB or ram and 8 GB of eMMC storage on board.

Add it to enable boards based on this Module

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
 .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
 1 file changed, 549 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da377319eda8506
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
@@ -0,0 +1,549 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ * 2025 Maud Spierings <maudspierings@gocontroll.com>
+ */
+
+#include "imx8mp.dtsi"
+
+/ {
+	/* PHY regulator */
+	regulator-3v3-etn {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_3v3_etn>;
+		regulator-name = "3v3-etn";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_vdd_3v3>;
+		gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_1 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_2 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_3 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+
+&eqos {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_eqos>;
+	pinctrl-1 = <&pinctrl_eqos_sleep>;
+	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
+			  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+			  <&clk IMX8MP_CLK_ENET_QOS>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+				 <&clk IMX8MP_SYS_PLL2_100M>,
+				 <&clk IMX8MP_SYS_PLL2_50M>;
+	assigned-clock-rates = <0>, <100000000>, <50000000>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ethphy_rst_b>;
+		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <25000>;
+
+		ethphy0: ethernet-phy@0 {
+			reg = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_ethphy_int_b>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+			clocks = <&clk IMX8MP_CLK_ENET_QOS>;
+			smsc,disable-energy-detect;
+		};
+	};
+};
+
+&gpio1 {
+	gpio-line-names = "SODIMM_152",
+		"SODIMM_42",
+		"PMIC_WDOG_B SODIMM_153",
+		"PMIC_IRQ_B",
+		"SODIMM_154",
+		"SODIMM_155",
+		"SODIMM_156",
+		"SODIMM_157",
+		"SODIMM_158",
+		"SODIMM_159",
+		"SODIMM_161",
+		"SODIMM_162",
+		"SODIMM_34",
+		"SODIMM_36",
+		"SODIMM_27",
+		"SODIMM_28",
+		"ENET_MDC",
+		"ENET_MDIO",
+		"",
+		"ENET_XTAL1/CLKIN",
+		"ENET_TXD1",
+		"ENET_TXD0",
+		"ENET_TXEN",
+		"ENET_POWER",
+		"ENET_COL/CRS_DV",
+		"ENET_RXER",
+		"ENET_RXD0",
+		"ENET_RXD1",
+		"",
+		"",
+		"",
+		"";
+};
+
+&gpio2 {
+	gpio-line-names = "",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"SODIMM_51",
+		"SODIMM_57",
+		"SODIMM_56",
+		"SODIMM_52",
+		"SODIMM_53",
+		"SODIMM_54",
+		"SODIMM_55",
+		"SODIMM_15",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"";
+};
+
+&gpio3 {
+	gpio-line-names = "",
+		"",
+		"EMMC_DS",
+		"EMMC_DAT5",
+		"EMMC_DAT6",
+		"EMMC_DAT7",
+		"",
+		"",
+		"",
+		"",
+		"EMMC_DAT0",
+		"EMMC_DAT1",
+		"EMMC_DAT2",
+		"EMMC_DAT3",
+		"",
+		"EMMC_DAT4",
+		"",
+		"EMMC_CLK",
+		"EMMC_CMD",
+		"SODIMM_75",
+		"SODIMM_145",
+		"SODIMM_163",
+		"SODIMM_164",
+		"SODIMM_165",
+		"SODIMM_143",
+		"SODIMM_144",
+		"SODIMM_72",
+		"SODIMM_73",
+		"SODIMM_74",
+		"SODIMM_93",
+		"",
+		"";
+};
+
+&gpio4 {
+	gpio-line-names = "SODIMM_98",
+		"SODIMM_99",
+		"SODIMM_100",
+		"SODIMM_101",
+		"SODIMM_45",
+		"SODIMM_43",
+		"SODIMM_105",
+		"SODIMM_106",
+		"SODIMM_107",
+		"SODIMM_108",
+		"SODIMM_104",
+		"SODIMM_103",
+		"SODIMM_115",
+		"SODIMM_114",
+		"SODIMM_113",
+		"SODIMM_112",
+		"SODIMM_109",
+		"SODIMM_110",
+		"SODIMM_95",
+		"SODIMM_96",
+		"SODIMM_97",
+		"ENET_nINT",
+		"ENET_nRST",
+		"SODIMM_84",
+		"SODIMM_87",
+		"SODIMM_86",
+		"SODIMM_85",
+		"SODIMM_83",
+		"",
+		"SODIMM_66",
+		"SODIMM_65",
+		"";
+};
+
+&gpio5 {
+	gpio-line-names = "",
+		"",
+		"",
+		"SODIMM_76",
+		"SODIMM_81",
+		"SODIMM_146",
+		"SODIMM_48",
+		"SODIMM_46",
+		"SODIMM_47",
+		"SODIMM_44",
+		"SODIMM_49",
+		"",
+		"SODIMM_70",
+		"SODIMM_69",
+		"PMIC_SCL",
+		"PMIC_SDA",
+		"SODIMM_41",
+		"SODIMM_40",
+		"SODIMM_148",
+		"SODIMM_149",
+		"SODIMM_150",
+		"SODIMM_151",
+		"SODIMM_60",
+		"SODIMM_59",
+		"SODIMM_64",
+		"SODIMM_63",
+		"SODIMM_62",
+		"SODIMM_61",
+		"SODIMM_68",
+		"SODIMM_67",
+		"",
+		"";
+};
+
+&i2c1 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	clock-frequency = <400000>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pmic@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			reg_vdd_soc: BUCK1 {
+				regulator-name = "vdd-soc";
+				regulator-min-microvolt = <805000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			reg_vdd_arm: BUCK2 {
+				regulator-name = "vdd-core";
+				regulator-min-microvolt = <805000>;
+				regulator-max-microvolt = <950000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			reg_vdd_3v3: BUCK4 {
+				regulator-name = "3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_nvcc_nand: BUCK5 {
+				regulator-name = "nvcc-nand";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_nvcc_dram: BUCK6 {
+				regulator-name = "nvcc-dram";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_snvs_1v8: LDO1 {
+				regulator-name = "snvs-1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+			};
+
+			reg_vdda_1v8: LDO3 {
+				regulator-name = "vdda-1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&usdhc3 { /* eMMC */
+	max-frequency = <200000000>;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	vmmc-supply = <&reg_vdd_3v3>;
+	vqmmc-supply = <&reg_nvcc_nand>;
+	voltage-ranges = <3300 3300>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK
+			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
+			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
+			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER
+			(MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
+		>;
+	};
+
+	pinctrl_eqos_sleep: eqos-sleep-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22
+			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_ethphy_int_b: ethphy-int-bgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21
+			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)
+		>;
+	};
+
+	pinctrl_ethphy_rst_b: ethphy-rst-bgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
+			(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_reg_3v3_etn: reg-3v3-etngrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
+			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
+			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
+			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+};

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
                   ` (4 preceding siblings ...)
  2025-03-27 15:52 ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 16:26   ` [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboardy Frank Li
  2025-03-27 15:52 ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Maud Spierings via B4 Relay
  2025-03-27 15:52 ` [PATCH v3 8/8] arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display Maud Spierings via B4 Relay
  7 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

The Moduline Display platform is a part of the wider GOcontroll Moduline
ecosystem. These are embedded controllers that focus on modularity with
their swappable IO modules.

The base Moduline Display board includes a board-to-board connector with
various busses to enable adding new display types required by the
application. It includes 2 Moduline IO module slots, a simple mono
codec/amplifier, a four channel adc, 2 CAN busses, an RTC and optional
wifi/bluetooth.

busses to the display adapter include:
- 4 lane LVDS
- 4 lane MIPI-DSI
- 4 lane MIPI-CSI
- HDMI 2.0a
- USB 2.0
- I2S
- I2C
- SPI

Also a couple of GPIO and PWM pins for controlling various ICs on the
display adapter board.

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
 .../imx8mp-tx8p-ml81-moduline-display-106.dtsi     | 535 +++++++++++++++++++++
 1 file changed, 535 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a3ab389c9744f5189d5a8a802aa4c4ebb9f7b12b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2025 GOcontroll B.V.
+ * Author: Maud Spierings <maudspierings@gocontroll.com>
+ */
+
+#include "imx8mp-tx8p-ml81.dtsi"
+
+/ {
+	chassis-type = "embedded";
+	compatible = "gocontroll,moduline-display", "fsl,imx8mp";
+	hardware =  "Moduline Display V1.06";
+
+	aliases {
+		ethernet0 = &eqos;
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc2;
+		spi0 = &ecspi2; /* spidev number compatibility */
+		spi1 = &ecspi1; /* spidev number compatibility */
+		can0 = &flexcan1;
+		can1 = &flexcan2;
+		rtc0 = &rtc_pcf; /* i2c rtc is the main rtc */
+		rtc1 = &snvs_rtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	external-sensor-supply {
+		compatible = "regulator-output";
+		vout-supply = <&reg_5v0_sensor>;
+	};
+
+	reg_can1_stby: regulator-can1-stby {
+		compatible = "regulator-fixed";
+		regulator-name = "can1-stby";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan1_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-stby";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan2_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_1v8_per: regulator-1v8-per {
+		compatible = "regulator-fixed";
+		regulator-name = "1v8-per";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_1v8>;
+		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		power-supply = <&reg_3v3_per>;
+	};
+
+	reg_3v3_per: regulator-3v3-per {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3-per";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		power-supply = <&reg_6v4>;
+	};
+
+	reg_5v0_sensor: regulator-5v0-sensor {
+		compatible = "regulator-fixed";
+		regulator-name = "5v0-supply-external-sensor";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_5v0_sensor>;
+		gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		power-supply = <&reg_6v4>;
+	};
+
+	reg_6v4: regulator-6v4 {
+		compatible = "regulator-fixed";
+		regulator-name = "6v4";
+		regulator-min-microvolt = <6400000>;
+		regulator-max-microvolt = <6400000>;
+		regulator-always-on;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "tas2505-audio";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&cpudai>;
+		simple-audio-card,bitclock-master = <&cpudai>;
+		simple-audio-card,widgets =
+		"Speaker", "Speaker External";
+		simple-audio-card,routing =
+		"Speaker", "DAC";
+
+		cpudai: simple-audio-card,cpu {
+			sound-dai = <&sai6>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&tas2505>;
+		};
+	};
+
+	wifi_powerseq: wifi-powerseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wl_reg>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <500000>;
+		reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <
+	&gpio2 12 GPIO_ACTIVE_LOW
+	&gpio1 11 GPIO_ACTIVE_LOW
+	&gpio1 10 GPIO_ACTIVE_LOW
+	>;
+	status = "okay";
+
+	connector@0 {
+		compatible = "gocontroll,moduline-module-slot";
+		reg = <0>;
+		reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+		sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+		vdd-supply = <&reg_3v3_per>;
+		vddp-supply = <&reg_5v0>;
+		vddhpp-supply = <&reg_6v4>;
+		i2c-bus = <&i2c2>;
+		slot-number = <1>;
+		spi-max-frequency = <54000000>;
+
+	};
+
+	connector@1 {
+		compatible = "gocontroll,moduline-module-slot";
+		reg = <1>;
+		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+		vdd-supply = <&reg_3v3_per>;
+		vddp-supply = <&reg_5v0>;
+		vddhpp-supply = <&reg_6v4>;
+		i2c-bus = <&i2c2>;
+		slot-number = <2>;
+		spi-max-frequency = <54000000>;
+	};
+
+	adc@2 {
+		compatible = "microchip,mcp3004";
+		reg = <2>;
+		spi-max-frequency = <2300000>;
+		vref-supply = <&reg_vdd_3v3>;
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_stby>;
+	status = "okay";
+};
+
+/* I2C2 bus to modules */
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	tas2505: tas2505@18 {
+		compatible = "ti,tas2505";
+		reg = <0x18>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tas_reset>;
+		reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+
+		dv-supply = <&reg_1v8_per>;
+		iov-supply = <&reg_vdd_3v3>;
+		av-supply = <&reg_1v8_per>;
+
+		clocks = <&clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>;
+		clock-names = "mclk";
+		aic32x4-gpio-func= <
+			0xff
+			0xff
+			0xff
+			0xff
+			0xff
+		>;
+	};
+
+	rtc_pcf: rtc@51 {
+		compatible = "nxp,pcf85063a";
+		reg = <0x51>;
+		quartz-load-femtofarads = <7000>;
+
+		clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+};
+
+/* tas2505 */
+&sai6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai6>;
+	status = "okay";
+	assigned-clocks = <&clk IMX8MP_CLK_SAI6>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <12288000>;
+	fsl,sai-mclk-direction-output;
+};
+
+/* debug/external */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
+	status = "okay";
+
+	/* muRata 1YN/1DX */
+	bluetooth {
+		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
+		max-speed = <921600>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_bt>;
+		device-wakeup-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-names = "host-wakeup";
+		vddio-supply = <&reg_3v3_per>;
+		vbat-supply = <&reg_3v3_per>;
+	};
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "peripheral";
+};
+
+&usdhc2 {
+	max-frequency = <50000000>;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+	assigned-clock-rates = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	mmc-pwrseq = <&wifi_powerseq>;
+	vmmc-supply = <&reg_3v3_per>;
+
+	cap-power-off-card;
+	keep-power-in-suspend;
+	non-removable;
+	sd-uhs-sdr25;
+
+	status = "okay";
+
+	/* muRata 1YN/1DX */
+	wifi@1 {
+		compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
+		reg = <1>;
+		brcm,board-type = "GOcontroll,moduline";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wl_int>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "host-wake";
+	};
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_reg_1v8: reg-1v8-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 /* COM pin 144 */
+			MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_reg_5v0_sensor: reg-5v0-sensorgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 /* COM pin 108 */
+			MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_tas_reset: tasresetgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 /* COM pin 143 */
+			MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 /* COM pin 27 */
+			MX8MP_DSE_X1
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 /* COM pin 34 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_HYS_SCHMITT)
+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 /* COM pin 28 */
+			MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+		MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI /* COM pin 46 */
+		MX8MP_DSE_X4
+		MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO /* COM pin 47 */
+		(MX8MP_DSE_X4 | MX8MP_HYS_SCHMITT)
+		MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK /* COM pin 48 */
+		MX8MP_DSE_X4
+		MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 /* COM pin 51 */
+		MX8MP_DSE_X1
+		MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 /* COM pin 162 */
+		MX8MP_DSE_X1
+		MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 /* COM pin 161 */
+		MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX /* COM pin 81 */
+			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX /* COM pin 76 */
+			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_flexcan1_reg: flexcan1reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 /* COM pin 101 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			 MX8MP_IOMUXC_UART3_TXD__CAN2_RX /* COM pin 61 */
+			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			 MX8MP_IOMUXC_UART3_RXD__CAN2_TX /* COM pin 62 */
+			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_flexcan2_reg: flexcan2reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 /* COM pin 44 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL /* COM pin 41 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA /* COM pin 40 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 /* COM pin 41 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 /* COM pin 40 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL /* COM pin 70 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA /* COM pin 69 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 /* COM pin 70 */
+			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 /* COM pin 69 */
+			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
+		>;
+	};
+
+	pinctrl_sai6: sai6grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC /* COM pin 95 */
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+			MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK /* COM pin 105 */
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+			MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 /* COM pin 110 */
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+			MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK /* COM pin 96 */
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+			MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 /* COM pin 106 */
+			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX /* COM pin 60 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX /* COM pin 59 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX /* COM pin 64 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX /* COM pin 63 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS /* COM pin 65 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS /* COM pin 66 */
+			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_usdhc2: pinctrlusdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK /* COM pin 57 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD /* COM pin 56 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 /* COM pin 52 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 /* COM pin 53 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 /* COM pin 54 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 /* COM pin 55 */
+			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B /* COM pin 153 */
+			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
+		>;
+	};
+
+	pinctrl_wl_int: wlintgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 /* COM pin 36 */
+			(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
+		>;
+	};
+
+	pinctrl_wl_reg: wlreggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 /* COM pin 15 */
+			MX8MP_DSE_X1
+		>;
+	};
+};

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
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@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  2025-03-27 16:31   ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy Frank Li
  2025-03-27 15:52 ` [PATCH v3 8/8] arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display Maud Spierings via B4 Relay
  7 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Add the BOE av101hdt-a10 variant of the Moduline Display, this variant
comes with a 10.1 1280x720 display with a touchscreen (not working in
mainline).

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>

---
Currently the backlight driver is not available, this will be upstreamed
in a future patch series. It is a Maxim max25014atg.

The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as
I know is not supported upstream, the driver we currently use for this is
a mess and I doubt we will be able to get it in an upstreamable state.
---
 ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 +++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
new file mode 100644
index 0000000000000000000000000000000000000000..1917e22001a1815a6540f00cf039ff352801cda8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2025 GOcontroll B.V.
+ * Author: Maud Spierings <maudspierings@gocontroll.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi"
+
+/ {
+	model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
+
+	panel {
+		compatible = "boe,av101hdt-a10";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_panel>;
+		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		power-supply = <&reg_3v3_per>;
+
+		port {
+			panel_lvds_in: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+
+	reg_vbus: regulator-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb-c-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		power-supply = <&reg_6v4>;
+		regulator-always-on;
+	};
+};
+
+&lcdif2 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+
+	port {
+		usb1_hs_ep: endpoint {
+			remote-endpoint = <&high_speed_ep>;
+		};
+	};
+
+	connector {
+		compatible = "usb-c-connector";
+		pd-disable;
+		data-role = "host";
+		vbus-supply = <&reg_vbus>;
+
+		port {
+			high_speed_ep: endpoint {
+				remote-endpoint = <&usb1_hs_ep>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
+	<&clk IMX8MP_VIDEO_PLL1>;
+	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */
+	assigned-clock-rates = <0>, <1054620000>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&panel_lvds_in>;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_panel: panelgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */
+			MX8MP_DSE_X1
+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */
+			MX8MP_DSE_X1
+		>;
+	};
+};

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 8/8] arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display
  2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
                   ` (6 preceding siblings ...)
  2025-03-27 15:52 ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Maud Spierings via B4 Relay
@ 2025-03-27 15:52 ` Maud Spierings via B4 Relay
  7 siblings, 0 replies; 19+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-03-27 15:52 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
  Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings

From: Maud Spierings <maudspierings@gocontroll.com>

Add the BOE av123z7m-n17 variant of the Moduline Display, this variant
comes with a 12.3" 1920x720 display.

Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>

---
Currently the backlight driver is not available, this will be upstreamed
in a future patch series. It is a Maxim max25014atg.
---
 ...tx8p-ml81-moduline-display-106-av123z7m-n17.dts | 133 +++++++++++++++++++++
 1 file changed, 133 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dts
new file mode 100644
index 0000000000000000000000000000000000000000..129c69598f38566460efb271628c1d1e10eb2a85
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2025 GOcontroll B.V.
+ * Author: Maud Spierings <maudspierings@gocontroll.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi"
+
+/ {
+	model = "GOcontroll Moduline Display with BOE av123z7m-n17 display";
+
+	panel {
+		compatible = "boe,av123z7m-n17";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_panel>;
+		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		power-supply = <&reg_3v3_per>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				dual-lvds-odd-pixels;
+
+				panel_in0: endpoint {
+					remote-endpoint = <&lvds1_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				dual-lvds-even-pixels;
+
+				panel_in1: endpoint {
+					remote-endpoint = <&lvds0_out>;
+				};
+			};
+		};
+	};
+};
+
+&i2c4 {
+	bridge@2d { /* sn65dsi85 */
+		compatible = "ti,sn65dsi84";
+		reg = <0x2d>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_bridge>;
+		enable-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+		vcc-supply = <&reg_1v8_per>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				dsi_lvds_bridge_in: endpoint {
+					remote-endpoint = <&mipi_dsi_out>;
+					data-lanes = <1 2 3 4>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				lvds0_out: endpoint {
+					remote-endpoint = <&panel_in1>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+
+				lvds1_out: endpoint {
+					remote-endpoint = <&panel_in0>;
+				};
+			};
+		};
+	};
+
+	/* max25014 @ 0x6f */
+};
+
+&lcdif1 {
+	status = "okay";
+};
+
+&mipi_dsi {
+	samsung,esc-clock-frequency = <12000000>;
+	/*
+	 * burst has to be at least 2x dsi clock that the sn65dsi85 expects
+	 * display pixelclock * bpp / lanes / 2 = dsi clock
+	 * 88.000.000 * 24 / 4 / 2 = 264.000.000
+	 * range gets rounded up to 265.000.000 - 270.000.000
+	 * 267.500.000 * 2 = 535.000.000
+	 */
+	samsung,burst-clock-frequency = <535000000>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			mipi_dsi_out: endpoint {
+				remote-endpoint = < &dsi_lvds_bridge_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_lvds_bridge: lvdsbridgegrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 /* COM pin 113 */
+			MX8MP_DSE_X1
+		>;
+	};
+
+	pinctrl_panel: panelgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */
+			MX8MP_DSE_X1
+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */
+			MX8MP_DSE_X1
+		>;
+	};
+};

-- 
2.49.0




^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitionsy
  2025-03-27 15:52 ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Maud Spierings via B4 Relay
@ 2025-03-27 16:01   ` Frank Li
  0 siblings, 0 replies; 19+ messages in thread
From: Frank Li @ 2025-03-27 16:01 UTC (permalink / raw)
  To: maudspierings
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Thu, Mar 27, 2025 at 04:52:37PM +0100, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maudspierings@gocontroll.com>
>
> Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this
> register is written in the dts, these values are not obvious. Add defines
> which describe the fields of this register which can be or-ed together to
> produce readable settings.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> This patch has already been sent in a different group of patches: [1]
> It was requested there to submit it along with a user, this series also
> includes some users for it.
>
> [1]: https://lore.kernel.org/all/20250218-pinctrl_defines-v2-2-c554cad0e1d2@gocontroll.com/
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 27 ++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
> index 0fef066471ba607be02d0ab15da5a048a8a213a7..34a6d3090926b8d9d7c96d1b0b01be0ed05cbd27 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
> @@ -6,6 +6,33 @@
>  #ifndef __DTS_IMX8MP_PINFUNC_H
>  #define __DTS_IMX8MP_PINFUNC_H
>
> +/* Drive Strength */
> +#define MX8MP_DSE_X1 0x0
> +#define MX8MP_DSE_X2 0x4
> +#define MX8MP_DSE_X4 0x2
> +#define MX8MP_DSE_X6 0x6
> +
> +/* Slew Rate */
> +#define MX8MP_FSEL_FAST 0x10
> +#define MX8MP_FSEL_SLOW 0x0
> +
> +/* Open Drain */
> +#define MX8MP_ODE_ENABLE 0x20
> +#define MX8MP_ODE_DISABLE 0x0
> +
> +#define MX8MP_PULL_DOWN 0x0
> +#define MX8MP_PULL_UP 0x40
> +
> +/* Hysteresis */
> +#define MX8MP_HYS_CMOS 0x0
> +#define MX8MP_HYS_SCHMITT 0x80
> +
> +#define MX8MP_PULL_ENABLE 0x100
> +#define MX8MP_PULL_DISABLE 0x0
> +
> +/* SION force input mode */
> +#define MX8MP_SION 0x40000000
> +
>  /*
>   * The pin function ID is a tuple of
>   * <mux_reg conf_reg input_reg mux_mode input_val>
>
> --
> 2.49.0
>
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM moduley
  2025-03-27 15:52 ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module Maud Spierings via B4 Relay
@ 2025-03-27 16:03   ` Frank Li
  0 siblings, 0 replies; 19+ messages in thread
From: Frank Li @ 2025-03-27 16:03 UTC (permalink / raw)
  To: maudspierings
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Thu, Mar 27, 2025 at 04:52:38PM +0100, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maudspierings@gocontroll.com>
>
> Add GOcontroll as unofficial maintainers of the Ka-Ro tx8p-ml81 COM
> module bindings.
>
> This support is not officially done by Ka-Ro electronics, if they at
> some point will supporting mainline, this should be changed to them.
>
> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> ---
>  MAINTAINERS | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 322ee00547f6e494a96d2495092f72148da22bd0..f8ad2c1023016d7f72cccff880e3753d71d635b2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -12752,6 +12752,12 @@ S:	Maintained
>  F:	Documentation/hwmon/k8temp.rst
>  F:	drivers/hwmon/k8temp.c
>
> +KA-RO TX8P COM MODULE
> +M:	Maud Spierings <maudspierings@gocontroll.com>
> +L:	devicetree@vger.kernel.org

Need
+L: imx@lists.linux.dev

> +S:	Maintained
> +F:	arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
> +
>  KASAN
>  M:	Andrey Ryabinin <ryabinin.a.a@gmail.com>
>  R:	Alexander Potapenko <glider@google.com>
>
> --
> 2.49.0
>
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy
  2025-03-27 15:52 ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Maud Spierings via B4 Relay
@ 2025-03-27 16:18   ` Frank Li
  2025-03-28  7:20     ` Maud Spierings | GOcontroll
  0 siblings, 1 reply; 19+ messages in thread
From: Frank Li @ 2025-03-27 16:18 UTC (permalink / raw)
  To: maudspierings
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Thu, Mar 27, 2025 at 04:52:40PM +0100, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maudspierings@gocontroll.com>
>
> The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has
> 2 GB or ram and 8 GB of eMMC storage on board.
>
> Add it to enable boards based on this Module
>
> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> ---
>  .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
>  1 file changed, 549 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da377319eda8506
> --- /dev/null

New dts files, suggest run https://github.com/lznuaa/dt-format to make
nodes and property ordered.

> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
> @@ -0,0 +1,549 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
> + * 2025 Maud Spierings <maudspierings@gocontroll.com>
> + */
> +
> +#include "imx8mp.dtsi"
> +
> +/ {
> +	/* PHY regulator */
> +	regulator-3v3-etn {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_3v3_etn>;
> +		regulator-name = "3v3-etn";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		vin-supply = <&reg_vdd_3v3>;
> +		gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		regulator-always-on;
> +		regulator-boot-on;
> +	};
> +};
> +
> +&A53_0 {
> +	cpu-supply = <&reg_vdd_arm>;
> +};
> +
> +&A53_1 {
> +	cpu-supply = <&reg_vdd_arm>;
> +};
> +
> +&A53_2 {
> +	cpu-supply = <&reg_vdd_arm>;
> +};
> +
> +&A53_3 {
> +	cpu-supply = <&reg_vdd_arm>;
> +};
> +
> +
> +&eqos {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	pinctrl-1 = <&pinctrl_eqos_sleep>;
> +	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
> +			  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
> +			  <&clk IMX8MP_CLK_ENET_QOS>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
> +				 <&clk IMX8MP_SYS_PLL2_100M>,
> +				 <&clk IMX8MP_SYS_PLL2_50M>;
> +	assigned-clock-rates = <0>, <100000000>, <50000000>;
> +	phy-mode = "rmii";
> +	phy-handle = <&ethphy0>;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";

"compatible" should be first property.

> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ethphy_rst_b>;
> +		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> +		reset-delay-us = <25000>;
> +
> +		ethphy0: ethernet-phy@0 {
> +			reg = <0>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pinctrl_ethphy_int_b>;
> +			interrupt-parent = <&gpio4>;
> +			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
> +			clocks = <&clk IMX8MP_CLK_ENET_QOS>;
> +			smsc,disable-energy-detect;
> +		};
> +	};
> +};
> +
> +&gpio1 {
> +	gpio-line-names = "SODIMM_152",
> +		"SODIMM_42",
> +		"PMIC_WDOG_B SODIMM_153",
> +		"PMIC_IRQ_B",
> +		"SODIMM_154",
> +		"SODIMM_155",
> +		"SODIMM_156",
> +		"SODIMM_157",
> +		"SODIMM_158",
> +		"SODIMM_159",
> +		"SODIMM_161",
> +		"SODIMM_162",
> +		"SODIMM_34",
> +		"SODIMM_36",
> +		"SODIMM_27",
> +		"SODIMM_28",
> +		"ENET_MDC",
> +		"ENET_MDIO",
> +		"",
> +		"ENET_XTAL1/CLKIN",
> +		"ENET_TXD1",
> +		"ENET_TXD0",
> +		"ENET_TXEN",
> +		"ENET_POWER",
> +		"ENET_COL/CRS_DV",
> +		"ENET_RXER",
> +		"ENET_RXD0",
> +		"ENET_RXD1",
> +		"",
> +		"",
> +		"",
> +		"";
> +};
> +
> +&gpio2 {
> +	gpio-line-names = "",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"SODIMM_51",
> +		"SODIMM_57",
> +		"SODIMM_56",
> +		"SODIMM_52",
> +		"SODIMM_53",
> +		"SODIMM_54",
> +		"SODIMM_55",
> +		"SODIMM_15",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"";
> +};
> +
> +&gpio3 {
> +	gpio-line-names = "",
> +		"",
> +		"EMMC_DS",
> +		"EMMC_DAT5",
> +		"EMMC_DAT6",
> +		"EMMC_DAT7",
> +		"",
> +		"",
> +		"",
> +		"",
> +		"EMMC_DAT0",
> +		"EMMC_DAT1",
> +		"EMMC_DAT2",
> +		"EMMC_DAT3",
> +		"",
> +		"EMMC_DAT4",
> +		"",
> +		"EMMC_CLK",
> +		"EMMC_CMD",
> +		"SODIMM_75",
> +		"SODIMM_145",
> +		"SODIMM_163",
> +		"SODIMM_164",
> +		"SODIMM_165",
> +		"SODIMM_143",
> +		"SODIMM_144",
> +		"SODIMM_72",
> +		"SODIMM_73",
> +		"SODIMM_74",
> +		"SODIMM_93",
> +		"",
> +		"";
> +};
> +
> +&gpio4 {
> +	gpio-line-names = "SODIMM_98",
> +		"SODIMM_99",
> +		"SODIMM_100",
> +		"SODIMM_101",
> +		"SODIMM_45",
> +		"SODIMM_43",
> +		"SODIMM_105",
> +		"SODIMM_106",
> +		"SODIMM_107",
> +		"SODIMM_108",
> +		"SODIMM_104",
> +		"SODIMM_103",
> +		"SODIMM_115",
> +		"SODIMM_114",
> +		"SODIMM_113",
> +		"SODIMM_112",
> +		"SODIMM_109",
> +		"SODIMM_110",
> +		"SODIMM_95",
> +		"SODIMM_96",
> +		"SODIMM_97",
> +		"ENET_nINT",
> +		"ENET_nRST",
> +		"SODIMM_84",
> +		"SODIMM_87",
> +		"SODIMM_86",
> +		"SODIMM_85",
> +		"SODIMM_83",
> +		"",
> +		"SODIMM_66",
> +		"SODIMM_65",
> +		"";
> +};
> +
> +&gpio5 {
> +	gpio-line-names = "",
> +		"",
> +		"",
> +		"SODIMM_76",
> +		"SODIMM_81",
> +		"SODIMM_146",
> +		"SODIMM_48",
> +		"SODIMM_46",
> +		"SODIMM_47",
> +		"SODIMM_44",
> +		"SODIMM_49",
> +		"",
> +		"SODIMM_70",
> +		"SODIMM_69",
> +		"PMIC_SCL",
> +		"PMIC_SDA",
> +		"SODIMM_41",
> +		"SODIMM_40",
> +		"SODIMM_148",
> +		"SODIMM_149",
> +		"SODIMM_150",
> +		"SODIMM_151",
> +		"SODIMM_60",
> +		"SODIMM_59",
> +		"SODIMM_64",
> +		"SODIMM_63",
> +		"SODIMM_62",
> +		"SODIMM_61",
> +		"SODIMM_68",
> +		"SODIMM_67",
> +		"",
> +		"";
> +};
> +
> +&i2c1 {
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	pinctrl-1 = <&pinctrl_i2c1_gpio>;
> +	clock-frequency = <400000>;
> +	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +
> +	pmic@25 {
> +		reg = <0x25>;
> +		compatible = "nxp,pca9450c";

Compatible is first,  reg is second.

> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pmic>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> +
> +		regulators {
> +			reg_vdd_soc: BUCK1 {
> +				regulator-name = "vdd-soc";
> +				regulator-min-microvolt = <805000>;
> +				regulator-max-microvolt = <900000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			reg_vdd_arm: BUCK2 {
> +				regulator-name = "vdd-core";
> +				regulator-min-microvolt = <805000>;
> +				regulator-max-microvolt = <950000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +				nxp,dvs-run-voltage = <950000>;
> +				nxp,dvs-standby-voltage = <850000>;
> +			};
> +
> +			reg_vdd_3v3: BUCK4 {
> +				regulator-name = "3v3";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_nvcc_nand: BUCK5 {
> +				regulator-name = "nvcc-nand";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_nvcc_dram: BUCK6 {
> +				regulator-name = "nvcc-dram";
> +				regulator-min-microvolt = <1100000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_snvs_1v8: LDO1 {
> +				regulator-name = "snvs-1v8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo2_reg: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1150000>;
> +				regulator-always-on;
> +			};
> +
> +			reg_vdda_1v8: LDO3 {
> +				regulator-name = "vdda-1v8";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4_reg: LDO4 {
> +				regulator-name = "LDO4";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			ldo5_reg: LDO5 {
> +				regulator-name = "LDO5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&usdhc3 { /* eMMC */
> +	max-frequency = <200000000>;
> +	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
> +	assigned-clock-rates = <200000000>;
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +	bus-width = <8>;
> +	vmmc-supply = <&reg_vdd_3v3>;
> +	vqmmc-supply = <&reg_nvcc_nand>;
> +	voltage-ranges = <3300 3300>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK
> +			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
> +			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
> +			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
> +			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
> +			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
> +		>;
> +	};
> +
> +	pinctrl_eqos_sleep: eqos-sleep-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22
> +			(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_ethphy_int_b: ethphy-int-bgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21
> +			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)
> +		>;
> +	};
> +
> +	pinctrl_ethphy_rst_b: ethphy-rst-bgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_i2c1_gpio: i2c1-gpiogrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_pmic: pmicgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
> +			(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_reg_3v3_etn: reg-3v3-etngrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
> +			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)


It is much better than hex value

The most are the same.  Can you define helper macro to reduce copy long OR

for example

#define USDHC_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)

so pinctrl_usdhc3_100mhz
		fsl,pins = <... (MX8MP_DSE_X2 | USDHC_DEFAULT);

usdhc3-200mhzgrp
		fsl,pins = <... (MX8MP_DSE_X6 | USDHC_DEFAULT);

Frank

> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
> +			(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
> +			(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +};
>
> --
> 2.49.0
>
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboardy
  2025-03-27 15:52 ` [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard Maud Spierings via B4 Relay
@ 2025-03-27 16:26   ` Frank Li
  0 siblings, 0 replies; 19+ messages in thread
From: Frank Li @ 2025-03-27 16:26 UTC (permalink / raw)
  To: maudspierings
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Thu, Mar 27, 2025 at 04:52:41PM +0100, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maudspierings@gocontroll.com>
>
> The Moduline Display platform is a part of the wider GOcontroll Moduline
> ecosystem. These are embedded controllers that focus on modularity with
> their swappable IO modules.
>
> The base Moduline Display board includes a board-to-board connector with
> various busses to enable adding new display types required by the
> application. It includes 2 Moduline IO module slots, a simple mono
> codec/amplifier, a four channel adc, 2 CAN busses, an RTC and optional
> wifi/bluetooth.
>
> busses to the display adapter include:
> - 4 lane LVDS
> - 4 lane MIPI-DSI
> - 4 lane MIPI-CSI
> - HDMI 2.0a
> - USB 2.0
> - I2S
> - I2C
> - SPI
>
> Also a couple of GPIO and PWM pins for controlling various ICs on the
> display adapter board.
>
> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> ---
>  .../imx8mp-tx8p-ml81-moduline-display-106.dtsi     | 535 +++++++++++++++++++++
>  1 file changed, 535 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..a3ab389c9744f5189d5a8a802aa4c4ebb9f7b12b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dtsi
> @@ -0,0 +1,535 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright 2025 GOcontroll B.V.
> + * Author: Maud Spierings <maudspierings@gocontroll.com>
> + */
> +
> +#include "imx8mp-tx8p-ml81.dtsi"
> +
> +/ {
> +	chassis-type = "embedded";
> +	compatible = "gocontroll,moduline-display", "fsl,imx8mp";
> +	hardware =  "Moduline Display V1.06";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		mmc0 = &usdhc3;
> +		mmc1 = &usdhc2;
> +		spi0 = &ecspi2; /* spidev number compatibility */
> +		spi1 = &ecspi1; /* spidev number compatibility */
> +		can0 = &flexcan1;
> +		can1 = &flexcan2;
> +		rtc0 = &rtc_pcf; /* i2c rtc is the main rtc */
> +		rtc1 = &snvs_rtc;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	external-sensor-supply {
> +		compatible = "regulator-output";
> +		vout-supply = <&reg_5v0_sensor>;
> +	};
> +
> +	reg_can1_stby: regulator-can1-stby {
> +		compatible = "regulator-fixed";
> +		regulator-name = "can1-stby";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flexcan1_reg>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	reg_can2_stby: regulator-can2-stby {
> +		compatible = "regulator-fixed";
> +		regulator-name = "can2-stby";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flexcan2_reg>;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio5 9 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	reg_1v8_per: regulator-1v8-per {
> +		compatible = "regulator-fixed";
> +		regulator-name = "1v8-per";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_1v8>;
> +		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		power-supply = <&reg_3v3_per>;
> +	};
> +
> +	reg_3v3_per: regulator-3v3-per {
> +		compatible = "regulator-fixed";
> +		regulator-name = "3v3-per";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +		power-supply = <&reg_6v4>;
> +	};
> +
> +	reg_5v0_sensor: regulator-5v0-sensor {
> +		compatible = "regulator-fixed";
> +		regulator-name = "5v0-supply-external-sensor";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_5v0_sensor>;
> +		gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
> +	reg_5v0: regulator-5v0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "5v0";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +		power-supply = <&reg_6v4>;
> +	};
> +
> +	reg_6v4: regulator-6v4 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "6v4";
> +		regulator-min-microvolt = <6400000>;
> +		regulator-max-microvolt = <6400000>;
> +		regulator-always-on;
> +	};
> +
> +	sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,name = "tas2505-audio";
> +		simple-audio-card,format = "i2s";
> +		simple-audio-card,frame-master = <&cpudai>;
> +		simple-audio-card,bitclock-master = <&cpudai>;
> +		simple-audio-card,widgets =
> +		"Speaker", "Speaker External";
> +		simple-audio-card,routing =
> +		"Speaker", "DAC";

fix indentation.

> +
> +		cpudai: simple-audio-card,cpu {
> +			sound-dai = <&sai6>;
> +		};
> +
> +		simple-audio-card,codec {
> +			sound-dai = <&tas2505>;
> +		};
> +	};
> +
> +	wifi_powerseq: wifi-powerseq {
> +		compatible = "mmc-pwrseq-simple";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_wl_reg>;
> +		post-power-on-delay-ms = <100>;
> +		power-off-delay-us = <500000>;
> +		reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
> +	};
> +};
> +
> +&ecspi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1>;
> +	cs-gpios = <
> +	&gpio2 12 GPIO_ACTIVE_LOW
> +	&gpio1 11 GPIO_ACTIVE_LOW
> +	&gpio1 10 GPIO_ACTIVE_LOW
> +	>;

fix indentation.

> +	status = "okay";
> +
> +	connector@0 {
> +		compatible = "gocontroll,moduline-module-slot";
> +		reg = <0>;
> +		reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
> +		sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> +		vdd-supply = <&reg_3v3_per>;
> +		vddp-supply = <&reg_5v0>;
> +		vddhpp-supply = <&reg_6v4>;
> +		i2c-bus = <&i2c2>;
> +		slot-number = <1>;
> +		spi-max-frequency = <54000000>;
> +

Needn't space line here.

> +	};
> +
> +	connector@1 {
> +		compatible = "gocontroll,moduline-module-slot";
> +		reg = <1>;
> +		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> +		sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
> +		vdd-supply = <&reg_3v3_per>;
> +		vddp-supply = <&reg_5v0>;
> +		vddhpp-supply = <&reg_6v4>;
> +		i2c-bus = <&i2c2>;
> +		slot-number = <2>;
> +		spi-max-frequency = <54000000>;
> +	};
> +
> +	adc@2 {
> +		compatible = "microchip,mcp3004";
> +		reg = <2>;
> +		spi-max-frequency = <2300000>;
> +		vref-supply = <&reg_vdd_3v3>;
> +	};
> +};
> +
> +&flexcan1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan1>;
> +	xceiver-supply = <&reg_can1_stby>;
> +	status = "okay";
> +};
> +
> +&flexcan2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan2>;
> +	xceiver-supply = <&reg_can2_stby>;
> +	status = "okay";
> +};
> +
> +/* I2C2 bus to modules */
> +&i2c2 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	pinctrl-1 = <&pinctrl_i2c2_gpio>;
> +	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +};
> +
> +&i2c4 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c4>;
> +	pinctrl-1 = <&pinctrl_i2c4_gpio>;
> +	sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +
> +	tas2505: tas2505@18 {

Please use common node name.

Frank
> +		compatible = "ti,tas2505";
> +		reg = <0x18>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_tas_reset>;
> +		reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
> +		#sound-dai-cells = <0>;
> +
> +		dv-supply = <&reg_1v8_per>;
> +		iov-supply = <&reg_vdd_3v3>;
> +		av-supply = <&reg_1v8_per>;
> +
> +		clocks = <&clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>;
> +		clock-names = "mclk";
> +		aic32x4-gpio-func= <
> +			0xff
> +			0xff
> +			0xff
> +			0xff
> +			0xff
> +		>;
> +	};
> +
> +	rtc_pcf: rtc@51 {
> +		compatible = "nxp,pcf85063a";
> +		reg = <0x51>;
> +		quartz-load-femtofarads = <7000>;
> +
> +		clock {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32768>;
> +		};
> +	};
> +};
> +
> +/* tas2505 */
> +&sai6 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sai6>;
> +	status = "okay";
> +	assigned-clocks = <&clk IMX8MP_CLK_SAI6>;
> +	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> +	assigned-clock-rates = <12288000>;
> +	fsl,sai-mclk-direction-output;
> +};
> +
> +/* debug/external */
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2>;
> +	uart-has-rtscts;
> +	status = "okay";
> +
> +	/* muRata 1YN/1DX */
> +	bluetooth {
> +		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
> +		max-speed = <921600>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_bt>;
> +		device-wakeup-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
> +		shutdown-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
> +		interrupt-names = "host-wakeup";
> +		vddio-supply = <&reg_3v3_per>;
> +		vbat-supply = <&reg_3v3_per>;
> +	};
> +};
> +
> +&usb3_0 {
> +	status = "okay";
> +};
> +
> +&usb3_phy0 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> +	dr_mode = "peripheral";
> +};
> +
> +&usdhc2 {
> +	max-frequency = <50000000>;
> +	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
> +	assigned-clock-rates = <50000000>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2>;
> +	mmc-pwrseq = <&wifi_powerseq>;
> +	vmmc-supply = <&reg_3v3_per>;
> +
> +	cap-power-off-card;
> +	keep-power-in-suspend;
> +	non-removable;
> +	sd-uhs-sdr25;
> +
> +	status = "okay";
> +
> +	/* muRata 1YN/1DX */
> +	wifi@1 {
> +		compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
> +		reg = <1>;
> +		brcm,board-type = "GOcontroll,moduline";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_wl_int>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +		interrupt-names = "host-wake";
> +	};
> +};
> +
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl_reg_1v8: reg-1v8-grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 /* COM pin 144 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +
> +	pinctrl_reg_5v0_sensor: reg-5v0-sensorgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 /* COM pin 108 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +
> +	pinctrl_tas_reset: tasresetgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 /* COM pin 143 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +
> +	pinctrl_bt: btgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 /* COM pin 27 */
> +			MX8MP_DSE_X1
> +			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 /* COM pin 34 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_HYS_SCHMITT)
> +			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 /* COM pin 28 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +
> +	pinctrl_ecspi1: ecspi1grp {
> +		fsl,pins = <
> +		MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI /* COM pin 46 */
> +		MX8MP_DSE_X4
> +		MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO /* COM pin 47 */
> +		(MX8MP_DSE_X4 | MX8MP_HYS_SCHMITT)
> +		MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK /* COM pin 48 */
> +		MX8MP_DSE_X4
> +		MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 /* COM pin 51 */
> +		MX8MP_DSE_X1
> +		MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 /* COM pin 162 */
> +		MX8MP_DSE_X1
> +		MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 /* COM pin 161 */
> +		MX8MP_DSE_X1
> +		>;
> +	};
> +
> +	pinctrl_flexcan1: flexcan1grp {
> +		fsl,pins = <
> +			 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX /* COM pin 81 */
> +			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX /* COM pin 76 */
> +			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_flexcan1_reg: flexcan1reggrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 /* COM pin 101 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_flexcan2: flexcan2grp {
> +		fsl,pins = <
> +			 MX8MP_IOMUXC_UART3_TXD__CAN2_RX /* COM pin 61 */
> +			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			 MX8MP_IOMUXC_UART3_RXD__CAN2_TX /* COM pin 62 */
> +			 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_flexcan2_reg: flexcan2reggrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 /* COM pin 44 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_i2c2: i2c2grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL /* COM pin 41 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA /* COM pin 40 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_i2c2_gpio: i2c2-gpiogrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 /* COM pin 41 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 /* COM pin 40 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_i2c4: i2c4grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL /* COM pin 70 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA /* COM pin 69 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_i2c4_gpio: i2c4-gpiogrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 /* COM pin 70 */
> +			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 /* COM pin 69 */
> +			(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
> +		>;
> +	};
> +
> +	pinctrl_sai6: sai6grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC /* COM pin 95 */
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +			MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK /* COM pin 105 */
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +			MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 /* COM pin 110 */
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +			MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK /* COM pin 96 */
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +			MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 /* COM pin 106 */
> +			(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX /* COM pin 60 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX /* COM pin 59 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_uart2: uart2grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX /* COM pin 64 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX /* COM pin 63 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS /* COM pin 65 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS /* COM pin 66 */
> +			(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: pinctrlusdhc2grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK /* COM pin 57 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD /* COM pin 56 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 /* COM pin 52 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 /* COM pin 53 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 /* COM pin 54 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 /* COM pin 55 */
> +			(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_wdog: wdoggrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B /* COM pin 153 */
> +			(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT)
> +		>;
> +	};
> +
> +	pinctrl_wl_int: wlintgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 /* COM pin 36 */
> +			(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> +		>;
> +	};
> +
> +	pinctrl_wl_reg: wlreggrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 /* COM pin 15 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +};
>
> --
> 2.49.0
>
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy
  2025-03-27 15:52 ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Maud Spierings via B4 Relay
@ 2025-03-27 16:31   ` Frank Li
  2025-03-28  7:37     ` Maud Spierings | GOcontroll
  0 siblings, 1 reply; 19+ messages in thread
From: Frank Li @ 2025-03-27 16:31 UTC (permalink / raw)
  To: maudspierings
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
	linux-kernel, imx, linux-arm-kernel

On Thu, Mar 27, 2025 at 04:52:42PM +0100, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maudspierings@gocontroll.com>
>
> Add the BOE av101hdt-a10 variant of the Moduline Display, this variant
> comes with a 10.1 1280x720 display with a touchscreen (not working in
> mainline).
>
> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
>
> ---
> Currently the backlight driver is not available, this will be upstreamed
> in a future patch series. It is a Maxim max25014atg.
>
> The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as
> I know is not supported upstream, the driver we currently use for this is
> a mess and I doubt we will be able to get it in an upstreamable state.
> ---
>  ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 +++++++++++++++++++++
>  1 file changed, 100 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..1917e22001a1815a6540f00cf039ff352801cda8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts

why not use dt overlay to handle difference dsplay module.

Frank

> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright 2025 GOcontroll B.V.
> + * Author: Maud Spierings <maudspierings@gocontroll.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi"
> +
> +/ {
> +	model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
> +
> +	panel {
> +		compatible = "boe,av101hdt-a10";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_panel>;
> +		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> +		power-supply = <&reg_3v3_per>;
> +
> +		port {
> +			panel_lvds_in: endpoint {
> +				remote-endpoint = <&ldb_lvds_ch0>;
> +			};
> +		};
> +	};
> +
> +	reg_vbus: regulator-vbus {
> +		compatible = "regulator-fixed";
> +		regulator-name = "usb-c-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		power-supply = <&reg_6v4>;
> +		regulator-always-on;
> +	};
> +};
> +
> +&lcdif2 {
> +	status = "okay";
> +};
> +
> +&usb3_1 {
> +	status = "okay";
> +};
> +
> +&usb3_phy1 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_1 {
> +	dr_mode = "host";
> +
> +	port {
> +		usb1_hs_ep: endpoint {
> +			remote-endpoint = <&high_speed_ep>;
> +		};
> +	};
> +
> +	connector {
> +		compatible = "usb-c-connector";
> +		pd-disable;
> +		data-role = "host";
> +		vbus-supply = <&reg_vbus>;
> +
> +		port {
> +			high_speed_ep: endpoint {
> +				remote-endpoint = <&usb1_hs_ep>;
> +			};
> +		};
> +	};
> +};
> +
> +&lvds_bridge {
> +	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
> +	<&clk IMX8MP_VIDEO_PLL1>;

fix indentation.

> +	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> +	/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */
> +	assigned-clock-rates = <0>, <1054620000>;
> +	status = "okay";
> +
> +	ports {
> +		port@1 {
> +			ldb_lvds_ch0: endpoint {
> +				remote-endpoint = <&panel_lvds_in>;
> +			};
> +		};
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl_panel: panelgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */
> +			MX8MP_DSE_X1
> +			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */
> +			MX8MP_DSE_X1
> +		>;
> +	};
> +};
>
> --
> 2.49.0
>
>


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy
  2025-03-27 16:18   ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy Frank Li
@ 2025-03-28  7:20     ` Maud Spierings | GOcontroll
  2025-03-28 10:43       ` Maud Spierings | GOcontroll
  0 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings | GOcontroll @ 2025-03-28  7:20 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org


From: Frank Li <Frank.li@nxp.com>
Sent: Thursday, March 27, 2025 5:18 PM
 
> On Thu, Mar 27, 2025 at 04:52:40PM +0100, Maud Spierings via B4 Relay wrote:
>> From: Maud Spierings <maudspierings@gocontroll.com>
>>
>> The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has
>> 2 GB or ram and 8 GB of eMMC storage on board.
>>
>> Add it to enable boards based on this Module
>>
>> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
>> ---
>>  .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
>>  1 file changed, 549 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da377319eda8506
>> --- /dev/null
> 
> New dts files, suggest run https://github.com/lznuaa/dt-format to make
> nodes and property ordered.

Ah I didn't know there is a tool for that, never seen it before, will
check it out.

>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
>> @@ -0,0 +1,549 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
>> + * 2025 Maud Spierings <maudspierings@gocontroll.com>
>> + */
>> +
>> +#include "imx8mp.dtsi"
>> +
>> +/ {
>> +     /* PHY regulator */
>> +     regulator-3v3-etn {
>> +             compatible = "regulator-fixed";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_reg_3v3_etn>;
>> +             regulator-name = "3v3-etn";
>> +             regulator-min-microvolt = <3300000>;
>> +             regulator-max-microvolt = <3300000>;
>> +             vin-supply = <&reg_vdd_3v3>;
>> +             gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
>> +             enable-active-high;
>> +             regulator-always-on;
>> +             regulator-boot-on;
>> +     };
>> +};
>> +
>> +&A53_0 {
>> +     cpu-supply = <&reg_vdd_arm>;
>> +};
>> +
>> +&A53_1 {
>> +     cpu-supply = <&reg_vdd_arm>;
>> +};
>> +
>> +&A53_2 {
>> +     cpu-supply = <&reg_vdd_arm>;
>> +};
>> +
>> +&A53_3 {
>> +     cpu-supply = <&reg_vdd_arm>;
>> +};
>> +
>> +
>> +&eqos {
>> +     pinctrl-names = "default", "sleep";
>> +     pinctrl-0 = <&pinctrl_eqos>;
>> +     pinctrl-1 = <&pinctrl_eqos_sleep>;
>> +     assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
>> +                       <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
>> +                       <&clk IMX8MP_CLK_ENET_QOS>;
>> +     assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
>> +                              <&clk IMX8MP_SYS_PLL2_100M>,
>> +                              <&clk IMX8MP_SYS_PLL2_50M>;
>> +     assigned-clock-rates = <0>, <100000000>, <50000000>;
>> +     phy-mode = "rmii";
>> +     phy-handle = <&ethphy0>;
>> +     status = "okay";
>> +
>> +     mdio {
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             compatible = "snps,dwmac-mdio";
> 
> "compatible" should be first property.

whoops, I guess copy paste mistake from the original, will fix.

>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_ethphy_rst_b>;
>> +             reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
>> +             reset-delay-us = <25000>;
>> +
>> +             ethphy0: ethernet-phy@0 {
>> +                     reg = <0>;
>> +                     pinctrl-names = "default";
>> +                     pinctrl-0 = <&pinctrl_ethphy_int_b>;
>> +                     interrupt-parent = <&gpio4>;
>> +                     interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
>> +                     clocks = <&clk IMX8MP_CLK_ENET_QOS>;
>> +                     smsc,disable-energy-detect;
>> +             };
>> +     };
>> +};
>> +
>> +&gpio1 {
>> +     gpio-line-names = "SODIMM_152",
>> +             "SODIMM_42",
>> +             "PMIC_WDOG_B SODIMM_153",
>> +             "PMIC_IRQ_B",
>> +             "SODIMM_154",
>> +             "SODIMM_155",
>> +             "SODIMM_156",
>> +             "SODIMM_157",
>> +             "SODIMM_158",
>> +             "SODIMM_159",
>> +             "SODIMM_161",
>> +             "SODIMM_162",
>> +             "SODIMM_34",
>> +             "SODIMM_36",
>> +             "SODIMM_27",
>> +             "SODIMM_28",
>> +             "ENET_MDC",
>> +             "ENET_MDIO",
>> +             "",
>> +             "ENET_XTAL1/CLKIN",
>> +             "ENET_TXD1",
>> +             "ENET_TXD0",
>> +             "ENET_TXEN",
>> +             "ENET_POWER",
>> +             "ENET_COL/CRS_DV",
>> +             "ENET_RXER",
>> +             "ENET_RXD0",
>> +             "ENET_RXD1",
>> +             "",
>> +             "",
>> +             "",
>> +             "";
>> +};
>> +
>> +&gpio2 {
>> +     gpio-line-names = "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "SODIMM_51",
>> +             "SODIMM_57",
>> +             "SODIMM_56",
>> +             "SODIMM_52",
>> +             "SODIMM_53",
>> +             "SODIMM_54",
>> +             "SODIMM_55",
>> +             "SODIMM_15",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "";
>> +};
>> +
>> +&gpio3 {
>> +     gpio-line-names = "",
>> +             "",
>> +             "EMMC_DS",
>> +             "EMMC_DAT5",
>> +             "EMMC_DAT6",
>> +             "EMMC_DAT7",
>> +             "",
>> +             "",
>> +             "",
>> +             "",
>> +             "EMMC_DAT0",
>> +             "EMMC_DAT1",
>> +             "EMMC_DAT2",
>> +             "EMMC_DAT3",
>> +             "",
>> +             "EMMC_DAT4",
>> +             "",
>> +             "EMMC_CLK",
>> +             "EMMC_CMD",
>> +             "SODIMM_75",
>> +             "SODIMM_145",
>> +             "SODIMM_163",
>> +             "SODIMM_164",
>> +             "SODIMM_165",
>> +             "SODIMM_143",
>> +             "SODIMM_144",
>> +             "SODIMM_72",
>> +             "SODIMM_73",
>> +             "SODIMM_74",
>> +             "SODIMM_93",
>> +             "",
>> +             "";
>> +};
>> +
>> +&gpio4 {
>> +     gpio-line-names = "SODIMM_98",
>> +             "SODIMM_99",
>> +             "SODIMM_100",
>> +             "SODIMM_101",
>> +             "SODIMM_45",
>> +             "SODIMM_43",
>> +             "SODIMM_105",
>> +             "SODIMM_106",
>> +             "SODIMM_107",
>> +             "SODIMM_108",
>> +             "SODIMM_104",
>> +             "SODIMM_103",
>> +             "SODIMM_115",
>> +             "SODIMM_114",
>> +             "SODIMM_113",
>> +             "SODIMM_112",
>> +             "SODIMM_109",
>> +             "SODIMM_110",
>> +             "SODIMM_95",
>> +             "SODIMM_96",
>> +             "SODIMM_97",
>> +             "ENET_nINT",
>> +             "ENET_nRST",
>> +             "SODIMM_84",
>> +             "SODIMM_87",
>> +             "SODIMM_86",
>> +             "SODIMM_85",
>> +             "SODIMM_83",
>> +             "",
>> +             "SODIMM_66",
>> +             "SODIMM_65",
>> +             "";
>> +};
>> +
>> +&gpio5 {
>> +     gpio-line-names = "",
>> +             "",
>> +             "",
>> +             "SODIMM_76",
>> +             "SODIMM_81",
>> +             "SODIMM_146",
>> +             "SODIMM_48",
>> +             "SODIMM_46",
>> +             "SODIMM_47",
>> +             "SODIMM_44",
>> +             "SODIMM_49",
>> +             "",
>> +             "SODIMM_70",
>> +             "SODIMM_69",
>> +             "PMIC_SCL",
>> +             "PMIC_SDA",
>> +             "SODIMM_41",
>> +             "SODIMM_40",
>> +             "SODIMM_148",
>> +             "SODIMM_149",
>> +             "SODIMM_150",
>> +             "SODIMM_151",
>> +             "SODIMM_60",
>> +             "SODIMM_59",
>> +             "SODIMM_64",
>> +             "SODIMM_63",
>> +             "SODIMM_62",
>> +             "SODIMM_61",
>> +             "SODIMM_68",
>> +             "SODIMM_67",
>> +             "",
>> +             "";
>> +};
>> +
>> +&i2c1 {
>> +     pinctrl-names = "default", "gpio";
>> +     pinctrl-0 = <&pinctrl_i2c1>;
>> +     pinctrl-1 = <&pinctrl_i2c1_gpio>;
>> +     clock-frequency = <400000>;
>> +     scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +     sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>> +     status = "okay";
>> +
>> +     pmic@25 {
>> +             reg = <0x25>;
>> +             compatible = "nxp,pca9450c";
> 
> Compatible is first,  reg is second.

whoops, I guess copy paste mistake from the original, will fix.

>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_pmic>;
>> +             interrupt-parent = <&gpio1>;
>> +             interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
>> +
>> +             regulators {
>> +                     reg_vdd_soc: BUCK1 {
>> +                             regulator-name = "vdd-soc";
>> +                             regulator-min-microvolt = <805000>;
>> +                             regulator-max-microvolt = <900000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                             regulator-ramp-delay = <3125>;
>> +                     };
>> +
>> +                     reg_vdd_arm: BUCK2 {
>> +                             regulator-name = "vdd-core";
>> +                             regulator-min-microvolt = <805000>;
>> +                             regulator-max-microvolt = <950000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                             regulator-ramp-delay = <3125>;
>> +                             nxp,dvs-run-voltage = <950000>;
>> +                             nxp,dvs-standby-voltage = <850000>;
>> +                     };
>> +
>> +                     reg_vdd_3v3: BUCK4 {
>> +                             regulator-name = "3v3";
>> +                             regulator-min-microvolt = <3300000>;
>> +                             regulator-max-microvolt = <3300000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     reg_nvcc_nand: BUCK5 {
>> +                             regulator-name = "nvcc-nand";
>> +                             regulator-min-microvolt = <1800000>;
>> +                             regulator-max-microvolt = <1800000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     reg_nvcc_dram: BUCK6 {
>> +                             regulator-name = "nvcc-dram";
>> +                             regulator-min-microvolt = <1100000>;
>> +                             regulator-max-microvolt = <1100000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     reg_snvs_1v8: LDO1 {
>> +                             regulator-name = "snvs-1v8";
>> +                             regulator-min-microvolt = <1800000>;
>> +                             regulator-max-microvolt = <1800000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     ldo2_reg: LDO2 {
>> +                             regulator-name = "LDO2";
>> +                             regulator-min-microvolt = <800000>;
>> +                             regulator-max-microvolt = <1150000>;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     reg_vdda_1v8: LDO3 {
>> +                             regulator-name = "vdda-1v8";
>> +                             regulator-min-microvolt = <1800000>;
>> +                             regulator-max-microvolt = <1800000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +
>> +                     ldo4_reg: LDO4 {
>> +                             regulator-name = "LDO4";
>> +                             regulator-min-microvolt = <800000>;
>> +                             regulator-max-microvolt = <3300000>;
>> +                     };
>> +
>> +                     ldo5_reg: LDO5 {
>> +                             regulator-name = "LDO5";
>> +                             regulator-min-microvolt = <1800000>;
>> +                             regulator-max-microvolt = <3300000>;
>> +                             regulator-boot-on;
>> +                             regulator-always-on;
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&usdhc3 { /* eMMC */
>> +     max-frequency = <200000000>;
>> +     assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
>> +     assigned-clock-rates = <200000000>;
>> +     pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> +     pinctrl-0 = <&pinctrl_usdhc3>;
>> +     pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>> +     pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
>> +     bus-width = <8>;
>> +     vmmc-supply = <&reg_vdd_3v3>;
>> +     vqmmc-supply = <&reg_nvcc_nand>;
>> +     voltage-ranges = <3300 3300>;
>> +     non-removable;
>> +     status = "okay";
>> +};
>> +
>> +&iomuxc {
>> +     pinctrl_eqos: eqosgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK
>> +                     (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)
>> +                     MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
>> +                     (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
>> +                     (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
>> +                     MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
>> +                     MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
>> +             >;
>> +     };
>> +
>> +     pinctrl_eqos_sleep: eqos-sleep-grp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22
>> +                     (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_ethphy_int_b: ethphy-int-bgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21
>> +                     (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)
>> +             >;
>> +     };
>> +
>> +     pinctrl_ethphy_rst_b: ethphy-rst-bgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
>> +                     (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_i2c1: i2c1grp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
>> +                     (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
>> +                     MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
>> +                     (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
>> +             >;
>> +     };
>> +
>> +     pinctrl_i2c1_gpio: i2c1-gpiogrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
>> +                     (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
>> +                     MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
>> +                     (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE | MX8MP_SION)
>> +             >;
>> +     };
>> +
>> +     pinctrl_pmic: pmicgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
>> +                     (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_reg_3v3_etn: reg-3v3-etngrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23
>> +                     (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_usdhc3: usdhc3grp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
>> +                     (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> 
> 
> It is much better than hex value
> 
> The most are the same.  Can you define helper macro to reduce copy long OR
> 
> for example
> 
> #define USDHC_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
> 
> so pinctrl_usdhc3_100mhz
>                 fsl,pins = <... (MX8MP_DSE_X2 | USDHC_DEFAULT);
> 
> usdhc3-200mhzgrp
>                 fsl,pins = <... (MX8MP_DSE_X6 | USDHC_DEFAULT);
> 
> Frank

Sounds like a plan, I guess those helper macros should also go into
imx8mp-pinfunc.h?

I think the I2C one may also be a nice standard one that everyone copies

>> +                     MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
>> +                     (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
>> +                     (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
>> +                     (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +
>> +     pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +                     MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
>> +                     (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>> +             >;
>> +     };
>> +};
>>
>> --
>> 2.49.0
>>
>>

Kind regards,
Maud

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy
  2025-03-27 16:31   ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy Frank Li
@ 2025-03-28  7:37     ` Maud Spierings | GOcontroll
  2025-03-28 15:34       ` Frank Li
  0 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings | GOcontroll @ 2025-03-28  7:37 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org

Sent: Thursday, March 27, 2025 5:31 PM
To: Maud Spierings | GOcontroll <maudspierings@gocontroll.com>
 
> On Thu, Mar 27, 2025 at 04:52:42PM +0100, Maud Spierings via B4 Relay wrote:
>> From: Maud Spierings <maudspierings@gocontroll.com>
>>
>> Add the BOE av101hdt-a10 variant of the Moduline Display, this variant
>> comes with a 10.1 1280x720 display with a touchscreen (not working in
>> mainline).
>>
>> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
>>
>> ---
>> Currently the backlight driver is not available, this will be upstreamed
>> in a future patch series. It is a Maxim max25014atg.
>>
>> The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as
>> I know is not supported upstream, the driver we currently use for this is
>> a mess and I doubt we will be able to get it in an upstreamable state.
>> ---
>>  ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 +++++++++++++++++++++
>>  1 file changed, 100 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..1917e22001a1815a6540f00cf039ff352801cda8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
> 
> why not use dt overlay to handle difference dsplay module.
> 
> Frank

This may just be me not being very familiar with overlays, how they work
and when to use them. I guess the advantage is saving some spaces in not
having the base board dtsi copied in two dtbs on the target right?

I am still quite new to all of this, so any info on when to use what is
greatly appreciated.

>> @@ -0,0 +1,100 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright 2025 GOcontroll B.V.
>> + * Author: Maud Spierings <maudspierings@gocontroll.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi"
>> +
>> +/ {
>> +     model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
>> +
>> +     panel {
>> +             compatible = "boe,av101hdt-a10";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_panel>;
>> +             enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
>> +             reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
>> +             power-supply = <&reg_3v3_per>;
>> +
>> +             port {
>> +                     panel_lvds_in: endpoint {
>> +                             remote-endpoint = <&ldb_lvds_ch0>;
>> +                     };
>> +             };
>> +     };
>> +
>> +     reg_vbus: regulator-vbus {
>> +             compatible = "regulator-fixed";
>> +             regulator-name = "usb-c-vbus";
>> +             regulator-min-microvolt = <5000000>;
>> +             regulator-max-microvolt = <5000000>;
>> +             power-supply = <&reg_6v4>;
>> +             regulator-always-on;
>> +     };
>> +};
>> +
>> +&lcdif2 {
>> +     status = "okay";
>> +};
>> +
>> +&usb3_1 {
>> +     status = "okay";
>> +};
>> +
>> +&usb3_phy1 {
>> +     status = "okay";
>> +};
>> +
>> +&usb_dwc3_1 {
>> +     dr_mode = "host";
>> +
>> +     port {
>> +             usb1_hs_ep: endpoint {
>> +                     remote-endpoint = <&high_speed_ep>;
>> +             };
>> +     };
>> +
>> +     connector {
>> +             compatible = "usb-c-connector";
>> +             pd-disable;
>> +             data-role = "host";
>> +             vbus-supply = <&reg_vbus>;
>> +
>> +             port {
>> +                     high_speed_ep: endpoint {
>> +                             remote-endpoint = <&usb1_hs_ep>;
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&lvds_bridge {
>> +     assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
>> +     <&clk IMX8MP_VIDEO_PLL1>;
> 
> fix indentation.

Just put it on one line as it fits within the 80 columns

>> +     assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
>> +     /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */
>> +     assigned-clock-rates = <0>, <1054620000>;
>> +     status = "okay";
>> +
>> +     ports {
>> +             port@1 {
>> +                     ldb_lvds_ch0: endpoint {
>> +                             remote-endpoint = <&panel_lvds_in>;
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&iomuxc {
>> +     pinctrl_panel: panelgrp {
>> +             fsl,pins = <
>> +                     MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */
>> +                     MX8MP_DSE_X1
>> +                     MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */
>> +                     MX8MP_DSE_X1
>> +             >;
>> +     };
>> +};
>>
>> --
>> 2.49.0
>>
>>

Kind Regards,
Maud

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy
  2025-03-28  7:20     ` Maud Spierings | GOcontroll
@ 2025-03-28 10:43       ` Maud Spierings | GOcontroll
  2025-03-28 15:27         ` Frank Li
  0 siblings, 1 reply; 19+ messages in thread
From: Maud Spierings | GOcontroll @ 2025-03-28 10:43 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org

From: Maud Spierings | GOcontroll <maudspierings@gocontroll.com>
Sent: Friday, March 28, 2025 8:20 AM

> From: Frank Li <Frank.li@nxp.com>
> Sent: Thursday, March 27, 2025 5:18 PM
>  
>> On Thu, Mar 27, 2025 at 04:52:40PM +0100, Maud Spierings via B4 Relay wrote:
>>> From: Maud Spierings <maudspierings@gocontroll.com>
>>>
>>> The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has
>>> 2 GB or ram and 8 GB of eMMC storage on board.
>>>
>>> Add it to enable boards based on this Module
>>>
>>> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
>>> ---
>>>  .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
>>>  1 file changed, 549 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da377319eda8506
>>> --- /dev/null
>>
>> New dts files, suggest run https://github.com/lznuaa/dt-format to make
>> nodes and property ordered.
> 
> Ah I didn't know there is a tool for that, never seen it before, will
> check it out.

I checked it out but I have one question, this tool orders all nodes
alphabetically, which is correct. But from what I've seen all imx
devicetrees have the iomuxc node at the bottom, regardless whether it
should be there alphabetically. Should I still keep the iomuxc node at the
bottom?

Kind regards,
Maud

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy
  2025-03-28 10:43       ` Maud Spierings | GOcontroll
@ 2025-03-28 15:27         ` Frank Li
  0 siblings, 0 replies; 19+ messages in thread
From: Frank Li @ 2025-03-28 15:27 UTC (permalink / raw)
  To: Maud Spierings | GOcontroll
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org

On Fri, Mar 28, 2025 at 10:43:44AM +0000, Maud Spierings | GOcontroll wrote:
> From: Maud Spierings | GOcontroll <maudspierings@gocontroll.com>
> Sent: Friday, March 28, 2025 8:20 AM
>
> > From: Frank Li <Frank.li@nxp.com>
> > Sent: Thursday, March 27, 2025 5:18 PM
> >
> >> On Thu, Mar 27, 2025 at 04:52:40PM +0100, Maud Spierings via B4 Relay wrote:
> >>> From: Maud Spierings <maudspierings@gocontroll.com>
> >>>
> >>> The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has
> >>> 2 GB or ram and 8 GB of eMMC storage on board.
> >>>
> >>> Add it to enable boards based on this Module
> >>>
> >>> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> >>> ---
> >>>  .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++++++
> >>>  1 file changed, 549 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
> >>> new file mode 100644
> >>> index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da377319eda8506
> >>> --- /dev/null
> >>
> >> New dts files, suggest run https://github.com/lznuaa/dt-format to make
> >> nodes and property ordered.
> >
> > Ah I didn't know there is a tool for that, never seen it before, will
> > check it out.
>
> I checked it out but I have one question, this tool orders all nodes
> alphabetically, which is correct. But from what I've seen all imx
> devicetrees have the iomuxc node at the bottom, regardless whether it
> should be there alphabetically. Should I still keep the iomuxc node at the
> bottom?

Old dts iomux is bottom. But I think there should not such requirement now.

Frank

>
> Kind regards,
> Maud


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy
  2025-03-28  7:37     ` Maud Spierings | GOcontroll
@ 2025-03-28 15:34       ` Frank Li
  0 siblings, 0 replies; 19+ messages in thread
From: Frank Li @ 2025-03-28 15:34 UTC (permalink / raw)
  To: Maud Spierings | GOcontroll
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org

On Fri, Mar 28, 2025 at 07:37:34AM +0000, Maud Spierings | GOcontroll wrote:
> Sent: Thursday, March 27, 2025 5:31 PM
> To: Maud Spierings | GOcontroll <maudspierings@gocontroll.com>
>  
> > On Thu, Mar 27, 2025 at 04:52:42PM +0100, Maud Spierings via B4 Relay wrote:
> >> From: Maud Spierings <maudspierings@gocontroll.com>
> >>
> >> Add the BOE av101hdt-a10 variant of the Moduline Display, this variant
> >> comes with a 10.1 1280x720 display with a touchscreen (not working in
> >> mainline).
> >>
> >> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
> >>
> >> ---
> >> Currently the backlight driver is not available, this will be upstreamed
> >> in a future patch series. It is a Maxim max25014atg.
> >>
> >> The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as
> >> I know is not supported upstream, the driver we currently use for this is
> >> a mess and I doubt we will be able to get it in an upstreamable state.
> >> ---
> >>  ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 +++++++++++++++++++++
> >>  1 file changed, 100 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
> >> new file mode 100644
> >> index 0000000000000000000000000000000000000000..1917e22001a1815a6540f00cf039ff352801cda8
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dts
> >
> > why not use dt overlay to handle difference dsplay module.
> >
> > Frank
>
> This may just be me not being very familiar with overlays, how they work
> and when to use them. I guess the advantage is saving some spaces in not
> having the base board dtsi copied in two dtbs on the target right?
>
> I am still quite new to all of this, so any info on when to use what is
> greatly appreciated.

Overlay help change NxM problem to N + M.

for example, if you have one "compatible = "boe,av101hdt-a10";" overlay file
BOE.dtso

there are N' type boards, such as iMX8MP-tx8p, iMX8MP-tx9p, ...

You only apply overlay BOE.dtso to iMX8MP-tx8p.dtb.
		       BOE.dtso to iMX8MP-tx9p
		       ....

So needn't create NxM dtb files.

There are many dtso file under freescale, which you can ref

Frank

>
> >> @@ -0,0 +1,100 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/*
> >> + * Copyright 2025 GOcontroll B.V.
> >> + * Author: Maud Spierings <maudspierings@gocontroll.com>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi"
> >> +
> >> +/ {
> >> +     model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
> >> +
> >> +     panel {
> >> +             compatible = "boe,av101hdt-a10";
> >> +             pinctrl-names = "default";
> >> +             pinctrl-0 = <&pinctrl_panel>;
> >> +             enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> >> +             reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> >> +             power-supply = <&reg_3v3_per>;
> >> +
> >> +             port {
> >> +                     panel_lvds_in: endpoint {
> >> +                             remote-endpoint = <&ldb_lvds_ch0>;
> >> +                     };
> >> +             };
> >> +     };
> >> +
> >> +     reg_vbus: regulator-vbus {
> >> +             compatible = "regulator-fixed";
> >> +             regulator-name = "usb-c-vbus";
> >> +             regulator-min-microvolt = <5000000>;
> >> +             regulator-max-microvolt = <5000000>;
> >> +             power-supply = <&reg_6v4>;
> >> +             regulator-always-on;
> >> +     };
> >> +};
> >> +
> >> +&lcdif2 {
> >> +     status = "okay";
> >> +};
> >> +
> >> +&usb3_1 {
> >> +     status = "okay";
> >> +};
> >> +
> >> +&usb3_phy1 {
> >> +     status = "okay";
> >> +};
> >> +
> >> +&usb_dwc3_1 {
> >> +     dr_mode = "host";
> >> +
> >> +     port {
> >> +             usb1_hs_ep: endpoint {
> >> +                     remote-endpoint = <&high_speed_ep>;
> >> +             };
> >> +     };
> >> +
> >> +     connector {
> >> +             compatible = "usb-c-connector";
> >> +             pd-disable;
> >> +             data-role = "host";
> >> +             vbus-supply = <&reg_vbus>;
> >> +
> >> +             port {
> >> +                     high_speed_ep: endpoint {
> >> +                             remote-endpoint = <&usb1_hs_ep>;
> >> +                     };
> >> +             };
> >> +     };
> >> +};
> >> +
> >> +&lvds_bridge {
> >> +     assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
> >> +     <&clk IMX8MP_VIDEO_PLL1>;
> >
> > fix indentation.
>
> Just put it on one line as it fits within the 80 columns
>
> >> +     assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> >> +     /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */
> >> +     assigned-clock-rates = <0>, <1054620000>;
> >> +     status = "okay";
> >> +
> >> +     ports {
> >> +             port@1 {
> >> +                     ldb_lvds_ch0: endpoint {
> >> +                             remote-endpoint = <&panel_lvds_in>;
> >> +                     };
> >> +             };
> >> +     };
> >> +};
> >> +
> >> +&iomuxc {
> >> +     pinctrl_panel: panelgrp {
> >> +             fsl,pins = <
> >> +                     MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */
> >> +                     MX8MP_DSE_X1
> >> +                     MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */
> >> +                     MX8MP_DSE_X1
> >> +             >;
> >> +     };
> >> +};
> >>
> >> --
> >> 2.49.0
> >>
> >>
>
> Kind Regards,
> Maud


^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2025-03-28 15:54 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-27 15:52 [PATCH v3 0/8] arm64: dts: freescale: Add support for the GOcontroll Moduline Display Maud Spierings via B4 Relay
2025-03-27 15:52 ` [PATCH v3 1/8] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay
2025-03-27 15:52 ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Maud Spierings via B4 Relay
2025-03-27 16:01   ` [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitionsy Frank Li
2025-03-27 15:52 ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM module Maud Spierings via B4 Relay
2025-03-27 16:03   ` [PATCH v3 3/8] MAINTAINERS: add maintainer for the Ka-Ro tx8p-ml81 COM moduley Frank Li
2025-03-27 15:52 ` [PATCH v3 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers Maud Spierings via B4 Relay
2025-03-27 15:52 ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Maud Spierings via B4 Relay
2025-03-27 16:18   ` [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COMy Frank Li
2025-03-28  7:20     ` Maud Spierings | GOcontroll
2025-03-28 10:43       ` Maud Spierings | GOcontroll
2025-03-28 15:27         ` Frank Li
2025-03-27 15:52 ` [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard Maud Spierings via B4 Relay
2025-03-27 16:26   ` [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboardy Frank Li
2025-03-27 15:52 ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Maud Spierings via B4 Relay
2025-03-27 16:31   ` [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Displayy Frank Li
2025-03-28  7:37     ` Maud Spierings | GOcontroll
2025-03-28 15:34       ` Frank Li
2025-03-27 15:52 ` [PATCH v3 8/8] arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display Maud Spierings via B4 Relay

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