From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
will@kernel.org, catalin.marinas@arm.com, joro@8bytes.org,
jean-philippe@linaro.org, iommu@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com,
ryan.roberts@arm.com
Subject: Re: [PATCH 2/2] arm64: cpufeature: Add GCS to cpucap_is_possible()
Date: Thu, 5 Dec 2024 15:40:57 +0000 [thread overview]
Message-ID: <Z1HJiUg60kZP4zPb@J2N7QTR9R3> (raw)
In-Reply-To: <051c017c-a60f-48a7-b09f-07f0f32e48e3@sirena.org.uk>
On Thu, Dec 05, 2024 at 03:04:11PM +0000, Mark Brown wrote:
> On Thu, Dec 05, 2024 at 01:48:10PM +0000, Robin Murphy wrote:
> > static inline bool system_supports_gcs(void)
> > {
> > - return IS_ENABLED(CONFIG_ARM64_GCS) &&
> > - alternative_has_cap_unlikely(ARM64_HAS_GCS);
> > + return alternative_has_cap_unlikely(ARM64_HAS_GCS);
> > }
>
> Ah, this is bitrot since the series was on the list for so long. As
> well as HAFT which Rutland mentioned it looks like _bti_kernel(),
> _irq_prio_masking() and possibly others have the same thing.
In <asm/cpufeature.h>, only system_supports_gcs() and
system_supports_haft() don't use cpucap_is_possible(); all the other
IS_ENABLED() checks are for additional dependent properties, and rely on
the base case being handled in cpucap_is_possible().
In <asm/cpucaps.h> we have:
static __always_inline bool
cpucap_is_possible(const unsigned int cap)
{
...
switch (cap) {
...
case ARM64_HAS_PAN:
return IS_ENABLED(CONFIG_ARM64_PAN);
...
case ARM64_BTI:
return IS_ENABLED(CONFIG_ARM64_BTI);
...
case ARM64_HAS_GIC_PRIO_MASKING:
return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI);
...
}
}
In <asm/cpufeature.h> we have:
// base case
static inline bool system_uses_hw_pan(void)
{
return alternative_has_cap_unlikely(ARM64_HAS_PAN);
}
// additional dependent property
static inline bool system_uses_ttbr0_pan(void)
{
return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
!system_uses_hw_pan();
}
...
// base case
static __always_inline bool system_uses_irq_prio_masking(void)
{
return alternative_has_cap_unlikely(ARM64_HAS_GIC_PRIO_MASKING);
}
// additional dependent property
static inline bool system_has_prio_mask_debugging(void)
{
return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
system_uses_irq_prio_masking();
}
...
// base case
static inline bool system_supports_bti(void)
{
return cpus_have_final_cap(ARM64_BTI);
}
// additional dependent property
static inline bool system_supports_bti_kernel(void)
{
return IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) &&
cpus_have_final_boot_cap(ARM64_BTI);
}
> Ideally we'd have no uses of IS_ENABLED() in these functions so it's a
> bit more obvious.
For the three cases above we can't do that without additional cpucaps,
and I think that'd be worse. I don't see anything we can practically do
other than add comments, and I suspect that's not going to help either.
Mark.
next prev parent reply other threads:[~2024-12-05 15:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-05 13:48 [PATCH 1/2] iommu/arm-smmu-v3: Document SVA interaction with new pagetable features Robin Murphy
2024-12-05 13:48 ` [PATCH 2/2] arm64: cpufeature: Add GCS to cpucap_is_possible() Robin Murphy
2024-12-05 14:23 ` Mark Rutland
2024-12-05 15:04 ` Mark Brown
2024-12-05 15:25 ` Catalin Marinas
2024-12-05 15:55 ` Robin Murphy
2024-12-05 15:40 ` Mark Rutland [this message]
2024-12-05 15:52 ` Mark Brown
2024-12-05 18:14 ` [PATCH 1/2] iommu/arm-smmu-v3: Document SVA interaction with new pagetable features Jean-Philippe Brucker
2024-12-06 12:03 ` Robin Murphy
2024-12-05 18:23 ` (subset) " Catalin Marinas
2024-12-10 0:17 ` Will Deacon
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