From: Nicolin Chen <nicolinc@nvidia.com>
To: Michael Shavit <mshavit@google.com>
Cc: <iommu@lists.linux.dev>, Jason Gunthorpe <jgg@ziepe.ca>,
"Jean-Philippe Brucker" <jean-philippe@linaro.org>,
Joerg Roedel <joro@8bytes.org>,
Lu Baolu <baolu.lu@linux.intel.com>,
Robin Murphy <robin.murphy@arm.com>,
Tomas Krcka <krckatom@amazon.de>, Will Deacon <will@kernel.org>,
Yicong Yang <yangyicong@hisilicon.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Simplify stage selection logic
Date: Thu, 17 Aug 2023 09:21:07 -0700 [thread overview]
Message-ID: <ZN5I88rsUHb693H/@Asurada-Nvidia> (raw)
In-Reply-To: <20230818000321.1.Ibca43cc8d1bcad3ac3deef5726b9745128aea634@changeid>
On Fri, Aug 18, 2023 at 12:03:30AM +0800, Michael Shavit wrote:
> It is invalid for an arm-smmu-v3 to have neither FEAT_TRANS_S1 nor
> FEAT_TRANS_S2 bits set, and this is even checked in the probe.
>
> Only set ARM_SMMU_DOMAIN_S2 if FEAT_TRANS_S1 isn't supported, otherwise set
> ARM_SMMU_DOMAIN_S1. This is clearer as the existing code implies that
> something more sophisticated is going on with the stage selection logic.
>
> Signed-off-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
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next prev parent reply other threads:[~2023-08-17 16:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 16:03 [PATCH] iommu/arm-smmu-v3: Simplify stage selection logic Michael Shavit
2023-08-17 16:21 ` Nicolin Chen [this message]
2023-08-17 16:35 ` Robin Murphy
2023-08-17 17:06 ` Michael Shavit
2023-08-17 18:19 ` Robin Murphy
2023-08-17 18:29 ` Michael Shavit
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