From: Nicolin Chen <nicolinc@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: <robin.murphy@arm.com>, <joro@8bytes.org>, <jgg@nvidia.com>,
<thierry.reding@gmail.com>, <vdumpa@nvidia.com>,
<jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>,
<iommu@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v11 9/9] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF
Date: Fri, 16 Aug 2024 12:42:17 -0700 [thread overview]
Message-ID: <Zr+rme98gB5uqTRX@Asurada-Nvidia> (raw)
In-Reply-To: <Zr+XQfzje2YWIOEo@Asurada-Nvidia>
On Fri, Aug 16, 2024 at 11:15:31AM -0700, Nicolin Chen wrote:
> On Fri, Aug 16, 2024 at 10:34:24AM -0700, Nicolin Chen wrote:
> > On Fri, Aug 16, 2024 at 02:21:03PM +0100, Will Deacon wrote:
> >
> > > > static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,
> > > > - struct arm_smmu_cmdq_batch *cmds)
> > > > + struct arm_smmu_cmdq_batch *cmds,
> > > > + u8 opcode)
> > > > {
> > > > + WARN_ON_ONCE(!opcode);
> > >
> > > This seems like a fairly arbitrary warning. Remove it?
> >
> > OK.
> >
> > > > +
> > > > cmds->num = 0;
> > > > - cmds->cmdq = arm_smmu_get_cmdq(smmu);
> > > > + cmds->cmdq = arm_smmu_get_cmdq(smmu, opcode);
> > >
> > > If we stashed the opcode here, we could actually just enforce that all
> > > commands in the batch are the same type in arm_smmu_cmdq_batch_add().
> > >
> > > Would that work better for you or not?
> >
> > A guested-owned queue is okay to mix different command types:
> > CMDQ_OP_TLBI_NH_ASID
> > CMDQ_OP_TLBI_NH_VA
> > CMDQ_OP_ATC_INV
> >
> > So, limiting a batch to one single opcode isn't ideal. Instead,
> > if we really have to apply an enforcement to every batch_add(),
> > I think the cmdq structure would need a scan function pointer:
> >
> > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > index d0d7c75c030a..1a83ad5ebadc 100644
> > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > @@ -918,2 +918,10 @@ static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,
> >
> > +static bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq,
> > + struct arm_smmu_cmdq_ent *ent)
> > +{
> > + if (!cmdq->supports_cmd)
> > + return true;
> > + return cmdq->supports_cmd(ent);
> > +}
> > +
> > static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,
> > @@ -924,4 +932,5 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,
> >
> > - if (cmds->num == CMDQ_BATCH_ENTRIES - 1 &&
> > - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) {
> > + if ((cmds->num == CMDQ_BATCH_ENTRIES - 1 &&
> > + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) ||
> > + !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) {
> > arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,
>
> We'd need re-init the batch after this too..
>
> Nicolin
>
> > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> > index e131d8170b90..c4872af6232c 100644
> > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> > @@ -616,2 +616,3 @@ struct arm_smmu_cmdq {
> > atomic_t lock;
> > + bool (*supports_cmd)(struct arm_smmu_cmdq_ent *ent);
> > };
> >
> > That being said, the whole thing doesn't seem to have a lot value
> > at this moment, since the SMMU driver doesn't mix commands?
OK. I have added a patch for this. Let's just make things a bit
perfect at once.
Here is a v13 branch that addressed most of your remarks here:
https://github.com/nicolinc/iommufd/commits/vcmdq_in_kernel-v13
Would you please let me know if you are okay with this?
Thank you
Nicolin
next prev parent reply other threads:[~2024-08-16 19:43 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 2:11 [PATCH v11 0/9] Add Tegra241 (Grace) CMDQV Support (part 1/2) Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 1/9] iommu/arm-smmu-v3: Issue a batch of commands to the same cmdq Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 2/9] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Nicolin Chen
2024-08-16 13:53 ` Will Deacon
2024-08-16 17:56 ` Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 3/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Nicolin Chen
2024-08-14 17:26 ` Jason Gunthorpe
2024-08-07 2:11 ` [PATCH v11 4/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_init Nicolin Chen
2024-08-14 17:27 ` Jason Gunthorpe
2024-08-07 2:11 ` [PATCH v11 5/9] iommu/arm-smmu-v3: Make symbols public for CONFIG_TEGRA241_CMDQV Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 6/9] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY Nicolin Chen
2024-08-14 17:31 ` Jason Gunthorpe
2024-08-07 2:11 ` [PATCH v11 7/9] iommu/arm-smmu-v3: Add struct arm_smmu_impl Nicolin Chen
2024-08-14 21:52 ` Jason Gunthorpe
2024-08-15 5:26 ` Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 8/9] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV Nicolin Chen
2024-08-14 21:57 ` Jason Gunthorpe
2024-08-15 5:27 ` Nicolin Chen
2024-08-16 14:19 ` Will Deacon
2024-08-16 17:41 ` Nicolin Chen
2024-08-23 15:38 ` Will Deacon
2024-08-24 0:11 ` Nicolin Chen
2024-08-07 2:11 ` [PATCH v11 9/9] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Nicolin Chen
2024-08-16 13:21 ` Will Deacon
2024-08-16 17:34 ` Nicolin Chen
2024-08-16 18:15 ` Nicolin Chen
2024-08-16 19:42 ` Nicolin Chen [this message]
2024-08-19 17:39 ` Jason Gunthorpe
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