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From: Nicolin Chen <nicolinc@nvidia.com>
To: Yang Shi <yang@os.amperecomputing.com>
Cc: <jgg@ziepe.ca>, <will@kernel.org>, <robin.murphy@arm.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for AmpereOne
Date: Tue, 1 Oct 2024 11:27:54 -0700	[thread overview]
Message-ID: <Zvw/Kghyt9zUkupn@Asurada-Nvidia> (raw)
In-Reply-To: <20241001180346.1485194-1-yang@os.amperecomputing.com>

On Tue, Oct 01, 2024 at 11:03:46AM -0700, Yang Shi wrote:
> Using 64 bit immediate when doing shift can solve the problem.  The
> disssembly after the fix looks like:

[...]

>         unsigned int last_sid_idx =
> -               arm_smmu_strtab_l1_idx((1 << smmu->sid_bits) - 1);
> +               arm_smmu_strtab_l1_idx((1UL << smmu->sid_bits) - 1);

Could a 32-bit build be a corner case where UL is no longer a
"64 bit" stated in the commit message?

Also, there are other places doing "1 << smmu->sid_bits", e.g.
arm_smmu_init_strtab_linear().

Then, can ssid_bits/s1cdmax be a concern similarly?

Thanks
Nicolin


  reply	other threads:[~2024-10-01 18:29 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-01 18:03 [PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for AmpereOne Yang Shi
2024-10-01 18:27 ` Nicolin Chen [this message]
2024-10-01 19:09   ` Yang Shi
2024-10-01 19:18     ` Jason Gunthorpe
2024-10-01 19:38       ` Yang Shi
2024-10-01 19:46         ` Jason Gunthorpe
2024-10-01 20:31           ` Yang Shi
2024-10-01 20:47           ` Yang Shi
2024-10-01 21:02             ` Jason Gunthorpe
2024-10-01 21:32               ` Yang Shi
2024-10-02 16:58             ` James Morse
2024-10-01 19:29     ` Nicolin Chen
2024-10-01 19:48       ` Yang Shi
2024-10-02  9:59         ` Robin Murphy
2024-10-02 15:38           ` Yang Shi
2024-10-02 16:58 ` James Morse
2024-10-02 17:39   ` Yang Shi

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