* [PATCH] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
@ 2026-03-27 6:59 Andy Chung via B4 Relay
2026-05-18 13:09 ` Andrew Jeffery
0 siblings, 1 reply; 2+ messages in thread
From: Andy Chung via B4 Relay @ 2026-03-27 6:59 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Andy Chung, Andy Chung
From: Andy Chung <Andy.Chung@amd.com>
Add the mctp-controller property to enable frontend NIC management
via PLDM over MCTP.
Also add EEPROM device for NIC FRU.
Signed-off-by: Andy Chung <Andy.Chung@amd.com>
---
Add the mctp-controller property to enable frontend NIC management
via PLDM over MCTP.
Also add EEPROM device for NIC FRU.
---
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 67 +++++++++++++++++++++-
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 221af858cb6b..138b081be049 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -584,38 +584,67 @@ eeprom@56 {
// R Bridge Board
&i2c10 {
status = "okay";
+ multi-master;
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
- i2c-mux-idle-disconnect;
i2c10mux0ch0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
};
i2c10mux0ch1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch4: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch5: i2c@5 {
reg = <5>;
@@ -661,38 +690,72 @@ i2c10mux0ch7: i2c@7 {
// L Bridge Board
&i2c11 {
status = "okay";
+ multi-master;
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
- i2c-mux-idle-disconnect;
i2c11mux0ch0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // FE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch4: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch5: i2c@5 {
reg = <5>;
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260327-dts_enable_nic_mctp-e35a5765b176
Best regards,
--
Andy Chung <Andy.Chung@amd.com>
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
2026-03-27 6:59 [PATCH] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Andy Chung via B4 Relay
@ 2026-05-18 13:09 ` Andrew Jeffery
0 siblings, 0 replies; 2+ messages in thread
From: Andrew Jeffery @ 2026-05-18 13:09 UTC (permalink / raw)
To: Andy.Chung, Colin Huang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
Hi Andy,
Sorry for the delay.
On Fri, 2026-03-27 at 14:59 +0800, Andy Chung via B4 Relay wrote:
> From: Andy Chung <Andy.Chung@amd.com>
>
> Add the mctp-controller property to enable frontend NIC management
> via PLDM over MCTP.
> Also add EEPROM device for NIC FRU.
>
> Signed-off-by: Andy Chung <Andy.Chung@amd.com>
> ---
> Add the mctp-controller property to enable frontend NIC management
> via PLDM over MCTP.
> Also add EEPROM device for NIC FRU.
> ---
> .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 67 +++++++++++++++++++++-
> 1 file changed, 65 insertions(+), 2 deletions(-)
Do you mind coordinating with Colin on this one, as he's rearranging
the Anacapa devicetrees.
Cheers,
Andrew
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> index 221af858cb6b..138b081be049 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> @@ -584,38 +584,67 @@ eeprom@56 {
> // R Bridge Board
> &i2c10 {
> status = "okay";
> + multi-master;
> + mctp@10 {
> + compatible = "mctp-i2c-controller";
> + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
> + };
>
> i2c-mux@71 {
> compatible = "nxp,pca9548";
> reg = <0x71>;
> #address-cells = <1>;
> #size-cells = <0>;
> - i2c-mux-idle-disconnect;
>
> i2c10mux0ch0: i2c@0 {
> reg = <0>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> };
> i2c10mux0ch1: i2c@1 {
> reg = <1>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c10mux0ch2: i2c@2 {
> reg = <2>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c10mux0ch3: i2c@3 {
> reg = <3>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c10mux0ch4: i2c@4 {
> reg = <4>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c10mux0ch5: i2c@5 {
> reg = <5>;
> @@ -661,38 +690,72 @@ i2c10mux0ch7: i2c@7 {
> // L Bridge Board
> &i2c11 {
> status = "okay";
> + multi-master;
> + mctp@10 {
> + compatible = "mctp-i2c-controller";
> + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
> + };
>
> i2c-mux@71 {
> compatible = "nxp,pca9548";
> reg = <0x71>;
> #address-cells = <1>;
> #size-cells = <0>;
> - i2c-mux-idle-disconnect;
>
> i2c11mux0ch0: i2c@0 {
> reg = <0>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // FE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c11mux0ch1: i2c@1 {
> reg = <1>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c11mux0ch2: i2c@2 {
> reg = <2>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c11mux0ch3: i2c@3 {
> reg = <3>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c11mux0ch4: i2c@4 {
> reg = <4>;
> #address-cells = <1>;
> #size-cells = <0>;
> + mctp-controller;
> + // BE NIC FRU
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> };
> i2c11mux0ch5: i2c@5 {
> reg = <5>;
>
> ---
> base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
> change-id: 20260327-dts_enable_nic_mctp-e35a5765b176
>
> Best regards,
> --
> Andy Chung <Andy.Chung@amd.com>
>
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