[PATCH v2 0/2] pci: clean up cpu_addr_fixup() for visconti

[PATCH v2 0/2] pci: clean up cpu_addr_fixup() for visconti

[Nobuhiro Iwamatsu]

Since
7db02f725df44 PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset

dwc common code have handled address translate by bus fabric.

1. Correct dts
2. remove cpu_addr_fixup()

dts change need be merge firstly.

Changes from v1:
  Update commit message.
  Fix range.
  Set true to use_parent_dt_ranges.
  move pcie under the dedicated sub-bus.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Frank Li (2):
  arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware
    behavior
  PCI: dwc: visconti: Remove cpu_addr_fix() after DTS fix ranges

 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi  | 75 +++++++++++++---------
 drivers/pci/controller/dwc/pcie-visconti.c | 15 +----
 2 files changed, 47 insertions(+), 43 deletions(-)

-- 
2.49.0

[PATCH v2 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior

[Nobuhiro Iwamatsu]

From: Frank Li <Frank.Li@nxp.com>

tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the PCIe
controller. Since only PCIe controller needs to convert the address range
0x40000000 - 0x80000000, add a bus definition, describe the ranges in it,
and move the PCIe definition.

Prepare for the removal of the driver’s cpu_addr_fixup().

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Suggested-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
v2:
  Update commit message.
  Fix range.
  Set true to use_parent_dt_ranges in pcie-visconti.c.
  move pcie under the dedicated sub-bus.

 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi  | 75 +++++++++++++---------
 drivers/pci/controller/dwc/pcie-visconti.c |  2 +
 2 files changed, 47 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 39806f0ae5133..b754965a76ca6 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -478,37 +478,52 @@ pwm: pwm@241c0000 {
 			status = "disabled";
 		};
 
-		pcie: pcie@28400000 {
-			compatible = "toshiba,visconti-pcie";
-			reg = <0x0 0x28400000 0x0 0x00400000>,
-			      <0x0 0x70000000 0x0 0x10000000>,
-			      <0x0 0x28050000 0x0 0x00010000>,
-			      <0x0 0x24200000 0x0 0x00002000>,
-			      <0x0 0x24162000 0x0 0x00001000>;
-			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
-			device_type = "pci";
-			bus-range = <0x00 0xff>;
-			num-lanes = <2>;
-			num-viewport = <8>;
-
-			#address-cells = <3>;
+		pcie_bus: bus@24000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
 			#size-cells = <2>;
-			#interrupt-cells = <1>;
-			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
-				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi", "intr";
-			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map =
-				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
-			max-link-speed = <2>;
-			clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
-			clock-names = "ref", "core", "aux";
-			status = "disabled";
+			ranges = /* register 1:1 map */
+				 <0x0 0x24000000 0x0 0x24000000 0x0 0x0C000000>,
+				 /*
+				  * bus fabric mask address bit 30 and 31 to 0
+				  * before send to PCIe controller.
+				  *
+				  * PCIe map address 0 to cpu's 0x40000000
+				  */
+				 <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
+
+			pcie: pcie@28400000 {
+				compatible = "toshiba,visconti-pcie";
+				reg = <0x0 0x28400000 0x0 0x00400000>,
+				      <0x0 0x30000000 0x0 0x10000000>,
+				      <0x0 0x28050000 0x0 0x00010000>,
+				      <0x0 0x24200000 0x0 0x00002000>,
+				      <0x0 0x24162000 0x0 0x00001000>;
+				reg-names = "dbi", "config", "ulreg", "smu", "mpu";
+				device_type = "pci";
+				bus-range = <0x00 0xff>;
+				num-lanes = <2>;
+				num-viewport = <8>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x81000000 0 0x00000000 0 0x00000000 0 0x00010000
+					  0x82000000 0 0x10000000 0 0x10000000 0 0x20000000>;
+				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "msi", "intr";
+				interrupt-map-mask = <0 0 0 7>;
+				interrupt-map =
+					<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+				max-link-speed = <2>;
+				clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
+				clock-names = "ref", "core", "aux";
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
index cdeac6177143c..2a724ab587f78 100644
--- a/drivers/pci/controller/dwc/pcie-visconti.c
+++ b/drivers/pci/controller/dwc/pcie-visconti.c
@@ -310,6 +310,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, pcie);
 
+	pci->use_parent_dt_ranges = true;
+
 	return visconti_add_pcie_port(pcie, pdev);
 }
 
-- 
2.49.0

Re: [PATCH v2 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior

[Frank Li]

On Tue, Aug 05, 2025 at 10:47:00AM +0900, Nobuhiro Iwamatsu wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the PCIe
> controller. Since only PCIe controller needs to convert the address range
> 0x40000000 - 0x80000000, add a bus definition, describe the ranges in it,
> and move the PCIe definition.
>
> Prepare for the removal of the driver’s cpu_addr_fixup().
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Suggested-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> ---
> v2:
>   Update commit message.
>   Fix range.
>   Set true to use_parent_dt_ranges in pcie-visconti.c.
>   move pcie under the dedicated sub-bus.
>
>  arch/arm64/boot/dts/toshiba/tmpv7708.dtsi  | 75 +++++++++++++---------
>  drivers/pci/controller/dwc/pcie-visconti.c |  2 +
>  2 files changed, 47 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> index 39806f0ae5133..b754965a76ca6 100644
> --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> @@ -478,37 +478,52 @@ pwm: pwm@241c0000 {
>  			status = "disabled";
>  		};
>
> -		pcie: pcie@28400000 {
> -			compatible = "toshiba,visconti-pcie";
> -			reg = <0x0 0x28400000 0x0 0x00400000>,
> -			      <0x0 0x70000000 0x0 0x10000000>,
> -			      <0x0 0x28050000 0x0 0x00010000>,
> -			      <0x0 0x24200000 0x0 0x00002000>,
> -			      <0x0 0x24162000 0x0 0x00001000>;
> -			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> -			device_type = "pci";
> -			bus-range = <0x00 0xff>;
> -			num-lanes = <2>;
> -			num-viewport = <8>;
> -
> -			#address-cells = <3>;
> +		pcie_bus: bus@24000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
>  			#size-cells = <2>;
> -			#interrupt-cells = <1>;
> -			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
> -				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
> -			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "msi", "intr";
> -			interrupt-map-mask = <0 0 0 7>;
> -			interrupt-map =
> -				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> -			max-link-speed = <2>;
> -			clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> -			clock-names = "ref", "core", "aux";
> -			status = "disabled";
> +			ranges = /* register 1:1 map */
> +				 <0x0 0x24000000 0x0 0x24000000 0x0 0x0C000000>,
> +				 /*
> +				  * bus fabric mask address bit 30 and 31 to 0
> +				  * before send to PCIe controller.
> +				  *
> +				  * PCIe map address 0 to cpu's 0x40000000
> +				  */
> +				 <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
> +
> +			pcie: pcie@28400000 {
> +				compatible = "toshiba,visconti-pcie";
> +				reg = <0x0 0x28400000 0x0 0x00400000>,
> +				      <0x0 0x30000000 0x0 0x10000000>,
> +				      <0x0 0x28050000 0x0 0x00010000>,
> +				      <0x0 0x24200000 0x0 0x00002000>,
> +				      <0x0 0x24162000 0x0 0x00001000>;
> +				reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> +				device_type = "pci";
> +				bus-range = <0x00 0xff>;
> +				num-lanes = <2>;
> +				num-viewport = <8>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x81000000 0 0x00000000 0 0x00000000 0 0x00010000
> +					  0x82000000 0 0x10000000 0 0x10000000 0 0x20000000>;
> +				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "msi", "intr";
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map =
> +					<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +				max-link-speed = <2>;
> +				clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> +				clock-names = "ref", "core", "aux";
> +				status = "disabled";
> +			};
>  		};
>  	};
>  };
> diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> index cdeac6177143c..2a724ab587f78 100644
> --- a/drivers/pci/controller/dwc/pcie-visconti.c
> +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> @@ -310,6 +310,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
>
>  	platform_set_drvdata(pdev, pcie);
>
> +	pci->use_parent_dt_ranges = true;
> +

This change belong to PATCH 2. It still works with old driver after add
pci-bus in dts, just a warning will print.

Frank

>  	return visconti_add_pcie_port(pcie, pdev);
>  }
>
> --
> 2.49.0
>
>

RE: [PATCH v2 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior

[nobuhiro.iwamatsu.x90]

> -----Original Message-----
> From: Frank Li <Frank.li@nxp.com>
> Sent: Wednesday, August 6, 2025 1:45 AM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> bhelgaas@google.com; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-pci@vger.kernel.org; ishikawa yuji(石川 悠司 □ＡＩＤＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>
> Subject: Re: [PATCH v2 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges
> to reflect hardware behavior
> 
> On Tue, Aug 05, 2025 at 10:47:00AM +0900, Nobuhiro Iwamatsu wrote:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the
> > PCIe controller. Since only PCIe controller needs to convert the
> > address range
> > 0x40000000 - 0x80000000, add a bus definition, describe the ranges in
> > it, and move the PCIe definition.
> >
> > Prepare for the removal of the driver’s cpu_addr_fixup().
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > Suggested-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> > ---
> > v2:
> >   Update commit message.
> >   Fix range.
> >   Set true to use_parent_dt_ranges in pcie-visconti.c.
> >   move pcie under the dedicated sub-bus.
> >
> >  arch/arm64/boot/dts/toshiba/tmpv7708.dtsi  | 75
> > +++++++++++++---------  drivers/pci/controller/dwc/pcie-visconti.c
> |
> > 2 +
> >  2 files changed, 47 insertions(+), 30 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > index 39806f0ae5133..b754965a76ca6 100644
> > --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > @@ -478,37 +478,52 @@ pwm: pwm@241c0000 {
> >  			status = "disabled";
> >  		};
> >
> > -		pcie: pcie@28400000 {
> > -			compatible = "toshiba,visconti-pcie";
> > -			reg = <0x0 0x28400000 0x0 0x00400000>,
> > -			      <0x0 0x70000000 0x0 0x10000000>,
> > -			      <0x0 0x28050000 0x0 0x00010000>,
> > -			      <0x0 0x24200000 0x0 0x00002000>,
> > -			      <0x0 0x24162000 0x0 0x00001000>;
> > -			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> > -			device_type = "pci";
> > -			bus-range = <0x00 0xff>;
> > -			num-lanes = <2>;
> > -			num-viewport = <8>;
> > -
> > -			#address-cells = <3>;
> > +		pcie_bus: bus@24000000 {
> > +			compatible = "simple-bus";
> > +			#address-cells = <2>;
> >  			#size-cells = <2>;
> > -			#interrupt-cells = <1>;
> > -			ranges = <0x81000000 0 0x40000000 0 0x40000000 0
> 0x00010000
> > -				  0x82000000 0 0x50000000 0 0x50000000 0
> 0x20000000>;
> > -			interrupts = <GIC_SPI 211
> IRQ_TYPE_LEVEL_HIGH>,
> > -				     <GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH>;
> > -			interrupt-names = "msi", "intr";
> > -			interrupt-map-mask = <0 0 0 7>;
> > -			interrupt-map =
> > -				<0 0 0 1 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > -				 0 0 0 2 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > -				 0 0 0 3 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > -				 0 0 0 4 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH>;
> > -			max-link-speed = <2>;
> > -			clocks = <&extclk100mhz>, <&pismu
> TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> > -			clock-names = "ref", "core", "aux";
> > -			status = "disabled";
> > +			ranges = /* register 1:1 map */
> > +				 <0x0 0x24000000 0x0 0x24000000 0x0
> 0x0C000000>,
> > +				 /*
> > +				  * bus fabric mask address bit 30 and 31 to 0
> > +				  * before send to PCIe controller.
> > +				  *
> > +				  * PCIe map address 0 to cpu's 0x40000000
> > +				  */
> > +				 <0x0 0x00000000 0x0 0x40000000 0x0
> 0x40000000>;
> > +
> > +			pcie: pcie@28400000 {
> > +				compatible = "toshiba,visconti-pcie";
> > +				reg = <0x0 0x28400000 0x0 0x00400000>,
> > +				      <0x0 0x30000000 0x0 0x10000000>,
> > +				      <0x0 0x28050000 0x0 0x00010000>,
> > +				      <0x0 0x24200000 0x0 0x00002000>,
> > +				      <0x0 0x24162000 0x0 0x00001000>;
> > +				reg-names = "dbi", "config", "ulreg", "smu",
> "mpu";
> > +				device_type = "pci";
> > +				bus-range = <0x00 0xff>;
> > +				num-lanes = <2>;
> > +				num-viewport = <8>;
> > +
> > +				#address-cells = <3>;
> > +				#size-cells = <2>;
> > +				#interrupt-cells = <1>;
> > +				ranges = <0x81000000 0 0x00000000 0
> 0x00000000 0 0x00010000
> > +					  0x82000000 0 0x10000000 0
> 0x10000000 0 0x20000000>;
> > +				interrupts = <GIC_SPI 211
> IRQ_TYPE_LEVEL_HIGH>,
> > +					     <GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-names = "msi", "intr";
> > +				interrupt-map-mask = <0 0 0 7>;
> > +				interrupt-map =
> > +					<0 0 0 1 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 2 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 3 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH
> > +					 0 0 0 4 &gic GIC_SPI 215
> IRQ_TYPE_LEVEL_HIGH>;
> > +				max-link-speed = <2>;
> > +				clocks = <&extclk100mhz>, <&pismu
> TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> > +				clock-names = "ref", "core", "aux";
> > +				status = "disabled";
> > +			};
> >  		};
> >  	};
> >  };
> > diff --git a/drivers/pci/controller/dwc/pcie-visconti.c
> > b/drivers/pci/controller/dwc/pcie-visconti.c
> > index cdeac6177143c..2a724ab587f78 100644
> > --- a/drivers/pci/controller/dwc/pcie-visconti.c
> > +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> > @@ -310,6 +310,8 @@ static int visconti_pcie_probe(struct
> > platform_device *pdev)
> >
> >  	platform_set_drvdata(pdev, pcie);
> >
> > +	pci->use_parent_dt_ranges = true;
> > +
> 
> This change belong to PATCH 2. It still works with old driver after add pci-bus
> in dts, just a warning will print.

Thanks for your review.
I see. I will fix and resed.

> 
> Frank

Best regards,
  Nobuhiro

[PATCH v2 2/2] PCI: dwc: visconti: Remove cpu_addr_fix() after DTS fix ranges

[Nobuhiro Iwamatsu]

From: Frank Li <Frank.Li@nxp.com>

Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges
property has been corrected in the DTS, and the DesignWare common code now
handles address translation properly without requiring this workaround.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
v2:
  No Update.

 drivers/pci/controller/dwc/pcie-visconti.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
index 2a724ab587f78..d8765e57147af 100644
--- a/drivers/pci/controller/dwc/pcie-visconti.c
+++ b/drivers/pci/controller/dwc/pcie-visconti.c
@@ -171,20 +171,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
 	visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
 }
 
-/*
- * In this SoC specification, the CPU bus outputs the offset value from
- * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
- * bus address. This 0x40000000 is also based on io_base from DT.
- */
-static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
-{
-	struct dw_pcie_rp *pp = &pci->pp;
-
-	return cpu_addr & ~pp->io_base;
-}
-
 static const struct dw_pcie_ops dw_pcie_ops = {
-	.cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
 	.link_up = visconti_pcie_link_up,
 	.start_link = visconti_pcie_start_link,
 	.stop_link = visconti_pcie_stop_link,
-- 
2.49.0