[PATCH 0/7] ARM: dts: lpc32xx: a number of dt binding clean-ups

[PATCH 0/7] ARM: dts: lpc32xx: a number of dt binding clean-ups

[Vladimir Zapolskiy]

The short series contains a number of trivial clean-ups in a shared
lpc32xx.dtsi file utilized by all NXP LPC32xx powered boards.

Vladimir Zapolskiy (7):
  dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
  ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
  ARM: dts: lpc32xx: Correct motor PWM device tree node name
  ARM: dts: lpc32xx: Correct SD/MMC controller device node name
  ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
  ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
  ARM: dts: lpc32xx: Correct PL080 DMA controller device node name

 .../devicetree/bindings/arm/nxp/lpc32xx.yaml          |  2 +-
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi                | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

-- 
2.49.0

[PATCH 1/7] dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms

[Vladimir Zapolskiy]

Make a formal change to reflect the actual NXP LPC32xx maintainership
for the last years.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Roland Stigge <stigge@antcom.de>
---
 Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
index f1bd6f50e726..6b7f5e6f99cf 100644
--- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
+++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: NXP LPC32xx Platforms
 
 maintainers:
-  - Roland Stigge <stigge@antcom.de>
+  - Vladimir Zapolskiy <vz@mleia.com>
 
 properties:
   compatible:
-- 
2.49.0

[PATCH 2/7] ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells

[Vladimir Zapolskiy]

Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt
to yaml format") both types of PWM controlles on NXP LPC32xx SoC
fairly gained 3 cells, reflect it in the platform dtsi file.

The change removes a dt binding checker warning:

    mpwm@400e8000: #pwm-cells:0:0: 3 was expected

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index 6cf405e9b082..916ab38f0a4c 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -301,8 +301,8 @@ i2c2: i2c@400a8000 {
 			mpwm: mpwm@400e8000 {
 				compatible = "nxp,lpc3220-motor-pwm";
 				reg = <0x400e8000 0x78>;
+				#pwm-cells = <3>;
 				status = "disabled";
-				#pwm-cells = <2>;
 			};
 		};
 
-- 
2.49.0

[PATCH 3/7] ARM: dts: lpc32xx: Correct motor PWM device tree node name

[Vladimir Zapolskiy]

Change once a customly selected 'mpwm' node name in favour of
the expected 'pwm' one.

The change eliminates a reported warning:

    mpwm@400e8000: $nodename:0: 'mpwm@400e8000' does not match '^pwm(@.*|-([0-9]|[1-9][0-9]+))?$'

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index 916ab38f0a4c..761432673c39 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -298,7 +298,7 @@ i2c2: i2c@400a8000 {
 				clocks = <&clk LPC32XX_CLK_I2C2>;
 			};
 
-			mpwm: mpwm@400e8000 {
+			mpwm: pwm@400e8000 {
 				compatible = "nxp,lpc3220-motor-pwm";
 				reg = <0x400e8000 0x78>;
 				#pwm-cells = <3>;
-- 
2.49.0

[PATCH 4/7] ARM: dts: lpc32xx: Correct SD/MMC controller device node name

[Vladimir Zapolskiy]

Change the PL180 SD/MMC controller device node name to the expected
'mmc' one.

The change removes a reported warning:

    sd@20098000: $nodename:0: 'sd@20098000' does not match '^mmc(@.*)?$'

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index 761432673c39..c8b9d70e9362 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -224,7 +224,7 @@ i2s0: i2s@20094000 {
 				status = "disabled";
 			};
 
-			sd: sd@20098000 {
+			sd: mmc@20098000 {
 				compatible = "arm,pl18x", "arm,primecell";
 				reg = <0x20098000 0x1000>;
 				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.49.0

[PATCH 5/7] ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP

[Vladimir Zapolskiy]

The SD/MMC controller on NXP LPC32xx SoC is ARM PrimeCell PL180, it is
reported by the driver:

    mmci-pl18x 20098000.sd: mmc0: PL180 manf 41 rev0 at 0x20098000 irq 36,37 (pio)

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index c8b9d70e9362..522d616a9205 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -225,7 +225,7 @@ i2s0: i2s@20094000 {
 			};
 
 			sd: mmc@20098000 {
-				compatible = "arm,pl18x", "arm,primecell";
+				compatible = "arm,pl180", "arm,primecell";
 				reg = <0x20098000 0x1000>;
 				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
 					     <13 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.49.0

[PATCH 6/7] ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller

[Vladimir Zapolskiy]

For DMA controllers it is required to specify a number of the cells for
users.

The change eliminates the next build time reported warning:

    dma@31000000: '#dma-cells' is a required property

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index 522d616a9205..a38f3c6dbe47 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -83,6 +83,7 @@ dma: dma@31000000 {
 			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk LPC32XX_CLK_DMA>;
 			clock-names = "apb_pclk";
+			#dma-cells = <2>;
 		};
 
 		usb {
-- 
2.49.0

[PATCH 7/7] ARM: dts: lpc32xx: Correct PL080 DMA controller device node name

[Vladimir Zapolskiy]

Rename PL080 DMA controller device node name to the expected one.

The issue was reported by a dt binding checker:

    dma@31000000: $nodename:0: 'dma@31000000' does not match '^dma-controller(@.*)?$'

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
 arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index a38f3c6dbe47..2236901a0031 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -77,7 +77,7 @@ mlc: flash@200a8000 {
 			status = "disabled";
 		};
 
-		dma: dma@31000000 {
+		dma: dma-controller@31000000 {
 			compatible = "arm,pl080", "arm,primecell";
 			reg = <0x31000000 0x1000>;
 			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.49.0

Re: [PATCH 0/7] ARM: dts: lpc32xx: a number of dt binding clean-ups

[Frank Li]

On Thu, Sep 04, 2025 at 09:46:40PM +0300, Vladimir Zapolskiy wrote:
> The short series contains a number of trivial clean-ups in a shared
> lpc32xx.dtsi file utilized by all NXP LPC32xx powered boards.
>
> Vladimir Zapolskiy (7):
>   dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
>   ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
>   ARM: dts: lpc32xx: Correct motor PWM device tree node name
>   ARM: dts: lpc32xx: Correct SD/MMC controller device node name
>   ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
>   ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
>   ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
>
>  .../devicetree/bindings/arm/nxp/lpc32xx.yaml          |  2 +-
>  arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi                | 11 ++++++-----
>  2 files changed, 7 insertions(+), 6 deletions(-)

For the whole serial.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> --
> 2.49.0
>

Re: [PATCH 1/7] dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms

[Rob Herring (Arm)]

On Thu, 04 Sep 2025 21:46:41 +0300, Vladimir Zapolskiy wrote:
> Make a formal change to reflect the actual NXP LPC32xx maintainership
> for the last years.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Roland Stigge <stigge@antcom.de>
> ---
>  Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/7] ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells

[Uwe Kleine-König]

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Hello,

On Thu, Sep 04, 2025 at 09:46:42PM +0300, Vladimir Zapolskiy wrote:
> Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt
> to yaml format") both types of PWM controlles on NXP LPC32xx SoC
> fairly gained 3 cells, reflect it in the platform dtsi file.
> 
> The change removes a dt binding checker warning:
> 
>     mpwm@400e8000: #pwm-cells:0:0: 3 was expected
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Thanks
Uwe

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