From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>,
chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
bhelgaas@google.com, jingoohan1@gmail.com,
kwilczynski@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
cassel@kernel.org
Subject: Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller
Date: Tue, 7 Oct 2025 17:41:55 +0200 [thread overview]
Message-ID: <aOU0w5Brp6uxjZDr@lpieralisi> (raw)
In-Reply-To: <iom65w7amxqf7miopujxeulyiglhkyjszjc3nd4ivknj5npcz2@bvxej6ymkecd>
On Mon, Sep 22, 2025 at 11:51:07AM +0530, Manivannan Sadhasivam wrote:
[...]
> > + /*
> > + * non-prefetchable memory, with best case size and
> > + * alignment
> > + */
> > + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>;
>
> s/0x82000000/0x02000000
>
> And the PCI address really starts from 0x00000000? I don't think so.
Isn't the DWC ATU programmed to make sure that the PCI memory window DT
provides _is_ the PCI "bus" memory base address ?
It is a question, I don't know the DWC inner details fully.
I don't get what you mean by "I don't think so". Either the host controller
AXI<->PCI translation is programmable, then the PCI base address is what
we decide it is or it isn't.
Thanks,
Lorenzo
next prev parent reply other threads:[~2025-10-07 15:42 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 15:58 [PATCH 0/4 v2] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-09-19 15:58 ` [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-09-19 16:39 ` Frank Li
2025-09-23 14:49 ` Vincent Guittot
2025-09-23 16:28 ` Frank Li
2025-09-22 6:21 ` Manivannan Sadhasivam
2025-09-23 17:40 ` Vincent Guittot
2025-10-07 15:41 ` Lorenzo Pieralisi [this message]
2025-10-07 22:28 ` Manivannan Sadhasivam
2025-10-08 8:26 ` Arnd Bergmann
2025-10-08 8:35 ` Arnd Bergmann
2025-10-08 15:19 ` Manivannan Sadhasivam
2025-10-08 17:56 ` Arnd Bergmann
2025-10-09 18:47 ` Manivannan Sadhasivam
2025-10-09 21:16 ` Arnd Bergmann
2025-10-17 15:12 ` Manivannan Sadhasivam
2025-10-08 15:14 ` Manivannan Sadhasivam
2025-09-19 15:58 ` [PATCH 2/3 v2] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-09-19 17:03 ` [External] : " ALOK TIWARI
2025-09-19 18:37 ` Frank Li
2025-09-25 17:09 ` Vincent Guittot
2025-09-22 4:07 ` kernel test robot
2025-09-22 7:56 ` Manivannan Sadhasivam
2025-09-25 16:52 ` Vincent Guittot
2025-09-29 13:57 ` Manivannan Sadhasivam
2025-09-29 16:23 ` Vincent Guittot
2025-09-29 16:32 ` Manivannan Sadhasivam
2025-09-30 16:11 ` Vincent Guittot
2025-09-22 14:52 ` Rob Herring
2025-09-25 16:56 ` Vincent Guittot
2025-09-25 19:15 ` Bjorn Helgaas
2025-09-26 14:18 ` Rob Herring
2025-09-19 15:58 ` [PATCH 3/3 v2] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-09-19 16:58 ` Frank Li
2025-09-25 17:16 ` Vincent Guittot
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