Re: [PATCH rc v4 1/4] iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence

[Nicolin Chen <nicolinc@nvidia.com>]

Hi Mostafa,

On Thu, Dec 18, 2025 at 04:40:01PM +0000, Mostafa Saleh wrote:
> On Tue, Dec 16, 2025 at 08:25:59PM -0800, Nicolin Chen wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > 
> > C_BAD_STE was observed when updating nested STE from an S1-bypass mode to
> > an S1DSS-bypass mode. As both modes enabled S2, the used bit is slightly
> > different than the normal S1-bypass and S1DSS-bypass modes. As a result,
> > fields like MEV and EATS in S2's used list marked the word1 as a critical
> > word that requested a STE.V=0. This breaks a hitless update.
> > 
> > However, both MEV and EATS aren't critical in terms of STE update. One
> > controls the merge of the events and the other controls the ATS that is
> > managed by the driver at the same time via pci_enable_ats().
> > 
> > Add an arm_smmu_get_ste_update_safe() to allow STE update algorithm to
> > relax those fields, avoiding the STE update breakages.
> > 
> > After this change, entry_set has no caller checking its return value, so
> > change it to void.
> > 
> > Note that this change is required by both MEV and EATS fields, which were
> > introduced in different kernel versions. So add get_update_safe() first.
> > MEV and EATS will be added to arm_smmu_get_ste_update_safe() separately.
> > 
> > Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> > Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
> > Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
 
> Reviewed-by: Mostafa Saleh <smostafa@google.com>

I failed to add the two review tags of yours into the v5..

Would you mind replying with your tags once again to v5?

Sorry for the inconvenience!

Nicolin