* [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1
@ 2026-02-26 10:11 Anshuman Khandual
2026-02-26 11:52 ` Mark Rutland
0 siblings, 1 reply; 2+ messages in thread
From: Anshuman Khandual @ 2026-02-26 10:11 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Catalin Marinas, Will Deacon, Ryan Roberts,
Mark Rutland, linux-kernel
A 52 bits physical address gets stored in TTBR_BADDR_MASK_52 in a folded
manner. Shifting PA[51:0] right ward by '46' bits, aligns PA[51:48] into
TTBRx_EL1[5:2] which gets ORed for the final TTBRx_EL1 encoding.
Define TTBR_BADDR_HIGH_52_PA_PIVOT which describes this inflection point,
where this right shift is done thus bringing some clarity to this 52 bits
PA address folding process in TTBRx_EL1.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
This applies on v7.0-rc1
Earlier context can be found here.
https://lore.kernel.org/linux-arm-kernel/aRb8ezhQd0c0jp9G@J2N7QTR9R3/
arch/arm64/include/asm/assembler.h | 2 +-
arch/arm64/include/asm/pgtable-hwdef.h | 14 ++++++++++++++
arch/arm64/include/asm/pgtable.h | 3 ++-
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index d3d46e5f7188..a68002dd4c0e 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -615,7 +615,7 @@ alternative_else_nop_endif
*/
.macro phys_to_ttbr, ttbr, phys
#ifdef CONFIG_ARM64_PA_BITS_52
- orr \ttbr, \phys, \phys, lsr #46
+ orr \ttbr, \phys, \phys, lsr #TTBR_BADDR_52_PA_PIVOT
and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
#else
mov \ttbr, \phys
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index d49180bb7cb3..21ca79f02a5d 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -284,6 +284,20 @@
* TTBR_ELx[1] is RES0 in this configuration.
*/
#define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2)
+
+/*
+ * A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 i.e
+ * GENMASK(47, 2) in a folded manner. Shifting PA[51:0] right ward
+ * by 46 bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed
+ * subsequently for the final TTBRx_EL1 encoding.
+ *
+ * 47 5 2 0
+ * +----------------------------------------------+-----------+--+
+ * | PA[47:X] | PA[51:48] | |
+ * +----------------------------------------------+-----------+--+
+ *
+ */
+#define TTBR_BADDR_52_PA_PIVOT (51 - 5)
#endif
#ifdef CONFIG_ARM64_VA_BITS_52
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b3e58735c49b..2f274c468d83 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -1576,7 +1576,8 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
#ifdef CONFIG_ARM64_PA_BITS_52
-#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
+#define phys_to_ttbr(addr) (((addr) | ((addr) >> TTBR_BADDR_52_PA_PIVOT)) & \
+ TTBR_BADDR_MASK_52)
#else
#define phys_to_ttbr(addr) (addr)
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1
2026-02-26 10:11 [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1 Anshuman Khandual
@ 2026-02-26 11:52 ` Mark Rutland
0 siblings, 0 replies; 2+ messages in thread
From: Mark Rutland @ 2026-02-26 11:52 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Ryan Roberts,
linux-kernel
On Thu, Feb 26, 2026 at 10:11:35AM +0000, Anshuman Khandual wrote:
> A 52 bits physical address gets stored in TTBR_BADDR_MASK_52 in a folded
> manner. Shifting PA[51:0] right ward by '46' bits, aligns PA[51:48] into
> TTBRx_EL1[5:2] which gets ORed for the final TTBRx_EL1 encoding.
>
> Define TTBR_BADDR_HIGH_52_PA_PIVOT which describes this inflection point,
> where this right shift is done thus bringing some clarity to this 52 bits
> PA address folding process in TTBRx_EL1.
TBH, I don't think this is adding much as-is. The phys_to_ttbr macros
are still inscrutable, even with '46' replaced with
'TTBR_BADDR_52_PA_PIVOT'.
As last time, I think this would be better with explcit bit
extraction/insertion, but I don't think it's necessary to actually
change this unless it's enabling something else in future (which it
doesn't seem to).
i.e. I think we should leave this as-is.
Mark.
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Ryan Roberts <ryan.roberts@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> This applies on v7.0-rc1
>
> Earlier context can be found here.
>
> https://lore.kernel.org/linux-arm-kernel/aRb8ezhQd0c0jp9G@J2N7QTR9R3/
>
> arch/arm64/include/asm/assembler.h | 2 +-
> arch/arm64/include/asm/pgtable-hwdef.h | 14 ++++++++++++++
> arch/arm64/include/asm/pgtable.h | 3 ++-
> 3 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index d3d46e5f7188..a68002dd4c0e 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -615,7 +615,7 @@ alternative_else_nop_endif
> */
> .macro phys_to_ttbr, ttbr, phys
> #ifdef CONFIG_ARM64_PA_BITS_52
> - orr \ttbr, \phys, \phys, lsr #46
> + orr \ttbr, \phys, \phys, lsr #TTBR_BADDR_52_PA_PIVOT
> and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
> #else
> mov \ttbr, \phys
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index d49180bb7cb3..21ca79f02a5d 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -284,6 +284,20 @@
> * TTBR_ELx[1] is RES0 in this configuration.
> */
> #define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2)
> +
> +/*
> + * A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 i.e
> + * GENMASK(47, 2) in a folded manner. Shifting PA[51:0] right ward
> + * by 46 bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed
> + * subsequently for the final TTBRx_EL1 encoding.
> + *
> + * 47 5 2 0
> + * +----------------------------------------------+-----------+--+
> + * | PA[47:X] | PA[51:48] | |
> + * +----------------------------------------------+-----------+--+
> + *
> + */
> +#define TTBR_BADDR_52_PA_PIVOT (51 - 5)
> #endif
>
> #ifdef CONFIG_ARM64_VA_BITS_52
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b3e58735c49b..2f274c468d83 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -1576,7 +1576,8 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
> #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
>
> #ifdef CONFIG_ARM64_PA_BITS_52
> -#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
> +#define phys_to_ttbr(addr) (((addr) | ((addr) >> TTBR_BADDR_52_PA_PIVOT)) & \
> + TTBR_BADDR_MASK_52)
> #else
> #define phys_to_ttbr(addr) (addr)
> #endif
> --
> 2.30.2
>
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2026-02-26 10:11 [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1 Anshuman Khandual
2026-02-26 11:52 ` Mark Rutland
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