[PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[Richard Zhu]

When the internal PLL is used as the PCIe reference clock source on i.MX95,
a REFCLK rise-fall time mismatch is observed during PCIe Gen1 compliance
testing with the Lfast IO analyzer.

Fix this issue by configuring the IREF_TX field to 0xF (15), which adjusts
the transmitter current reference to meet the PCIe specification timing
requirements.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 1f9259f45607..bc6957299cec 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data {
 	const char * const *parent_names;
 	u32 num_parents;
 	u32 reg;
+	u32 reg_init_msk;
+	u32 reg_init_val;
 	u32 bit_idx;
 	u32 bit_width;
 	u32 clk_type;
@@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
 		.parent_names = (const char *[]){ "func_out_en", },
 		.num_parents = 1,
 		.reg = 0,
+		.reg_init_msk = GENMASK(10, 7),
+		.reg_init_val = GENMASK(10, 7),
 		.bit_idx = 6,
 		.bit_width = 1,
 		.type = CLK_GATE,
@@ -410,6 +414,9 @@ static int imx95_bc_probe(struct platform_device *pdev)
 		const struct imx95_blk_ctl_clk_dev_data *data = &bc->pdata->clk_dev_data[i];
 		void __iomem *reg = base + data->reg;
 
+		if (data->reg_init_msk)
+			writel((readl(reg) & ~data->reg_init_msk) | data->reg_init_val, reg);
+
 		if (data->type == CLK_MUX) {
 			hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
 						     data->num_parents, data->flags, reg,
-- 
2.37.1

RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[Peng Fan]

Hi Richard,

> Subject: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on
> i.MX95
> 
> When the internal PLL is used as the PCIe reference clock source on
> i.MX95, a REFCLK rise-fall time mismatch is observed during PCIe Gen1
> compliance testing with the Lfast IO analyzer.
> 
> Fix this issue by configuring the IREF_TX field to 0xF (15), which adjusts
> the transmitter current reference to meet the PCIe specification timing
> requirements.

BLK CTRL in HSIOMIX should be save/restore for the settings you configured
in probe phase.

Regards
Peng.

> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-
> imx95-blk-ctl.c
> index 1f9259f45607..bc6957299cec 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data {
>  	const char * const *parent_names;
>  	u32 num_parents;
>  	u32 reg;
> +	u32 reg_init_msk;
> +	u32 reg_init_val;
>  	u32 bit_idx;
>  	u32 bit_width;
>  	u32 clk_type;
> @@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data
> hsio_blk_ctl_clk_dev_data[] = {
>  		.parent_names = (const char *[]){ "func_out_en", },
>  		.num_parents = 1,
>  		.reg = 0,
> +		.reg_init_msk = GENMASK(10, 7),
> +		.reg_init_val = GENMASK(10, 7),
>  		.bit_idx = 6,
>  		.bit_width = 1,
>  		.type = CLK_GATE,
> @@ -410,6 +414,9 @@ static int imx95_bc_probe(struct
> platform_device *pdev)
>  		const struct imx95_blk_ctl_clk_dev_data *data = &bc-
> >pdata->clk_dev_data[i];
>  		void __iomem *reg = base + data->reg;
> 
> +		if (data->reg_init_msk)
> +			writel((readl(reg) & ~data->reg_init_msk) |
> data->reg_init_val,
> +reg);
> +
>  		if (data->type == CLK_MUX) {
>  			hws[i] = clk_hw_register_mux(dev, data-
> >name, data->parent_names,
>  						     data-
> >num_parents, data->flags, reg,
> --
> 2.37.1

RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[Hongxing Zhu]

> -----Original Message-----
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Friday, April 17, 2026 5:22 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; abelvesa@kernel.org;
> mturquette@baylibre.com; sboyd@kernel.org; Frank Li <frank.li@nxp.com>;
> s.hauer@pengutronix.de; festevam@gmail.com
> Cc: linux-clk@vger.kernel.org; imx@nxp.com; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; kernel@pengutronix.de
> Subject: RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on
> i.MX95
> 
> Hi Richard,
> 
> > Subject: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch
> > on
> > i.MX95
> >
> > When the internal PLL is used as the PCIe reference clock source on
> > i.MX95, a REFCLK rise-fall time mismatch is observed during PCIe Gen1
> > compliance testing with the Lfast IO analyzer.
> >
> > Fix this issue by configuring the IREF_TX field to 0xF (15), which
> > adjusts the transmitter current reference to meet the PCIe
> > specification timing requirements.
> 
> BLK CTRL in HSIOMIX should be save/restore for the settings you configured in
> probe phase.
Good suggestion, thanks.

Best Regards
Richard Zhu
> 
> Regards
> Peng.
> 
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > b/drivers/clk/imx/clk- imx95-blk-ctl.c index
> > 1f9259f45607..bc6957299cec 100644
> > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > @@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data {
> >  	const char * const *parent_names;
> >  	u32 num_parents;
> >  	u32 reg;
> > +	u32 reg_init_msk;
> > +	u32 reg_init_val;
> >  	u32 bit_idx;
> >  	u32 bit_width;
> >  	u32 clk_type;
> > @@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data
> > hsio_blk_ctl_clk_dev_data[] = {
> >  		.parent_names = (const char *[]){ "func_out_en", },
> >  		.num_parents = 1,
> >  		.reg = 0,
> > +		.reg_init_msk = GENMASK(10, 7),
> > +		.reg_init_val = GENMASK(10, 7),
> >  		.bit_idx = 6,
> >  		.bit_width = 1,
> >  		.type = CLK_GATE,
> > @@ -410,6 +414,9 @@ static int imx95_bc_probe(struct platform_device
> > *pdev)
> >  		const struct imx95_blk_ctl_clk_dev_data *data = &bc-
> > >pdata->clk_dev_data[i];
> >  		void __iomem *reg = base + data->reg;
> >
> > +		if (data->reg_init_msk)
> > +			writel((readl(reg) & ~data->reg_init_msk) |
> > data->reg_init_val,
> > +reg);
> > +
> >  		if (data->type == CLK_MUX) {
> >  			hws[i] = clk_hw_register_mux(dev, data-
> > >name, data->parent_names,
> >  						     data-
> > >num_parents, data->flags, reg,
> > --
> > 2.37.1

RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[Hongxing Zhu]

> -----Original Message-----
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Friday, April 17, 2026 5:22 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; abelvesa@kernel.org;
> mturquette@baylibre.com; sboyd@kernel.org; Frank Li <frank.li@nxp.com>;
> s.hauer@pengutronix.de; festevam@gmail.com
> Cc: linux-clk@vger.kernel.org; imx@nxp.com; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; kernel@pengutronix.de
> Subject: RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on
> i.MX95
> 
> Hi Richard,
> 
> > Subject: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch
> > on
> > i.MX95
> >
> > When the internal PLL is used as the PCIe reference clock source on
> > i.MX95, a REFCLK rise-fall time mismatch is observed during PCIe Gen1
> > compliance testing with the Lfast IO analyzer.
> >
> > Fix this issue by configuring the IREF_TX field to 0xF (15), which
> > adjusts the transmitter current reference to meet the PCIe
> > specification timing requirements.
> 
> BLK CTRL in HSIOMIX should be save/restore for the settings you configured in
> probe phase.
Hi Peng:
The register containing the pre-configured settings is the same as the
gate-clock register. Therefore, its value will be saved and restored during
the suspend/resume procedures.
Thanks.

Best Regards
Richard Zhu
> 
> Regards
> Peng.
> 
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > b/drivers/clk/imx/clk- imx95-blk-ctl.c index
> > 1f9259f45607..bc6957299cec 100644
> > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > @@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data {
> >  	const char * const *parent_names;
> >  	u32 num_parents;
> >  	u32 reg;
> > +	u32 reg_init_msk;
> > +	u32 reg_init_val;
> >  	u32 bit_idx;
> >  	u32 bit_width;
> >  	u32 clk_type;
> > @@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data
> > hsio_blk_ctl_clk_dev_data[] = {
> >  		.parent_names = (const char *[]){ "func_out_en", },
> >  		.num_parents = 1,
> >  		.reg = 0,
> > +		.reg_init_msk = GENMASK(10, 7),
> > +		.reg_init_val = GENMASK(10, 7),
> >  		.bit_idx = 6,
> >  		.bit_width = 1,
> >  		.type = CLK_GATE,
> > @@ -410,6 +414,9 @@ static int imx95_bc_probe(struct platform_device
> > *pdev)
> >  		const struct imx95_blk_ctl_clk_dev_data *data = &bc-
> > >pdata->clk_dev_data[i];
> >  		void __iomem *reg = base + data->reg;
> >
> > +		if (data->reg_init_msk)
> > +			writel((readl(reg) & ~data->reg_init_msk) |
> > data->reg_init_val,
> > +reg);
> > +
> >  		if (data->type == CLK_MUX) {
> >  			hws[i] = clk_hw_register_mux(dev, data-
> > >name, data->parent_names,
> >  						     data-
> > >num_parents, data->flags, reg,
> > --
> > 2.37.1

Re: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95

[Peng Fan]

On Fri, Apr 17, 2026 at 04:29:10PM +0800, Richard Zhu wrote:
>When the internal PLL is used as the PCIe reference clock source on i.MX95,
>a REFCLK rise-fall time mismatch is observed during PCIe Gen1 compliance
>testing with the Lfast IO analyzer.
>
>Fix this issue by configuring the IREF_TX field to 0xF (15), which adjusts
>the transmitter current reference to meet the PCIe specification timing
>requirements.
>
>Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>