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* [PATCH] clk: samsung: exynos5410: fix refcount leak
@ 2026-05-26  6:13 Alexander A. Klimov
  2026-05-26 17:29 ` Brian Masney
  0 siblings, 1 reply; 2+ messages in thread
From: Alexander A. Klimov @ 2026-05-26  6:13 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
	Alim Akhtar, Michael Turquette, Stephen Boyd, Brian Masney,
	open list:SAMSUNG SOC CLOCK DRIVERS,
	open list:COMMON CLK FRAMEWORK,
	moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
	open list
  Cc: Alexander A. Klimov

Every value returned from of_clk_get() is supposed to be cleaned up
via clk_put() once not needed anymore.

Fixes: be95d2c7d918 ("clk: samsung: Add support for EPLL on exynos5410")
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
---
 drivers/clk/samsung/clk-exynos5410.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index baa9988c7bb7..0cd9b0392cf5 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -269,8 +269,12 @@ static void __init exynos5410_clk_init(struct device_node *np)
 {
 	struct clk *xxti = of_clk_get(np, 0);
 
-	if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
-		exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
+	if (!IS_ERR(xxti)) {
+		if (clk_get_rate(xxti) == 24 * MHZ)
+			exynos5410_plls[epll].rate_table =
+				exynos5410_pll2550x_24mhz_tbl;
+		clk_put(xxti);
+	}
 
 	samsung_cmu_register_one(np, &cmu);
 
-- 
2.54.0



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2026-05-26  6:13 [PATCH] clk: samsung: exynos5410: fix refcount leak Alexander A. Klimov
2026-05-26 17:29 ` Brian Masney

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