[PATCH v2 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence

[PATCH v2 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence

[Richard Zhu]

This series addresses PHY initialization sequence issues for i.MX95 PCIe
that were identified through careful review of the i.MX95 PCIe PHY Databook.

The current implementation does not strictly follow the timing requirements
specified in the PHY documentation for reference clock configuration and
PHY reset sequencing. These violations can potentially lead to unreliable
PHY initialization.

Patch 1 ensures that the REF_USE_PAD configuration is applied before the
PHY reset is toggled, as required by the Common Block Signals specification.
Any change to ref_use_pad must be followed by a PHY reset assertion to take
effect properly.

Patch 2 corrects the ref_clk_en signal timing by moving its manipulation
into the reference clock enable function. This ensures the reference clock
is stable before ref_clk_en is asserted and before the PHY reset is
de-asserted, meeting the PHY's power sequencing requirements.

Together, these patches ensure proper PHY initialization sequence compliance
and improve the reliability of PCIe operation on i.MX95 platforms.

Changes in v2:
Correct the register when configure REF_USE_PAD bit.
Rebase to controller/dwc-imx6 branch of pci git repo.
Collect the Reviewed-by tag.

[PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for
[PATCH v2 2/2] PCI: imx6: Assert ref_clk_en after reference clock

drivers/pci/controller/dwc/pci-imx6.c | 53 +++++++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 45 insertions(+), 8 deletions(-)

[PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95

[Richard Zhu]

According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
Common Block Signals section selects the reference clock source connected
to the PHY pads. Per the specification, any change to this input must be
followed by a PHY reset assertion to take effect.

Move the REF_USE_PAD configuration before the PHY reset toggle to comply
with the required initialization sequence.

Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
Cc: <stable@vger.kernel.org>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 002e0a0d9382..66e760015c92 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
 	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
 	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
 	const struct pci_epc_features *epc_features;
+	int (*init_pre_reset)(struct imx_pcie *pcie);
 	int (*init_phy)(struct imx_pcie *pcie);
 	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
 	int (*core_reset)(struct imx_pcie *pcie, bool assert);
@@ -249,6 +250,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 	return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
+static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
+{
+	bool ext = imx_pcie->enable_ext_refclk;
+
+	/*
+	 * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
+	 * used to select reference clock connected to a pair of pads.
+	 *
+	 * Any change in this input must be followed by phy_reset assertion.
+	 */
+
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+			   IMX95_PCIE_REF_USE_PAD,
+			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
+
+	return 0;
+}
+
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
 	bool ext = imx_pcie->enable_ext_refclk;
@@ -271,9 +290,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
-			   IMX95_PCIE_REF_USE_PAD,
-			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
 	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
 			   IMX95_PCIE_REF_CLKEN,
 			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
@@ -1348,6 +1364,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
 		pp->bridge->disable_device = imx_pcie_disable_device;
 	}
 
+	if (imx_pcie->drvdata->init_pre_reset)
+		imx_pcie->drvdata->init_pre_reset(imx_pcie);
+
 	imx_pcie_assert_core_reset(imx_pcie);
 
 	if (imx_pcie->drvdata->init_phy)
@@ -2047,6 +2066,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
 		.core_reset = imx95_pcie_core_reset,
 		.init_phy = imx95_pcie_init_phy,
+		.init_pre_reset = imx95_pcie_init_pre_reset,
 		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
 		.enable_ref_clk = imx95_pcie_enable_ref_clk,
 		.clr_clkreq_override = imx95_pcie_clr_clkreq_override,
@@ -2102,6 +2122,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
 		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
 		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+		.init_pre_reset = imx95_pcie_init_pre_reset,
 		.init_phy = imx95_pcie_init_phy,
 		.core_reset = imx95_pcie_core_reset,
 		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,

base-commit: 40b7f61a1a4d7fd18188f3f87e15ff5a90ce1d31
-- 
2.37.1

Re: [PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95

[Manivannan Sadhasivam]

On Mon, May 18, 2026 at 03:27:14PM +0800, Richard Zhu wrote:
> According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
> Common Block Signals section selects the reference clock source connected
> to the PHY pads. Per the specification, any change to this input must be
> followed by a PHY reset assertion to take effect.
> 
> Move the REF_USE_PAD configuration before the PHY reset toggle to comply
> with the required initialization sequence.
> 
> Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 002e0a0d9382..66e760015c92 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
>  	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
>  	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
>  	const struct pci_epc_features *epc_features;
> +	int (*init_pre_reset)(struct imx_pcie *pcie);

I renamed the callback and helper while applying:

s/init_pre_reset/select_ref_clk_src

- Mani

>  	int (*init_phy)(struct imx_pcie *pcie);
>  	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
>  	int (*core_reset)(struct imx_pcie *pcie, bool assert);
> @@ -249,6 +250,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
>  	return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
>  }
>  
> +static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
> +{
> +	bool ext = imx_pcie->enable_ext_refclk;
> +
> +	/*
> +	 * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
> +	 * used to select reference clock connected to a pair of pads.
> +	 *
> +	 * Any change in this input must be followed by phy_reset assertion.
> +	 */
> +
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
> +			   IMX95_PCIE_REF_USE_PAD,
> +			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
> +
> +	return 0;
> +}
> +
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  {
>  	bool ext = imx_pcie->enable_ext_refclk;
> @@ -271,9 +290,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
>  			IMX95_PCIE_PHY_CR_PARA_SEL);
>  
> -	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
> -			   IMX95_PCIE_REF_USE_PAD,
> -			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
>  	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
>  			   IMX95_PCIE_REF_CLKEN,
>  			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
> @@ -1348,6 +1364,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
>  		pp->bridge->disable_device = imx_pcie_disable_device;
>  	}
>  
> +	if (imx_pcie->drvdata->init_pre_reset)
> +		imx_pcie->drvdata->init_pre_reset(imx_pcie);
> +
>  	imx_pcie_assert_core_reset(imx_pcie);
>  
>  	if (imx_pcie->drvdata->init_phy)
> @@ -2047,6 +2066,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
>  		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
> +		.init_pre_reset = imx95_pcie_init_pre_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>  		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  		.clr_clkreq_override = imx95_pcie_clr_clkreq_override,
> @@ -2102,6 +2122,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> +		.init_pre_reset = imx95_pcie_init_pre_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  		.core_reset = imx95_pcie_core_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> 
> base-commit: 40b7f61a1a4d7fd18188f3f87e15ff5a90ce1d31
> -- 
> 2.37.1
> 

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <mani@kernel.org>
> Sent: Tuesday, June 9, 2026 11:48 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kwilczynski@kernel.org; robh@kernel.org; bhelgaas@google.com;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-
> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org; stable@vger.kernel.org
> Subject: Re: [PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset
> for i.MX95
> 
> On Mon, May 18, 2026 at 03:27:14PM +0800, Richard Zhu wrote:
> > According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in
> > the Common Block Signals section selects the reference clock source
> > connected to the PHY pads. Per the specification, any change to this
> > input must be followed by a PHY reset assertion to take effect.
> >
> > Move the REF_USE_PAD configuration before the PHY reset toggle to
> > comply with the required initialization sequence.
> >
> > Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95
> > PCIe")
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 27
> > ++++++++++++++++++++++++---
> >  1 file changed, 24 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 002e0a0d9382..66e760015c92 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
> >  	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
> >  	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> >  	const struct pci_epc_features *epc_features;
> > +	int (*init_pre_reset)(struct imx_pcie *pcie);
> 
> I renamed the callback and helper while applying:
> 
> s/init_pre_reset/select_ref_clk_src
Thanks for your kindly help.

Best Regards
Richard Zhu
> 
> - Mani
> 
> >  	int (*init_phy)(struct imx_pcie *pcie);
> >  	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
> >  	int (*core_reset)(struct imx_pcie *pcie, bool assert); @@ -249,6
> > +250,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie
> *imx_pcie)
> >  	return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 :
> IOMUXC_GPR14;
> > }
> >
> > +static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie) {
> > +	bool ext = imx_pcie->enable_ext_refclk;
> > +
> > +	/*
> > +	 * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
> > +	 * used to select reference clock connected to a pair of pads.
> > +	 *
> > +	 * Any change in this input must be followed by phy_reset assertion.
> > +	 */
> > +
> > +	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_GEN_CTRL,
> > +			   IMX95_PCIE_REF_USE_PAD,
> > +			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
> > +
> > +	return 0;
> > +}
> > +
> >  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)  {
> >  	bool ext = imx_pcie->enable_ext_refclk; @@ -271,9 +290,6 @@ static
> > int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> >  			IMX95_PCIE_PHY_CR_PARA_SEL,
> >  			IMX95_PCIE_PHY_CR_PARA_SEL);
> >
> > -	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_GEN_CTRL,
> > -			   IMX95_PCIE_REF_USE_PAD,
> > -			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
> >  	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
> >  			   IMX95_PCIE_REF_CLKEN,
> >  			   ext ? 0 : IMX95_PCIE_REF_CLKEN); @@ -1348,6
> +1364,9 @@ static
> > int imx_pcie_host_init(struct dw_pcie_rp *pp)
> >  		pp->bridge->disable_device = imx_pcie_disable_device;
> >  	}
> >
> > +	if (imx_pcie->drvdata->init_pre_reset)
> > +		imx_pcie->drvdata->init_pre_reset(imx_pcie);
> > +
> >  	imx_pcie_assert_core_reset(imx_pcie);
> >
> >  	if (imx_pcie->drvdata->init_phy)
> > @@ -2047,6 +2066,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> >  		.core_reset = imx95_pcie_core_reset,
> >  		.init_phy = imx95_pcie_init_phy,
> > +		.init_pre_reset = imx95_pcie_init_pre_reset,
> >  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> >  		.enable_ref_clk = imx95_pcie_enable_ref_clk,
> >  		.clr_clkreq_override = imx95_pcie_clr_clkreq_override, @@ -
> 2102,6
> > +2122,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > +		.init_pre_reset = imx95_pcie_init_pre_reset,
> >  		.init_phy = imx95_pcie_init_phy,
> >  		.core_reset = imx95_pcie_core_reset,
> >  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> >
> > base-commit: 40b7f61a1a4d7fd18188f3f87e15ff5a90ce1d31
> > --
> > 2.37.1
> >
> 
> --
> மணிவண்ணன் சதாசிவம்

[PATCH v2 2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95

[Richard Zhu]

According to the PHY Databook Common Block Signals section, the
ref_clk_en signal must remain de-asserted until the reference clock is
running at the appropriate frequency. Once the clock is stable,
ref_clk_en can be asserted. For lower power states where the reference
clock to the PHY is disabled, ref_clk_en should also be de-asserted.

Move the ref_clk_en bit manipulation into imx95_pcie_enable_ref_clk()
to ensure the reference clock stabilizes before ref_clk_en is asserted
and before the PHY reset is de-asserted. This aligns with the timing
requirements specified in the PHY documentation.

Fixes: d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++------
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 66e760015c92..c4b079c93648 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -270,8 +270,6 @@ static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
-	bool ext = imx_pcie->enable_ext_refclk;
-
 	/*
 	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
 	 * Through Beacon or PERST# De-assertion
@@ -290,10 +288,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
-			   IMX95_PCIE_REF_CLKEN,
-			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
-
 	return 0;
 }
 
@@ -742,7 +736,29 @@ static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
 
 static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 {
+	bool ext = imx_pcie->enable_ext_refclk;
+
 	imx95_pcie_clkreq_override(imx_pcie, enable);
+	/*
+	 * The ref_clk_en signal must remain de-asserted until the
+	 * reference clock is running at appropriate frequency, at which
+	 * point this bit can be asserted. For lower power states where
+	 * the reference clock to the PHY is disabled, it may also be
+	 * de-asserted.
+	 * +------------------- -+--------+----------------+
+	 * | External clock mode | Enable | PCIE_REF_CLKEN |
+	 * +---------------------+--------+----------------+
+	 * | TRUE                | X      | 1b'0           |
+	 * +---------------------+--------+----------------+
+	 * | FALSE               | TRUE   | 1b'1           |
+	 * +---------------------+--------+----------------+
+	 * | FALSE               | FALSE  | 1b'0           |
+	 * +---------------------+--------+----------------+
+	 */
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
+			   IMX95_PCIE_REF_CLKEN,
+			   ext || !enable ? 0 : IMX95_PCIE_REF_CLKEN);
+
 	return 0;
 }
 
-- 
2.37.1

Re: [PATCH v2 2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95

[Frank Li]

On Mon, May 18, 2026 at 03:27:15PM +0800, Richard Zhu wrote:
> According to the PHY Databook Common Block Signals section, the
> ref_clk_en signal must remain de-asserted until the reference clock is
> running at the appropriate frequency. Once the clock is stable,
> ref_clk_en can be asserted. For lower power states where the reference
> clock to the PHY is disabled, ref_clk_en should also be de-asserted.
>
> Move the ref_clk_en bit manipulation into imx95_pcie_enable_ref_clk()
> to ensure the reference clock stabilizes before ref_clk_en is asserted
> and before the PHY reset is de-asserted. This aligns with the timing
> requirements specified in the PHY documentation.
>
> Fixes: d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++------
>  1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 66e760015c92..c4b079c93648 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -270,8 +270,6 @@ static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
>
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  {
> -	bool ext = imx_pcie->enable_ext_refclk;
> -
>  	/*
>  	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
>  	 * Through Beacon or PERST# De-assertion
> @@ -290,10 +288,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
>  			IMX95_PCIE_PHY_CR_PARA_SEL);
>
> -	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> -			   IMX95_PCIE_REF_CLKEN,
> -			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
> -
>  	return 0;
>  }
>
> @@ -742,7 +736,29 @@ static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
>
>  static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  {
> +	bool ext = imx_pcie->enable_ext_refclk;
> +
>  	imx95_pcie_clkreq_override(imx_pcie, enable);
> +	/*
> +	 * The ref_clk_en signal must remain de-asserted until the
> +	 * reference clock is running at appropriate frequency, at which
> +	 * point this bit can be asserted. For lower power states where
> +	 * the reference clock to the PHY is disabled, it may also be
> +	 * de-asserted.
> +	 * +------------------- -+--------+----------------+
> +	 * | External clock mode | Enable | PCIE_REF_CLKEN |
> +	 * +---------------------+--------+----------------+
> +	 * | TRUE                | X      | 1b'0           |
> +	 * +---------------------+--------+----------------+
> +	 * | FALSE               | TRUE   | 1b'1           |
> +	 * +---------------------+--------+----------------+
> +	 * | FALSE               | FALSE  | 1b'0           |
> +	 * +---------------------+--------+----------------+
> +	 */
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> +			   IMX95_PCIE_REF_CLKEN,
> +			   ext || !enable ? 0 : IMX95_PCIE_REF_CLKEN);
> +
>  	return 0;
>  }
>
> --
> 2.37.1
>

Re: [PATCH v2 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence

[Manivannan Sadhasivam]

On Mon, 18 May 2026 15:27:13 +0800, Richard Zhu wrote:
> This series addresses PHY initialization sequence issues for i.MX95 PCIe
> that were identified through careful review of the i.MX95 PCIe PHY Databook.
> 
> The current implementation does not strictly follow the timing requirements
> specified in the PHY documentation for reference clock configuration and
> PHY reset sequencing. These violations can potentially lead to unreliable
> PHY initialization.
> 
> [...]

Applied, thanks!

[1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95
      commit: 0c26b1c34d12d4debfb5363cc0be6cdf68e87ba2
[2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95
      commit: 9dda3f83ba677b9cc2613cecd9120123000ae50f

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>