From: Vincent Donnefort <vdonnefort@google.com>
To: Fuad Tabba <tabba@google.com>
Cc: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Steffen Eiden <seiden@linux.ibm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Quentin Perret <qperret@google.com>,
Sebastian Ene <sebastianene@google.com>,
Hyunwoo Kim <imv4bel@gmail.com>
Subject: Re: [PATCH v2 2/8] KVM: arm64: Make vcpu_{read,write}_sys_reg available to HYP code
Date: Fri, 19 Jun 2026 14:26:34 +0100 [thread overview]
Message-ID: <ajVDijsleEVAV-ss@google.com> (raw)
In-Reply-To: <20260619070719.812227-3-tabba@google.com>
On Fri, Jun 19, 2026 at 08:07:13AM +0100, Fuad Tabba wrote:
> The vcpu_{read,write}_sys_reg() accessors are host-only, so helpers
> built on them such as kvm_vcpu_set_be()/kvm_vcpu_is_be() cannot be
> shared with hyp code. exception.c already wraps them in
> __vcpu_{read,write}_sys_reg(), which pick the host- or hyp-side accessor
> via has_vhe() and so are valid in any context.
>
> Move those wrappers to kvm_emulate.h as kvm_vcpu_{read,write}_sys_reg()
> and switch the callers over, so a follow-up series can share that
> emulation code at EL2.
>
> No functional change intended.
>
> Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Vincent Donnefort <vdonnefort@google.com>
> ---
> arch/arm64/include/asm/kvm_emulate.h | 22 +++++++++++++++---
> arch/arm64/kvm/hyp/exception.c | 34 ++++++++--------------------
> 2 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index 5bf3d7e1d92c..80b30fead3d1 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -506,6 +506,22 @@ static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
> return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
> }
>
> +static inline u64 kvm_vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
> +{
> + if (has_vhe())
> + return vcpu_read_sys_reg(vcpu, reg);
> +
> + return __vcpu_sys_reg(vcpu, reg);
> +}
> +
> +static inline void kvm_vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
> +{
> + if (has_vhe())
> + vcpu_write_sys_reg(vcpu, val, reg);
> + else
> + __vcpu_assign_sys_reg(vcpu, reg, val);
> +}
> +
> static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
> {
> if (vcpu_mode_is_32bit(vcpu)) {
> @@ -516,9 +532,9 @@ static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
>
> r = vcpu_has_nv(vcpu) ? SCTLR_EL2 : SCTLR_EL1;
>
> - sctlr = vcpu_read_sys_reg(vcpu, r);
> + sctlr = kvm_vcpu_read_sys_reg(vcpu, r);
> sctlr |= SCTLR_ELx_EE;
> - vcpu_write_sys_reg(vcpu, sctlr, r);
> + kvm_vcpu_write_sys_reg(vcpu, sctlr, r);
> }
> }
>
> @@ -533,7 +549,7 @@ static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
> r = is_hyp_ctxt(vcpu) ? SCTLR_EL2 : SCTLR_EL1;
> bit = vcpu_mode_priv(vcpu) ? SCTLR_ELx_EE : SCTLR_EL1_E0E;
>
> - return vcpu_read_sys_reg(vcpu, r) & bit;
> + return kvm_vcpu_read_sys_reg(vcpu, r) & bit;
> }
>
> static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
> diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c
> index bef40ddb16db..2cb68dc7d441 100644
> --- a/arch/arm64/kvm/hyp/exception.c
> +++ b/arch/arm64/kvm/hyp/exception.c
> @@ -20,22 +20,6 @@
> #error Hypervisor code only!
> #endif
>
> -static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
> -{
> - if (has_vhe())
> - return vcpu_read_sys_reg(vcpu, reg);
> -
> - return __vcpu_sys_reg(vcpu, reg);
> -}
> -
> -static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
> -{
> - if (has_vhe())
> - vcpu_write_sys_reg(vcpu, val, reg);
> - else
> - __vcpu_assign_sys_reg(vcpu, reg, val);
> -}
> -
> static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode,
> u64 val)
> {
> @@ -101,14 +85,14 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
>
> switch (target_mode) {
> case PSR_MODE_EL1h:
> - vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL1);
> - sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> - __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1);
> + vbar = kvm_vcpu_read_sys_reg(vcpu, VBAR_EL1);
> + sctlr = kvm_vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> + kvm_vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1);
> break;
> case PSR_MODE_EL2h:
> - vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL2);
> - sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL2);
> - __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2);
> + vbar = kvm_vcpu_read_sys_reg(vcpu, VBAR_EL2);
> + sctlr = kvm_vcpu_read_sys_reg(vcpu, SCTLR_EL2);
> + kvm_vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2);
> break;
> default:
> /* Don't do that */
> @@ -185,7 +169,7 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
> */
> static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
> {
> - u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> + u32 sctlr = kvm_vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> unsigned long old, new;
>
> old = *vcpu_cpsr(vcpu);
> @@ -281,7 +265,7 @@ static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
> {
> unsigned long spsr = *vcpu_cpsr(vcpu);
> bool is_thumb = (spsr & PSR_AA32_T_BIT);
> - u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> + u32 sctlr = kvm_vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> u32 return_address;
>
> *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
> @@ -305,7 +289,7 @@ static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
> if (sctlr & (1 << 13))
> vect_offset += 0xffff0000;
> else /* always have security exceptions */
> - vect_offset += __vcpu_read_sys_reg(vcpu, VBAR_EL1);
> + vect_offset += kvm_vcpu_read_sys_reg(vcpu, VBAR_EL1);
>
> *vcpu_pc(vcpu) = vect_offset;
> }
> --
> 2.55.0.rc0.738.g0c8ab3ebcc-goog
>
next prev parent reply other threads:[~2026-06-19 13:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-19 7:07 [PATCH v2 0/8] KVM: arm64: Rework pKVM vCPU state synchronisation Fuad Tabba
2026-06-19 7:07 ` [PATCH v2 1/8] KVM: arm64: Extract MPIDR computation into a shared header Fuad Tabba
2026-06-19 13:24 ` Vincent Donnefort
2026-06-19 7:07 ` [PATCH v2 2/8] KVM: arm64: Make vcpu_{read,write}_sys_reg available to HYP code Fuad Tabba
2026-06-19 13:26 ` Vincent Donnefort [this message]
2026-06-19 7:07 ` [PATCH v2 3/8] KVM: arm64: Factor out reusable vCPU reset helpers Fuad Tabba
2026-06-19 13:29 ` Vincent Donnefort
2026-06-19 7:07 ` [PATCH v2 4/8] KVM: arm64: Move PSCI helper functions to a shared header Fuad Tabba
2026-06-19 13:30 ` Vincent Donnefort
2026-06-19 7:07 ` [PATCH v2 5/8] KVM: arm64: Add host and hypervisor vCPU lookup primitives Fuad Tabba
2026-06-19 13:31 ` Vincent Donnefort
2026-06-19 7:07 ` [PATCH v2 6/8] KVM: arm64: Minimise EL2's exposure of host VGIC state during world switch Fuad Tabba
2026-06-19 7:07 ` [PATCH v2 7/8] KVM: arm64: Add primitives to flush/sync the VGIC state at EL2 Fuad Tabba
2026-06-19 7:07 ` [PATCH v2 8/8] KVM: arm64: Implement lazy vCPU state sync for non-protected guests Fuad Tabba
2026-06-19 13:12 ` Vincent Donnefort
2026-06-19 16:41 ` Fuad Tabba
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