* [PATCH 0/2] fix clock refcount imbalance for all Coresight platform drivers
@ 2026-07-01 6:05 Jie Gan
2026-07-01 6:05 ` [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan
2026-07-01 6:05 ` [PATCH 2/2] coresight: tnoc: " Jie Gan
0 siblings, 2 replies; 5+ messages in thread
From: Jie Gan @ 2026-07-01 6:05 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Anshuman Khandual, Yeoreum Yun,
Yuanfang Zhang, Maxime Coquelin, Alexandre Torgue, Tingwei Zhang
Cc: coresight, linux-arm-kernel, linux-kernel, linux-stm32, Jie Gan
Found a clock imbalance issue when remove the CTCU module.
coresight_get_enable_clocks() enables the programming clock and the
optional AT clock through devm_clk_get_optional_enabled(), which also
registers a devm action to call clk_disable_unprepare() when the driver
detaches.
After probe, pm_runtime_put() allows the device to suspend and the
runtime suspend callback disables the same clocks. During remove the
device is left runtime suspended, so pm_runtime_disable() freezes it
with the clocks already disabled. The devm cleanup that runs afterwards
calls clk_disable_unprepare() a second time, underflowing the clock
enable refcount.
Resume the device with pm_runtime_get_sync() before pm_runtime_disable()
so the clocks are enabled again and balance the devm-managed disable.
Calltrace:
[ 194.074015] ------------[ cut here ]------------
[ 194.078779] qdss already disabled
[ 194.082210] WARNING: drivers/clk/clk.c:1188 at clk_core_disable+0x238/0x240, CPU#4: rmmod/508
[ 194.090976] Modules linked in: coresight_ctcu(-) snd_soc_hdmi_codec snd_soc_core snd_compress snd_pcm_dmaengine snd_pcm snd_timer snd soundcore 8021q garp mrp phy_qcom_edp stp af_alg llc anx7625 typec pci_pwrctrl_pwrseq hci_uart qcom_iris v4l2_mem2mem btqca btbcm qcom_pon videobuf2_dma_contig rtc_pm8xxx nvmem_qcom_spmi_sdam qcom_spmi_temp_alarm videobuf2_memops qrtr videobuf2_v4l2 bluetooth msm qcom_stats pwrseq_qcom_wcn ubwc_config videodev ocmem ecdh_generic drm_gpuvm videobuf2_common drm_exec gpu_sched qcom_q6v5_pas kpp marvell videocc_sa8775p camcc_sa8775p ecc drm_dp_aux_bus dispcc0_sa8775p spi_geni_qcom i2c_qcom_geni llcc_qcom mc qcom_refgen_regulator phy_qcom_snps_femto_v2 phy_qcom_qmp_usb icc_bwmon phy_qcom_sgmii_eth dwmac_qcom_ethqos qcom_pil_info gpucc_sa8775p qcom_q6v5 stmmac_platform stmmac ufs_qcom qcom_sysmon drm_display_helper qcom_common pcs_xpcs phylink cec qcom_glink_smem qcrypto drm_client_lib mdt_loader dispcc1_sa8775p qmi_helpers phy_qcom_qmp_ufs libdes qcom_ice display_connector phy_qcom_qmp_pcie
[ 194.091130] qcom_wdt qcomtee nvmem_reboot_mode icc_osm_l3 qcom_rng drm_kms_helper cfg80211 rfkill socinfo fuse drm backlight stm_p_basic
[ 194.196124] CPU: 4 UID: 0 PID: 508 Comm: rmmod Not tainted 7.1.0-next-20260623-00008-ga4671328ba36 #831 PREEMPT
[ 194.206566] Hardware name: Qualcomm SA8775P Ride (DT)
[ 194.211771] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 194.218938] pc : clk_core_disable+0x238/0x240
[ 194.223426] lr : clk_core_disable+0x238/0x240
[ 194.227908] sp : ffff8000889fbb40
[ 194.231327] x29: ffff8000889fbb40 x28: ffff0000972eb580 x27: 0000000000000000
[ 194.238662] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000000
[ 194.245995] x23: ffffd181d3de4620 x22: ffff8000889fbc28 x21: ffff000082382810
[ 194.253322] x20: ffff000082334a00 x19: ffff000082334a00 x18: 0000000000000006
[ 194.260658] x17: ffffd181d293fb18 x16: ffffd181d295c3c8 x15: ffff8000889fb550
[ 194.267991] x14: 0000000000000000 x13: ffffd181d4eea620 x12: 00000000000004cf
[ 194.275346] x11: 0000000000000e6d x10: ffffd181d4f42620 x9 : ffffd181d4eea620
[ 194.282676] x8 : 3fffffffffffefff x7 : ffffd181d4f42620 x6 : bffffffffffff000
[ 194.290007] x5 : ffff000ead974248 x4 : 0000000000000000 x3 : ffff2e8cd9611000
[ 194.297338] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000972eb580
[ 194.304671] Call trace:
[ 194.307199] clk_core_disable+0x238/0x240 (P)
[ 194.311687] clk_disable+0x30/0x4c
[ 194.315192] clk_disable_unprepare+0x18/0x30
[ 194.319596] devm_clk_release+0x24/0x3c
[ 194.323578] dr_node_release+0x1c/0x28
[ 194.327466] release_nodes+0x5c/0x90
[ 194.331147] devres_release_all+0x90/0x104
[ 194.335364] device_unbind_cleanup+0x2c/0x84
[ 194.339762] device_release_driver_internal+0x200/0x23c
[ 194.345153] driver_detach+0x4c/0x94
[ 194.348835] bus_remove_driver+0x6c/0xbc
[ 194.352872] driver_unregister+0x30/0x60
[ 194.356914] platform_driver_unregister+0x14/0x20
[ 194.361753] ctcu_driver_exit+0x18/0xdf8 [coresight_ctcu]
[ 194.367308] __arm64_sys_delete_module+0x1bc/0x298
[ 194.372240] invoke_syscall+0x54/0x10c
[ 194.376114] el0_svc_common.constprop.0+0xc0/0xe0
[ 194.380956] do_el0_svc+0x1c/0x28
[ 194.384374] el0_svc+0x54/0x3a0
[ 194.387626] el0t_64_sync_handler+0xa0/0xe4
[ 194.391951] el0t_64_sync+0x198/0x19c
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Jie Gan (2):
coresight: Fix clock refcount imbalance on platform remove
coresight: tnoc: Fix clock refcount imbalance on platform remove
drivers/hwtracing/coresight/coresight-catu.c | 1 +
drivers/hwtracing/coresight/coresight-cpu-debug.c | 1 +
drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 +
drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
drivers/hwtracing/coresight/coresight-funnel.c | 1 +
drivers/hwtracing/coresight/coresight-replicator.c | 1 +
drivers/hwtracing/coresight/coresight-stm.c | 1 +
drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
drivers/hwtracing/coresight/coresight-tnoc.c | 1 +
drivers/hwtracing/coresight/coresight-tpiu.c | 1 +
10 files changed, 10 insertions(+)
---
base-commit: be5c93fa674f0fc3c8f359c2143abce6bbb422e6
change-id: 20260701-fix-clock-refcount-unbalance-e7c467136a86
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove 2026-07-01 6:05 [PATCH 0/2] fix clock refcount imbalance for all Coresight platform drivers Jie Gan @ 2026-07-01 6:05 ` Jie Gan 2026-07-01 9:20 ` Yeoreum Yun 2026-07-01 16:23 ` Leo Yan 2026-07-01 6:05 ` [PATCH 2/2] coresight: tnoc: " Jie Gan 1 sibling, 2 replies; 5+ messages in thread From: Jie Gan @ 2026-07-01 6:05 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan, Alexander Shishkin, Anshuman Khandual, Yeoreum Yun, Yuanfang Zhang, Maxime Coquelin, Alexandre Torgue, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, linux-stm32, Jie Gan coresight_get_enable_clocks() enables the programming clock and the optional AT clock through devm_clk_get_optional_enabled(), which also registers a devm action to call clk_disable_unprepare() when the driver detaches. After probe, pm_runtime_put() allows the device to suspend and the runtime suspend callback disables the same clocks. During remove the device is left runtime suspended, so pm_runtime_disable() freezes it with the clocks already disabled. The devm cleanup that runs afterwards calls clk_disable_unprepare() a second time, underflowing the clock enable refcount. Resume the device with pm_runtime_get_sync() before pm_runtime_disable() so the clocks are enabled again and balance the devm-managed disable. This affects all CoreSight platform drivers that obtain their clocks through coresight_get_enable_clocks(): catu, cpu-debug, ctcu, etm4x, funnel, replicator, stm, tmc and tpiu. Fixes: 1abc1b212eff ("coresight: Appropriately disable programming clocks") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 1 + drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + 9 files changed, 9 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index ad8dafea7d2f..f7e501e6cbd7 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -647,6 +647,7 @@ static void catu_platform_remove(struct platform_device *pdev) return; __catu_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 3a806c1d50ea..f7efae5b5ce5 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -711,6 +711,7 @@ static void debug_platform_remove(struct platform_device *pdev) return; __debug_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index 9043cad42f01..9b6da29d9735 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -266,6 +266,7 @@ static void ctcu_platform_remove(struct platform_device *pdev) return; ctcu_remove(pdev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 14bb31bd6a0b..147761024c0f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2416,6 +2416,7 @@ static void etm4_remove_platform_dev(struct platform_device *pdev) if (drvdata) etm4_remove_dev(drvdata); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 0abc11f0690c..4c5b94640e6a 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -334,6 +334,7 @@ static void funnel_platform_remove(struct platform_device *pdev) return; funnel_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 2f382de357ee..2d765f1f73b3 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -313,6 +313,7 @@ static void replicator_platform_remove(struct platform_device *pdev) return; replicator_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 4e860519a73f..a653f1eebeca 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -1026,6 +1026,7 @@ static void stm_platform_remove(struct platform_device *pdev) return; __stm_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index bc5a133ada3e..c9cf486873e2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -989,6 +989,7 @@ static void tmc_platform_remove(struct platform_device *pdev) return; __tmc_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 7b029d2eb389..72ac93749be1 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -286,6 +286,7 @@ static void tpiu_platform_remove(struct platform_device *pdev) return; __tpiu_remove(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove 2026-07-01 6:05 ` [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan @ 2026-07-01 9:20 ` Yeoreum Yun 2026-07-01 16:23 ` Leo Yan 1 sibling, 0 replies; 5+ messages in thread From: Yeoreum Yun @ 2026-07-01 9:20 UTC (permalink / raw) To: Jie Gan Cc: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan, Alexander Shishkin, Anshuman Khandual, Yuanfang Zhang, Maxime Coquelin, Alexandre Torgue, Tingwei Zhang, coresight, linux-arm-kernel, linux-kernel, linux-stm32 Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com> On Wed, Jul 01, 2026 at 02:05:02PM +0800, Jie Gan wrote: > coresight_get_enable_clocks() enables the programming clock and the > optional AT clock through devm_clk_get_optional_enabled(), which also > registers a devm action to call clk_disable_unprepare() when the driver > detaches. > > After probe, pm_runtime_put() allows the device to suspend and the > runtime suspend callback disables the same clocks. During remove the > device is left runtime suspended, so pm_runtime_disable() freezes it > with the clocks already disabled. The devm cleanup that runs afterwards > calls clk_disable_unprepare() a second time, underflowing the clock > enable refcount. > > Resume the device with pm_runtime_get_sync() before pm_runtime_disable() > so the clocks are enabled again and balance the devm-managed disable. > > This affects all CoreSight platform drivers that obtain their clocks > through coresight_get_enable_clocks(): catu, cpu-debug, ctcu, etm4x, > funnel, replicator, stm, tmc and tpiu. > > Fixes: 1abc1b212eff ("coresight: Appropriately disable programming clocks") > Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-catu.c | 1 + > drivers/hwtracing/coresight/coresight-cpu-debug.c | 1 + > drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + > drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + > drivers/hwtracing/coresight/coresight-funnel.c | 1 + > drivers/hwtracing/coresight/coresight-replicator.c | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 1 + > drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + > drivers/hwtracing/coresight/coresight-tpiu.c | 1 + > 9 files changed, 9 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c > index ad8dafea7d2f..f7e501e6cbd7 100644 > --- a/drivers/hwtracing/coresight/coresight-catu.c > +++ b/drivers/hwtracing/coresight/coresight-catu.c > @@ -647,6 +647,7 @@ static void catu_platform_remove(struct platform_device *pdev) > return; > > __catu_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c > index 3a806c1d50ea..f7efae5b5ce5 100644 > --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c > +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c > @@ -711,6 +711,7 @@ static void debug_platform_remove(struct platform_device *pdev) > return; > > __debug_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index 9043cad42f01..9b6da29d9735 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -266,6 +266,7 @@ static void ctcu_platform_remove(struct platform_device *pdev) > return; > > ctcu_remove(pdev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 14bb31bd6a0b..147761024c0f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -2416,6 +2416,7 @@ static void etm4_remove_platform_dev(struct platform_device *pdev) > > if (drvdata) > etm4_remove_dev(drvdata); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c > index 0abc11f0690c..4c5b94640e6a 100644 > --- a/drivers/hwtracing/coresight/coresight-funnel.c > +++ b/drivers/hwtracing/coresight/coresight-funnel.c > @@ -334,6 +334,7 @@ static void funnel_platform_remove(struct platform_device *pdev) > return; > > funnel_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c > index 2f382de357ee..2d765f1f73b3 100644 > --- a/drivers/hwtracing/coresight/coresight-replicator.c > +++ b/drivers/hwtracing/coresight/coresight-replicator.c > @@ -313,6 +313,7 @@ static void replicator_platform_remove(struct platform_device *pdev) > return; > > replicator_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index 4e860519a73f..a653f1eebeca 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -1026,6 +1026,7 @@ static void stm_platform_remove(struct platform_device *pdev) > return; > > __stm_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index bc5a133ada3e..c9cf486873e2 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -989,6 +989,7 @@ static void tmc_platform_remove(struct platform_device *pdev) > return; > > __tmc_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c > index 7b029d2eb389..72ac93749be1 100644 > --- a/drivers/hwtracing/coresight/coresight-tpiu.c > +++ b/drivers/hwtracing/coresight/coresight-tpiu.c > @@ -286,6 +286,7 @@ static void tpiu_platform_remove(struct platform_device *pdev) > return; > > __tpiu_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); > } > > > -- > 2.34.1 > -- Sincerely, Yeoreum Yun ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove 2026-07-01 6:05 ` [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan 2026-07-01 9:20 ` Yeoreum Yun @ 2026-07-01 16:23 ` Leo Yan 1 sibling, 0 replies; 5+ messages in thread From: Leo Yan @ 2026-07-01 16:23 UTC (permalink / raw) To: Jie Gan Cc: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Anshuman Khandual, Yeoreum Yun, Yuanfang Zhang, Maxime Coquelin, Alexandre Torgue, Tingwei Zhang, coresight, linux-arm-kernel, linux-kernel, linux-stm32 On Wed, Jul 01, 2026 at 02:05:02PM +0800, Jie Gan wrote: > After probe, pm_runtime_put() allows the device to suspend and the > runtime suspend callback disables the same clocks. During remove the > device is left runtime suspended, so pm_runtime_disable() freezes it > with the clocks already disabled. The devm cleanup that runs afterwards > calls clk_disable_unprepare() a second time, underflowing the clock > enable refcount. Thanks for fixing the issue. The problem is that if the device has already been runtime suspended and its clock has been disabled, afterwards when remove the device, the devm cleanup disables the clock again, resulting in clock count underflow. > diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c > index 0abc11f0690c..4c5b94640e6a 100644 > --- a/drivers/hwtracing/coresight/coresight-funnel.c > +++ b/drivers/hwtracing/coresight/coresight-funnel.c > @@ -334,6 +334,7 @@ static void funnel_platform_remove(struct platform_device *pdev) > return; > > funnel_remove(&pdev->dev); > + pm_runtime_get_sync(&pdev->dev); > pm_runtime_disable(&pdev->dev); Let's use the funnel driver for the discussion. Once we agree on the approach, we can apply the same change to the other CoreSight platform drivers. How about the following teardown? static void funnel_platform_remove(struct platform_device *pdev) { struct funnel_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + int ret; if (WARN_ON(!drvdata)) return; + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) + dev_warn(&pdev->dev, "failed to resume before remove: %d\n", ret); + funnel_remove(&pdev->dev); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); } The idea is to first resume the device with pm_runtime_get_sync(), then perform the remove (which is safe if they need to access or clean up hardware state), and finally clean up the runtime PM states. I mainly referred to drivers/iio/adc/stm32-adc.c. Thanks, Leo ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] coresight: tnoc: Fix clock refcount imbalance on platform remove 2026-07-01 6:05 [PATCH 0/2] fix clock refcount imbalance for all Coresight platform drivers Jie Gan 2026-07-01 6:05 ` [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan @ 2026-07-01 6:05 ` Jie Gan 1 sibling, 0 replies; 5+ messages in thread From: Jie Gan @ 2026-07-01 6:05 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan, Alexander Shishkin, Anshuman Khandual, Yeoreum Yun, Yuanfang Zhang, Maxime Coquelin, Alexandre Torgue, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, linux-stm32, Jie Gan coresight_get_enable_clocks() enables the programming clock through devm_clk_get_optional_enabled(), which also registers a devm action to call clk_disable_unprepare() when the driver detaches. After probe, pm_runtime_put() allows the device to suspend and the runtime suspend callback disables the same clock. During remove the device is left runtime suspended, so pm_runtime_disable() freezes it with the clock already disabled. The devm cleanup that runs afterwards calls clk_disable_unprepare() a second time, underflowing the clock enable refcount. Resume the device with pm_runtime_get_sync() before pm_runtime_disable() so the clock is enabled again and balances the devm-managed disable. Fixes: 5799dee92dc2 ("coresight-tnoc: add platform driver to support Interconnect TNOC") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- drivers/hwtracing/coresight/coresight-tnoc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index 9e8de4323d28..a4ac0eb02248 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -300,6 +300,7 @@ static void itnoc_remove(struct platform_device *pdev) struct trace_noc_drvdata *drvdata = platform_get_drvdata(pdev); coresight_unregister(drvdata->csdev); + pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-07-01 16:23 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-01 6:05 [PATCH 0/2] fix clock refcount imbalance for all Coresight platform drivers Jie Gan 2026-07-01 6:05 ` [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan 2026-07-01 9:20 ` Yeoreum Yun 2026-07-01 16:23 ` Leo Yan 2026-07-01 6:05 ` [PATCH 2/2] coresight: tnoc: " Jie Gan
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox