* [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe Gen3 stability
@ 2026-07-06 7:03 hongxing.zhu
2026-07-06 16:00 ` Frank Li
0 siblings, 1 reply; 3+ messages in thread
From: hongxing.zhu @ 2026-07-06 7:03 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel, Richard Zhu
From: Richard Zhu <hongxing.zhu@nxp.com>
Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
the default MPLLB_BINDWIDTH value. This margin degradation worsens
across voltage and temperature (VT) variations and different test
matrices, potentially causing link stability issues.
Testing with MPLLB_BINDWIDTH value of 140 (0x8c) shows significant
improvement in bandwidth margins across all VT conditions and test
scenarios.
Implement PHY register write helper function and configure:
- MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
- MPLLB_BW_OVRD_EN to enable the override
This ensures robust PCIe Gen3 performance across all operating
conditions.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 31 +++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6924a06bde305..023145b0dd2c7 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -80,6 +80,15 @@
#define IMX95_SID_MASK GENMASK(5, 0)
#define IMX95_MAX_LUT 32
+#define IMX95_PCIE_PHY_REG_ADDR 0x3008
+#define IMX95_PCIE_PHY_REG_EN BIT(31)
+#define IMX95_PCIE_PHY_REG_ADDR_MASK GENMASK(15, 0)
+#define IMX95_PCIE_PHY_REG_DATA 0x300c
+#define IMX95_PCIE_PHY_MPLLB_OVRD_IN 0x2004
+#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN 0x400
+#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN 0x2005
+#define IMX95_PCIE_PHY_MPLLB_BW 0x8c
+
#define IMX95_PCIE_RST_CTRL 0x3010
#define IMX95_PCIE_COLD_RST BIT(0)
@@ -269,6 +278,20 @@ static int imx95_pcie_select_ref_clk_src(struct imx_pcie *imx_pcie)
return 0;
}
+static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_PHY_CR_PARA_SEL,
+ IMX95_PCIE_PHY_CR_PARA_SEL);
+
+ fsleep(200);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
+ IMX95_PCIE_PHY_REG_EN, IMX95_PCIE_PHY_REG_EN);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
+ IMX95_PCIE_PHY_REG_ADDR_MASK, addr);
+ regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA, data);
+}
+
static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
/*
@@ -284,10 +307,10 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
IMX95_PCIE_SYS_AUX_PWR_DET);
- regmap_update_bits(imx_pcie->iomuxc_gpr,
- IMX95_PCIE_SS_RW_REG_0,
- IMX95_PCIE_PHY_CR_PARA_SEL,
- IMX95_PCIE_PHY_CR_PARA_SEL);
+ imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN,
+ IMX95_PCIE_PHY_MPLLB_BW);
+ imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN,
+ IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe Gen3 stability
2026-07-06 7:03 [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe Gen3 stability hongxing.zhu
@ 2026-07-06 16:00 ` Frank Li
2026-07-07 3:12 ` Hongxing Zhu (OSS)
0 siblings, 1 reply; 3+ messages in thread
From: Frank Li @ 2026-07-06 16:00 UTC (permalink / raw)
To: hongxing.zhu
Cc: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
s.hauer, kernel, festevam, linux-pci, linux-arm-kernel, imx,
linux-kernel, Richard Zhu
On Mon, Jul 06, 2026 at 03:03:40PM +0800, hongxing.zhu@oss.nxp.com wrote:
> From: Richard Zhu <hongxing.zhu@nxp.com>
subject:
PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
>
> Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
> the default MPLLB_BINDWIDTH value. This margin degradation worsens
> across voltage and temperature (VT) variations and different test
> matrices, potentially causing link stability issues.
>
> Testing with MPLLB_BINDWIDTH value of 140 (0x8c) shows significant
> improvement in bandwidth margins across all VT conditions and test
> scenarios.
>
> Implement PHY register write helper function and configure:
> - MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
> - MPLLB_BW_OVRD_EN to enable the override
>
> This ensures robust PCIe Gen3 performance across all operating
> conditions.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 31 +++++++++++++++++++++++----
> 1 file changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 6924a06bde305..023145b0dd2c7 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -80,6 +80,15 @@
> #define IMX95_SID_MASK GENMASK(5, 0)
> #define IMX95_MAX_LUT 32
>
> +#define IMX95_PCIE_PHY_REG_ADDR 0x3008
> +#define IMX95_PCIE_PHY_REG_EN BIT(31)
> +#define IMX95_PCIE_PHY_REG_ADDR_MASK GENMASK(15, 0)
> +#define IMX95_PCIE_PHY_REG_DATA 0x300c
> +#define IMX95_PCIE_PHY_MPLLB_OVRD_IN 0x2004
> +#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN 0x400
Not sure how spec descript it. but BW_OVRD_EN is bit of OVRD_IN register
look like IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN is more clean to avoid confuse
it is a bit of register BW_OVRD_IN.
> +#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN 0x2005
> +#define IMX95_PCIE_PHY_MPLLB_BW 0x8c
> +
> #define IMX95_PCIE_RST_CTRL 0x3010
> #define IMX95_PCIE_COLD_RST BIT(0)
>
> @@ -269,6 +278,20 @@ static int imx95_pcie_select_ref_clk_src(struct imx_pcie *imx_pcie)
> return 0;
> }
>
> +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> + IMX95_PCIE_PHY_CR_PARA_SEL,
> + IMX95_PCIE_PHY_CR_PARA_SEL);
> +
> + fsleep(200);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
> + IMX95_PCIE_PHY_REG_EN, IMX95_PCIE_PHY_REG_EN);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
> + IMX95_PCIE_PHY_REG_ADDR_MASK, addr);
> + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA, data);
> +}
> +
> static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> /*
> @@ -284,10 +307,10 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> IMX95_PCIE_SYS_AUX_PWR_DET);
>
> - regmap_update_bits(imx_pcie->iomuxc_gpr,
> - IMX95_PCIE_SS_RW_REG_0,
> - IMX95_PCIE_PHY_CR_PARA_SEL,
> - IMX95_PCIE_PHY_CR_PARA_SEL);
why need remove this part?
Frank
> + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN,
> + IMX95_PCIE_PHY_MPLLB_BW);
> + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN,
> + IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN);
>
> return 0;
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe Gen3 stability
2026-07-06 16:00 ` Frank Li
@ 2026-07-07 3:12 ` Hongxing Zhu (OSS)
0 siblings, 0 replies; 3+ messages in thread
From: Hongxing Zhu (OSS) @ 2026-07-07 3:12 UTC (permalink / raw)
To: Frank Li (OSS), Hongxing Zhu (OSS)
Cc: Frank Li, l.stach@pengutronix.de, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
bhelgaas@google.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-kernel@vger.kernel.org, Hongxing Zhu
> -----Original Message-----
> From: Frank Li (OSS) <frank.li@oss.nxp.com>
> Sent: Tuesday, July 7, 2026 12:00 AM
> To: Hongxing Zhu (OSS) <hongxing.zhu@oss.nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> robh@kernel.org; bhelgaas@google.com; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; linux-
> kernel@vger.kernel.org; Hongxing Zhu <hongxing.zhu@nxp.com>
> Subject: Re: [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe
> Gen3 stability
>
> On Mon, Jul 06, 2026 at 03:03:40PM +0800, hongxing.zhu@oss.nxp.com
> wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
>
> subject:
> PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
>
> >
> > Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
> > the default MPLLB_BINDWIDTH value. This margin degradation worsens
> > across voltage and temperature (VT) variations and different test
> > matrices, potentially causing link stability issues.
> >
> > Testing with MPLLB_BINDWIDTH value of 140 (0x8c) shows significant
> > improvement in bandwidth margins across all VT conditions and test
> > scenarios.
> >
> > Implement PHY register write helper function and configure:
> > - MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
> > - MPLLB_BW_OVRD_EN to enable the override
> >
> > This ensures robust PCIe Gen3 performance across all operating
> > conditions.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 31
> > +++++++++++++++++++++++----
> > 1 file changed, 27 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 6924a06bde305..023145b0dd2c7 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -80,6 +80,15 @@
> > #define IMX95_SID_MASK GENMASK(5, 0)
> > #define IMX95_MAX_LUT 32
> >
> > +#define IMX95_PCIE_PHY_REG_ADDR 0x3008
> > +#define IMX95_PCIE_PHY_REG_EN BIT(31)
> > +#define IMX95_PCIE_PHY_REG_ADDR_MASK
> GENMASK(15, 0)
> > +#define IMX95_PCIE_PHY_REG_DATA 0x300c
> > +#define IMX95_PCIE_PHY_MPLLB_OVRD_IN 0x2004
> > +#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN 0x400
>
> Not sure how spec descript it. but BW_OVRD_EN is bit of OVRD_IN register
>
> look like IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN is more clean to avoid
> confuse it is a bit of register BW_OVRD_IN.
>
> > +#define IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN 0x2005
> > +#define IMX95_PCIE_PHY_MPLLB_BW 0x8c
> > +
> > #define IMX95_PCIE_RST_CTRL 0x3010
> > #define IMX95_PCIE_COLD_RST BIT(0)
> >
> > @@ -269,6 +278,20 @@ static int imx95_pcie_select_ref_clk_src(struct
> imx_pcie *imx_pcie)
> > return 0;
> > }
> >
> > +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr,
> > +u16 data) {
> > + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
> > + IMX95_PCIE_PHY_CR_PARA_SEL,
> > + IMX95_PCIE_PHY_CR_PARA_SEL);
> > +
> > + fsleep(200);
> > + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_REG_ADDR,
> > + IMX95_PCIE_PHY_REG_EN,
> IMX95_PCIE_PHY_REG_EN);
> > + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_REG_ADDR,
> > + IMX95_PCIE_PHY_REG_ADDR_MASK, addr);
> > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA,
> data); }
> > +
> > static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) {
> > /*
> > @@ -284,10 +307,10 @@ static int imx95_pcie_init_phy(struct imx_pcie
> *imx_pcie)
> > regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> > IMX95_PCIE_SYS_AUX_PWR_DET);
> >
> > - regmap_update_bits(imx_pcie->iomuxc_gpr,
> > - IMX95_PCIE_SS_RW_REG_0,
> > - IMX95_PCIE_PHY_CR_PARA_SEL,
> > - IMX95_PCIE_PHY_CR_PARA_SEL);
>
> why need remove this part?
>
It's a part of PHY RW routine.
Move it into imx95_pcie_phy_write() above.
I can discard this change if you want to keep it separate.
Best Regards
Richard Zhu
> Frank
>
> > + imx95_pcie_phy_write(imx_pcie,
> IMX95_PCIE_PHY_MPLLB_BW_OVRD_IN,
> > + IMX95_PCIE_PHY_MPLLB_BW);
> > + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN,
> > + IMX95_PCIE_PHY_MPLLB_BW_OVRD_EN);
> >
> > return 0;
> > }
> > --
> > 2.34.1
> >
> >
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-07-06 7:03 [PATCH v1] PCI: imx6: Update MPLLB bandwidth for i.MX95 PCIe Gen3 stability hongxing.zhu
2026-07-06 16:00 ` Frank Li
2026-07-07 3:12 ` Hongxing Zhu (OSS)
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