From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: <iommu@lists.linux.dev>, "Joerg Roedel (AMD)" <joro@8bytes.org>,
Jean-Philippe Brucker <jpb@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>,
David Matlack <dmatlack@google.com>,
"Pasha Tatashin" <pasha.tatashin@soleen.com>,
<patches@lists.linux.dev>,
"Pranjal Shrivastava" <praan@google.com>,
Samiullah Khawaja <skhawaja@google.com>,
Mostafa Saleh <smostafa@google.com>
Subject: Re: [PATCH v3 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain
Date: Tue, 14 Jul 2026 14:29:20 -0700 [thread overview]
Message-ID: <alaqMJnkplAuT9kT@nvidia.com> (raw)
In-Reply-To: <6-v3-4e7f64f4e094+85e-smmu_tlbi_jgg@nvidia.com>
On Tue, Jul 14, 2026 at 03:46:06PM -0300, Jason Gunthorpe wrote:
> +/*
> + * Called by io-pgtable-arm.c for each single table level it wants to remove.
> + * size is the size of the table level and granule is the tg in bytes. This must
> + * clear the walk cache and any leaves within the range.
> + */
> static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size,
> size_t granule, void *cookie)
> {
> struct arm_smmu_domain *smmu_domain = cookie;
> + struct arm_smmu_tlbi tlbi = {
> + .tgsz_lg2 = smmu_domain->tgsz_lg2,
> + .iova = iova,
> + .size = size,
> + .iopte_size = smmu_domain->tgsz_lg2,
Sashiko reported a typo here, though this gets fixed in patch-7.
Nicolin
next prev parent reply other threads:[~2026-07-14 21:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-14 18:46 [PATCH v3 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-14 18:46 ` [PATCH v3 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-14 18:46 ` [PATCH v3 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-14 18:46 ` [PATCH v3 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-14 18:46 ` [PATCH v3 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-14 18:46 ` [PATCH v3 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-14 21:42 ` Nicolin Chen
2026-07-14 18:46 ` [PATCH v3 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-14 21:29 ` Nicolin Chen [this message]
2026-07-14 18:46 ` [PATCH v3 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-14 23:09 ` Nicolin Chen
2026-07-14 18:46 ` [PATCH v3 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-15 1:45 ` [PATCH v3 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Nicolin Chen
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