* [PATCH 2/4 v2] irqchip: refactor Gemini driver to reflect Faraday origin
2017-03-18 16:53 [PATCH 1/4 v2] irqchip: augment Gemini bindings to reflect Faraday origin Linus Walleij
@ 2017-03-18 16:53 ` Linus Walleij
2017-03-18 16:53 ` [PATCH 3/4 v2] irqchip: faraday: fix the trigger types Linus Walleij
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2017-03-18 16:53 UTC (permalink / raw)
To: linux-arm-kernel
The Gemini irqchip turns out to be a standard IP component from
Faraday Technology named FTINTC010 after some research and new
information.
- Rename the driver and all symbols to reflect the new information.
- Add the new compatible string "faraday,ftintc010"
- Create a Kconfig symbol CONFIG_FARADAY_FTINTC010 so that SoCs
using this interrupt controller can easily select and reuse it
instead of hardwiring it to ARCH_GEMINI
I have created a separate patch to select the new Kconfig symbol
from the Gemini machine, which will be merged through the ARM
SoC tree.
Cc: Greentime Hu <green.hu@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Fix Paulius email address.
---
drivers/irqchip/Kconfig | 6 ++
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-ftintc010.c | 187 ++++++++++++++++++++++++++++++++++++++++
drivers/irqchip/irq-gemini.c | 185 ---------------------------------------
4 files changed, 194 insertions(+), 186 deletions(-)
create mode 100644 drivers/irqchip/irq-ftintc010.c
delete mode 100644 drivers/irqchip/irq-gemini.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 125528f39e92..6afa9e01e610 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -115,6 +115,12 @@ config DW_APB_ICTL
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
+config FARADAY_FTINTC010
+ bool
+ select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
+ select SPARSE_IRQ
+
config HISILICON_IRQ_MBIGEN
bool
select ARM_GIC_V3
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 152bc40b6762..cdf3474d3851 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
-obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o
+obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
diff --git a/drivers/irqchip/irq-ftintc010.c b/drivers/irqchip/irq-ftintc010.c
new file mode 100644
index 000000000000..81929aa33990
--- /dev/null
+++ b/drivers/irqchip/irq-ftintc010.c
@@ -0,0 +1,187 @@
+/*
+ * irqchip for the Faraday Technology FTINTC010 Copyright (C) 2017 Linus
+ * Walleij <linus.walleij@linaro.org>
+ *
+ * Based on arch/arm/mach-gemini/irq.c
+ * Copyright (C) 2001-2006 Storlink, Corp.
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
+ */
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/versatile-fpga.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#define FT010_NUM_IRQS 32
+
+#define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00)
+#define FT010_IRQ_MASK(base_addr) (base_addr + 0x04)
+#define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08)
+#define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C)
+#define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10)
+#define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14)
+#define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20)
+#define FT010_FIQ_MASK(base_addr) (base_addr + 0x24)
+#define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28)
+#define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C)
+#define FT010_FIQ_POLARITY(base_addr) (base_addr + 0x30)
+#define FT010_FIQ_STATUS(base_addr) (base_addr + 0x34)
+
+/**
+ * struct ft010_irq_data - irq data container for the Faraday IRQ controller
+ * @base: memory offset in virtual memory
+ * @chip: chip container for this instance
+ * @domain: IRQ domain for this instance
+ */
+struct ft010_irq_data {
+ void __iomem *base;
+ struct irq_chip chip;
+ struct irq_domain *domain;
+};
+
+static void ft010_irq_mask(struct irq_data *d)
+{
+ struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
+ unsigned int mask;
+
+ mask = readl(FT010_IRQ_MASK(f->base));
+ mask &= ~BIT(irqd_to_hwirq(d));
+ writel(mask, FT010_IRQ_MASK(f->base));
+}
+
+static void ft010_irq_unmask(struct irq_data *d)
+{
+ struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
+ unsigned int mask;
+
+ mask = readl(FT010_IRQ_MASK(f->base));
+ mask |= BIT(irqd_to_hwirq(d));
+ writel(mask, FT010_IRQ_MASK(f->base));
+}
+
+static void ft010_irq_ack(struct irq_data *d)
+{
+ struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
+
+ writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
+}
+
+static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger)
+{
+ struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
+ int offset = irqd_to_hwirq(d);
+ u32 mode, polarity;
+
+ mode = readl(FT010_IRQ_MODE(f->base));
+ polarity = readl(FT010_IRQ_POLARITY(f->base));
+
+ if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
+ irq_set_handler_locked(d, handle_level_irq);
+ /* Disable edge detection */
+ mode &= ~BIT(offset);
+ polarity &= ~BIT(offset);
+ } else if (trigger & IRQ_TYPE_EDGE_RISING) {
+ irq_set_handler_locked(d, handle_edge_irq);
+ mode |= BIT(offset);
+ polarity |= BIT(offset);
+ } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
+ irq_set_handler_locked(d, handle_edge_irq);
+ mode |= BIT(offset);
+ polarity &= ~BIT(offset);
+ } else {
+ irq_set_handler_locked(d, handle_bad_irq);
+ pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
+ offset);
+ }
+
+ writel(mode, FT010_IRQ_MODE(f->base));
+ writel(polarity, FT010_IRQ_POLARITY(f->base));
+
+ return 0;
+}
+
+static struct irq_chip ft010_irq_chip = {
+ .name = "FTINTC010",
+ .irq_ack = ft010_irq_ack,
+ .irq_mask = ft010_irq_mask,
+ .irq_unmask = ft010_irq_unmask,
+ .irq_set_type = ft010_irq_set_type,
+};
+
+/* Local static for the IRQ entry call */
+static struct ft010_irq_data firq;
+
+asmlinkage void __exception_irq_entry ft010_irqchip_handle_irq(struct pt_regs *regs)
+{
+ struct ft010_irq_data *f = &firq;
+ int irq;
+ u32 status;
+
+ while ((status = readl(FT010_IRQ_STATUS(f->base)))) {
+ irq = ffs(status) - 1;
+ handle_domain_irq(f->domain, irq, regs);
+ }
+}
+
+static int ft010_irqdomain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct ft010_irq_data *f = d->host_data;
+
+ irq_set_chip_data(irq, f);
+ /* All IRQs should set up their type, flags as bad by default */
+ irq_set_chip_and_handler(irq, &ft010_irq_chip, handle_bad_irq);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static void ft010_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ irq_set_chip_and_handler(irq, NULL, NULL);
+ irq_set_chip_data(irq, NULL);
+}
+
+static const struct irq_domain_ops ft010_irqdomain_ops = {
+ .map = ft010_irqdomain_map,
+ .unmap = ft010_irqdomain_unmap,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+int __init ft010_of_init_irq(struct device_node *node,
+ struct device_node *parent)
+{
+ struct ft010_irq_data *f = &firq;
+
+ /*
+ * Disable the idle handler by default since it is buggy
+ * For more info see arch/arm/mach-gemini/idle.c
+ */
+ cpu_idle_poll_ctrl(true);
+
+ f->base = of_iomap(node, 0);
+ WARN(!f->base, "unable to map gemini irq registers\n");
+
+ /* Disable all interrupts */
+ writel(0, FT010_IRQ_MASK(f->base));
+ writel(0, FT010_FIQ_MASK(f->base));
+
+ f->domain = irq_domain_add_simple(node, FT010_NUM_IRQS, 0,
+ &ft010_irqdomain_ops, f);
+ set_handle_irq(ft010_irqchip_handle_irq);
+
+ return 0;
+}
+IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
+ ft010_of_init_irq);
+IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
+ ft010_of_init_irq);
diff --git a/drivers/irqchip/irq-gemini.c b/drivers/irqchip/irq-gemini.c
deleted file mode 100644
index 495224c743ee..000000000000
--- a/drivers/irqchip/irq-gemini.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * irqchip for the Cortina Systems Gemini Copyright (C) 2017 Linus
- * Walleij <linus.walleij@linaro.org>
- *
- * Based on arch/arm/mach-gemini/irq.c
- * Copyright (C) 2001-2006 Storlink, Corp.
- * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- */
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/irqchip.h>
-#include <linux/irqchip/versatile-fpga.h>
-#include <linux/irqdomain.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/cpu.h>
-
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-
-#define GEMINI_NUM_IRQS 32
-
-#define GEMINI_IRQ_SOURCE(base_addr) (base_addr + 0x00)
-#define GEMINI_IRQ_MASK(base_addr) (base_addr + 0x04)
-#define GEMINI_IRQ_CLEAR(base_addr) (base_addr + 0x08)
-#define GEMINI_IRQ_MODE(base_addr) (base_addr + 0x0C)
-#define GEMINI_IRQ_POLARITY(base_addr) (base_addr + 0x10)
-#define GEMINI_IRQ_STATUS(base_addr) (base_addr + 0x14)
-#define GEMINI_FIQ_SOURCE(base_addr) (base_addr + 0x20)
-#define GEMINI_FIQ_MASK(base_addr) (base_addr + 0x24)
-#define GEMINI_FIQ_CLEAR(base_addr) (base_addr + 0x28)
-#define GEMINI_FIQ_MODE(base_addr) (base_addr + 0x2C)
-#define GEMINI_FIQ_POLARITY(base_addr) (base_addr + 0x30)
-#define GEMINI_FIQ_STATUS(base_addr) (base_addr + 0x34)
-
-/**
- * struct gemini_irq_data - irq data container for the Gemini IRQ controller
- * @base: memory offset in virtual memory
- * @chip: chip container for this instance
- * @domain: IRQ domain for this instance
- */
-struct gemini_irq_data {
- void __iomem *base;
- struct irq_chip chip;
- struct irq_domain *domain;
-};
-
-static void gemini_irq_mask(struct irq_data *d)
-{
- struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
- unsigned int mask;
-
- mask = readl(GEMINI_IRQ_MASK(g->base));
- mask &= ~BIT(irqd_to_hwirq(d));
- writel(mask, GEMINI_IRQ_MASK(g->base));
-}
-
-static void gemini_irq_unmask(struct irq_data *d)
-{
- struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
- unsigned int mask;
-
- mask = readl(GEMINI_IRQ_MASK(g->base));
- mask |= BIT(irqd_to_hwirq(d));
- writel(mask, GEMINI_IRQ_MASK(g->base));
-}
-
-static void gemini_irq_ack(struct irq_data *d)
-{
- struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
-
- writel(BIT(irqd_to_hwirq(d)), GEMINI_IRQ_CLEAR(g->base));
-}
-
-static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger)
-{
- struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
- int offset = irqd_to_hwirq(d);
- u32 mode, polarity;
-
- mode = readl(GEMINI_IRQ_MODE(g->base));
- polarity = readl(GEMINI_IRQ_POLARITY(g->base));
-
- if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
- irq_set_handler_locked(d, handle_level_irq);
- /* Disable edge detection */
- mode &= ~BIT(offset);
- polarity &= ~BIT(offset);
- } else if (trigger & IRQ_TYPE_EDGE_RISING) {
- irq_set_handler_locked(d, handle_edge_irq);
- mode |= BIT(offset);
- polarity |= BIT(offset);
- } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
- irq_set_handler_locked(d, handle_edge_irq);
- mode |= BIT(offset);
- polarity &= ~BIT(offset);
- } else {
- irq_set_handler_locked(d, handle_bad_irq);
- pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
- offset);
- }
-
- writel(mode, GEMINI_IRQ_MODE(g->base));
- writel(polarity, GEMINI_IRQ_POLARITY(g->base));
-
- return 0;
-}
-
-static struct irq_chip gemini_irq_chip = {
- .name = "GEMINI",
- .irq_ack = gemini_irq_ack,
- .irq_mask = gemini_irq_mask,
- .irq_unmask = gemini_irq_unmask,
- .irq_set_type = gemini_irq_set_type,
-};
-
-/* Local static for the IRQ entry call */
-static struct gemini_irq_data girq;
-
-asmlinkage void __exception_irq_entry gemini_irqchip_handle_irq(struct pt_regs *regs)
-{
- struct gemini_irq_data *g = &girq;
- int irq;
- u32 status;
-
- while ((status = readl(GEMINI_IRQ_STATUS(g->base)))) {
- irq = ffs(status) - 1;
- handle_domain_irq(g->domain, irq, regs);
- }
-}
-
-static int gemini_irqdomain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- struct gemini_irq_data *g = d->host_data;
-
- irq_set_chip_data(irq, g);
- /* All IRQs should set up their type, flags as bad by default */
- irq_set_chip_and_handler(irq, &gemini_irq_chip, handle_bad_irq);
- irq_set_probe(irq);
-
- return 0;
-}
-
-static void gemini_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
-{
- irq_set_chip_and_handler(irq, NULL, NULL);
- irq_set_chip_data(irq, NULL);
-}
-
-static const struct irq_domain_ops gemini_irqdomain_ops = {
- .map = gemini_irqdomain_map,
- .unmap = gemini_irqdomain_unmap,
- .xlate = irq_domain_xlate_onetwocell,
-};
-
-int __init gemini_of_init_irq(struct device_node *node,
- struct device_node *parent)
-{
- struct gemini_irq_data *g = &girq;
-
- /*
- * Disable the idle handler by default since it is buggy
- * For more info see arch/arm/mach-gemini/idle.c
- */
- cpu_idle_poll_ctrl(true);
-
- g->base = of_iomap(node, 0);
- WARN(!g->base, "unable to map gemini irq registers\n");
-
- /* Disable all interrupts */
- writel(0, GEMINI_IRQ_MASK(g->base));
- writel(0, GEMINI_FIQ_MASK(g->base));
-
- g->domain = irq_domain_add_simple(node, GEMINI_NUM_IRQS, 0,
- &gemini_irqdomain_ops, g);
- set_handle_irq(gemini_irqchip_handle_irq);
-
- return 0;
-}
-IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
- gemini_of_init_irq);
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4 v2] irqchip: replace moxa with ftintc010
2017-03-18 16:53 [PATCH 1/4 v2] irqchip: augment Gemini bindings to reflect Faraday origin Linus Walleij
2017-03-18 16:53 ` [PATCH 2/4 v2] irqchip: refactor Gemini driver " Linus Walleij
2017-03-18 16:53 ` [PATCH 3/4 v2] irqchip: faraday: fix the trigger types Linus Walleij
@ 2017-03-18 16:53 ` Linus Walleij
2017-03-19 10:21 ` [PATCH 1/4 v2] irqchip: augment Gemini bindings to reflect Faraday origin Hans Ulli Kroll
2017-03-24 9:29 ` Marc Zyngier
4 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2017-03-18 16:53 UTC (permalink / raw)
To: linux-arm-kernel
The Moxa Art interrupt controller is very very likely just an instance
of the Faraday FTINTC010 interrupt controller from Faraday Technology.
An indication would be its close association with the FA526 ARM core
and the fact that the register layout is the same.
The implementation in irq-moxart.c can probably be right off replaced
with the irq-ftintc010.c driver by adding a compatible string, selecting
this irqchip from the machine and run.
As a bonus we have an irqchip driver supporting high/low and
rising/falling edges for the Moxa Art, and shared code with the Gemini
platform.
Acked-by: Olof Johansson <olof@lixom.net>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- No longer a RFT patch, Jonas has successfully tested this on
the Moxart board.
- Add Olof's ACK so it can be applied to the irqchip tree.
---
arch/arm/mach-moxart/Kconfig | 2 +-
drivers/irqchip/Makefile | 1 -
drivers/irqchip/irq-ftintc010.c | 2 +
drivers/irqchip/irq-moxart.c | 116 ----------------------------------------
4 files changed, 3 insertions(+), 118 deletions(-)
delete mode 100644 drivers/irqchip/irq-moxart.c
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index f69e28b85e88..70db2abf6163 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -3,8 +3,8 @@ menuconfig ARCH_MOXART
depends on ARCH_MULTI_V4
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
+ select FARADAY_FTINTC010
select MOXART_TIMER
- select GENERIC_IRQ_CHIP
select GPIOLIB
select PHYLIB if NETDEVICES
help
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cdf3474d3851..d80bc3e9d511 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
-obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
diff --git a/drivers/irqchip/irq-ftintc010.c b/drivers/irqchip/irq-ftintc010.c
index 0cc81df6f743..cd2dc8bbbe9c 100644
--- a/drivers/irqchip/irq-ftintc010.c
+++ b/drivers/irqchip/irq-ftintc010.c
@@ -190,3 +190,5 @@ IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
ft010_of_init_irq);
IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
ft010_of_init_irq);
+IRQCHIP_DECLARE(moxa, "moxa,moxart-ic",
+ ft010_of_init_irq);
diff --git a/drivers/irqchip/irq-moxart.c b/drivers/irqchip/irq-moxart.c
deleted file mode 100644
index a24b06a1718b..000000000000
--- a/drivers/irqchip/irq-moxart.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * MOXA ART SoCs IRQ chip driver.
- *
- * Copyright (C) 2013 Jonas Jensen
- *
- * Jonas Jensen <jonas.jensen@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-
-#include <asm/exception.h>
-
-#define IRQ_SOURCE_REG 0
-#define IRQ_MASK_REG 0x04
-#define IRQ_CLEAR_REG 0x08
-#define IRQ_MODE_REG 0x0c
-#define IRQ_LEVEL_REG 0x10
-#define IRQ_STATUS_REG 0x14
-
-#define FIQ_SOURCE_REG 0x20
-#define FIQ_MASK_REG 0x24
-#define FIQ_CLEAR_REG 0x28
-#define FIQ_MODE_REG 0x2c
-#define FIQ_LEVEL_REG 0x30
-#define FIQ_STATUS_REG 0x34
-
-
-struct moxart_irq_data {
- void __iomem *base;
- struct irq_domain *domain;
- unsigned int interrupt_mask;
-};
-
-static struct moxart_irq_data intc;
-
-static void __exception_irq_entry handle_irq(struct pt_regs *regs)
-{
- u32 irqstat;
- int hwirq;
-
- irqstat = readl(intc.base + IRQ_STATUS_REG);
-
- while (irqstat) {
- hwirq = ffs(irqstat) - 1;
- handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
- irqstat &= ~(1 << hwirq);
- }
-}
-
-static int __init moxart_of_intc_init(struct device_node *node,
- struct device_node *parent)
-{
- unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
- int ret;
- struct irq_chip_generic *gc;
-
- intc.base = of_iomap(node, 0);
- if (!intc.base) {
- pr_err("%s: unable to map IC registers\n",
- node->full_name);
- return -EINVAL;
- }
-
- intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
- intc.base);
- if (!intc.domain) {
- pr_err("%s: unable to create IRQ domain\n", node->full_name);
- return -EINVAL;
- }
-
- ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1,
- "MOXARTINTC", handle_edge_irq,
- clr, 0, IRQ_GC_INIT_MASK_CACHE);
- if (ret) {
- pr_err("%s: could not allocate generic chip\n",
- node->full_name);
- irq_domain_remove(intc.domain);
- return -EINVAL;
- }
-
- ret = of_property_read_u32(node, "interrupt-mask",
- &intc.interrupt_mask);
- if (ret)
- pr_err("%s: could not read interrupt-mask DT property\n",
- node->full_name);
-
- gc = irq_get_domain_generic_chip(intc.domain, 0);
-
- gc->reg_base = intc.base;
- gc->chip_types[0].regs.mask = IRQ_MASK_REG;
- gc->chip_types[0].regs.ack = IRQ_CLEAR_REG;
- gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
- gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
- gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
-
- writel(0, intc.base + IRQ_MASK_REG);
- writel(0xffffffff, intc.base + IRQ_CLEAR_REG);
-
- writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG);
- writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG);
-
- set_handle_irq(handle_irq);
-
- return 0;
-}
-IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-ic", moxart_of_intc_init);
--
2.9.3
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