Re: [PATCH v3 3/6] arm64: cpufeature: Extend bbml2_noabort support list

[Mark Rutland <mark.rutland@arm.com>]

On Thu, Jul 16, 2026 at 10:00:40AM +1000, Gavin Shan wrote:
> On 7/15/26 3:34 PM, Linu Cherian wrote:
> > C1-Ultra and C1-Premium both suffer from erratum 3683289,
> > where Break-Before-Make must be followed to avoid a livelock.
> > For both CPUs, the erratum is fixed from r1p1.
> > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.

> > @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void)
> >   		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> > +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_PRO),
> > +		/* Erratum 3683289 fixed in r1p1 */
> > +		MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
> > +		MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),
> 
> The revisions for C1_ULTRA and C1_PREMIUM have been limited to
> r1p1 to r1p15. How about r2p0 and the revisions after that? We
> probably won't get a chance to hit the ceiling? :-)

Yes, those should be:

	MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf),
	MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf),

In general, MIDR_REV_RANGE() doesn't make much sense and should be
removed. I have a patch for that hidden in some other MIDR cleanup, so
I'll go revive that shortly...

Mark.