From: Mark Rutland <mark.rutland@arm.com>
To: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: ryan.roberts@arm.com, usama.anjum@arm.com, peterz@infradead.org,
catalin.marinas@arm.com, david.laight.linux@gmail.com,
stable@vger.kernel.org, ruanjinjie@huawei.com,
james.morse@arm.com, yang@os.amperecomputing.com, cl@gentwo.org,
maz@kernel.org, david@kernel.org, ljs@kernel.org,
will@kernel.org, ardb@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 05/21] arm64: cmpxchg128: LSE: Remove redundant operands
Date: Fri, 11 Sep 2026 12:43:15 +0100 [thread overview]
Message-ID: <aqPpU2fHtK4CXOc6@J2N7QTR9R3> (raw)
In-Reply-To: <1b0a435e-68c1-46c2-8fc0-310694728772@arm.com>
On Thu, Sep 10, 2026 at 11:06:48AM +0100, Vladimir Murzin wrote:
> On 9/8/26 16:17, Mark Rutland wrote:
> > @@ -291,15 +291,13 @@ __lse__cmpxchg128##name(volatile u128 *ptr, u128 old, u128 new) \
> > register unsigned long x1 asm ("x1") = o.high; \
> > register unsigned long x2 asm ("x2") = n.low; \
> > register unsigned long x3 asm ("x3") = n.high; \
> > - register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
> > \
> > asm volatile( \
> > __LSE_PREAMBLE \
> > " casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
> > : [old1] "+&r" (x0), [old2] "+&r" (x1), \
> > [v] "+Q" (*(u128 *)ptr) \
> > - : [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
> > - [oldval1] "r" (o.low), [oldval2] "r" (o.high) \
>
> Both 'old1' and #old are read and write and that reflected by '+' constraint modifier.
> However, I do not fully understand why we need earlyclobber for them:
> - they are not written before read
> - we already constrained registers, so they do not overlap
> - cmpxchg few lines above doesn't need it
I agree that the earlyclobber shouldn't be necessary for 'old1' or
'old2'. I expect it shouldn't have a negative effect on code generation
here, as removing it doesn't give the compiler any new freedom to
allocate registers differently, but maybe it causes the compiler to do a
bit more work internally.
I'll leave this patch as-is for now, but I am happy to delete the
earlyclobber in a subsequent patch (or to ack a patch doing so), if
people want?
> I had a look at ll/sc counterpart and both earlyclobebr and '=' constraint modifier
> make sense there, since we do not want registers to overlap and they are written.
>
> I admit might be missing something. Anyway, FWIW
I don't think you're missing anything here. I suspect we just
copy-pasted the LL/SC constraints without thinking too hard when this
was added in commit:
b23e139d0b66c021 ("arch: Introduce arch_{,try_}_cmpxchg128{,_local}()")
> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Thanks!
Mark.
>
> > + : [new1] "r" (x2), [new2] "r" (x3) \
> > : cl); \
> > \
> > r.low = x0; r.high = x1; \
> > -- 2.30.2
> >
>
next prev parent reply other threads:[~2026-09-11 11:43 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 15:17 [PATCH v4 00/21] Preemptible this_cpu_*() operations Mark Rutland
2026-09-08 15:17 ` [PATCH v4 01/21] arm64: percpu: Fix this_cpu_write() casting Mark Rutland
2026-09-10 10:56 ` Lorenzo Stoakes (ARM)
2026-09-08 15:17 ` [PATCH v4 02/21] arm64: percpu: Fix this_cpu_and() mask generation Mark Rutland
2026-09-08 15:17 ` [PATCH v4 03/21] arm64: percpu: Fix LSE operations on {8,16}-bit types Mark Rutland
2026-09-10 15:18 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 04/21] arm64: cmpxchg: LL/SC: Avoid redundant extension Mark Rutland
2026-09-08 15:17 ` [PATCH v4 05/21] arm64: cmpxchg128: LSE: Remove redundant operands Mark Rutland
2026-09-10 10:06 ` Vladimir Murzin
2026-09-11 11:43 ` Mark Rutland [this message]
2026-09-08 15:17 ` [PATCH v4 06/21] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test() Mark Rutland
2026-09-08 15:17 ` [PATCH v4 07/21] arm64: preempt: Treat should_resched() as unlikely Mark Rutland
2026-09-08 15:17 ` [PATCH v4 08/21] arm64: ptrace: Always inline pt_regs_[read,write}_reg() Mark Rutland
2026-09-11 10:20 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 09/21] arm64: percpu: Factor out percpu offset asm Mark Rutland
2026-09-11 12:39 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 10/21] arm64: gpr-num: Add wxN aliases for wN registers Mark Rutland
2026-09-11 12:43 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 11/21] arm64: gpr-num: add __GPR_NUM() helper Mark Rutland
2026-09-10 14:24 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 12/21] arm64: entry: sdei: Restore all clobberable GPRs Mark Rutland
2026-09-11 12:47 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 13/21] arm64: entry: sdei: Make 'tsk' available Mark Rutland
2026-09-10 13:06 ` Vladimir Murzin
2026-09-08 15:17 ` [PATCH v4 14/21] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 15/21] arm64: percpu: Implement preemptible read/write ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 16/21] arm64: percpu: Implement preemptible void RMW ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 17/21] arm64: percpu: Implement preemptible return " Mark Rutland
2026-09-08 15:17 ` [PATCH v4 18/21] arm64: percpu: Implement preemptible XCHG ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 19/21] arm64: percpu: Implement preemptible CMPXCHG ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 20/21] arm64: percpu: Implement preemptible CMPXCHG128 ops Mark Rutland
2026-09-08 15:17 ` [PATCH v4 21/21] arm64: percpu: Remove _pcp_protect*() wrappers Mark Rutland
2026-09-11 13:44 ` [PATCH v4 00/21] Preemptible this_cpu_*() operations Will Deacon
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