[PATCH v2 0/2] arm64: Add KVM support for newer Apple Silicon CPUs

[PATCH v2 0/2] arm64: Add KVM support for newer Apple Silicon CPUs

[Michael Reeves via B4 Relay]

Hi,

This series enables KVM support on Apple Silicon M3 (base, Pro and Max),
base M4, A18 Pro and M5 Pro CPUs.

The first patch adds the CPU part numbers and MIDR definitions.

The second patch adds these CPUs to the existing Apple Silicon PMU and
broken SEIS workarounds. It also enables TDIR detection so KVM can trap
guest DIR accesses without trapping all common registers.

This series was developed from testing on:
- Apple M3 and M3 Pro by Michael Reeves
- Apple M3 Max by Myria Sarvay and Yureka Lilian
- Apple M4, A18 Pro and M5 Pro by Yureka Lilian

These tests also confirmed that the SEIS workaround is still needed.

---
Changes in v2:
- Add A18 Pro and M5 CPU IDs and workaround coverage.
- Add all to has_vgic_v3 for TDIR detection
- Document testing confirming SEIS workaround still needed
- Link to v1:
  https://patch.msgid.link/20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com

---
Michael Reeves (1):
      arm64: Apply existing Apple Silicon CPU workarounds to newer CPUs

Myria Sarvay (1):
      arm64: Add CPU part numbers for newer Apple Silicon CPUs

 arch/arm64/include/asm/cputype.h | 28 ++++++++++++++++++++++++++++
 arch/arm64/kernel/cpu_errata.c   | 12 ++++++++++++
 arch/arm64/kernel/cpufeature.c   | 12 ++++++++++++
 3 files changed, 52 insertions(+)
---
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
change-id: 20261008-apple-m3-m4-kvm-b7b9b2e34bcd

Best regards,
--  
Michael Reeves <michael.reeves077@gmail.com>

[PATCH v2 1/2] arm64: Add CPU part numbers for newer Apple Silicon CPUs

[Michael Reeves via B4 Relay]

From: Myria Sarvay <myrialsarvay@gmail.com>

Add CPU part numbers and MIDR definitions for M3, M3 Pro, M3 Max,
base M4, A18 Pro and M5 Pro so CPU workarounds can identify these cores.

Use the SoC codenames for M4, A18 Pro and M5 Pro, with suffixes for
their core types, as separate core codenames are not known.

Signed-off-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/include/asm/cputype.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 1fa29616e..86adfebcb 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -155,6 +155,18 @@
 #define APPLE_CPU_PART_M2_AVALANCHE_PRO	0x035
 #define APPLE_CPU_PART_M2_BLIZZARD_MAX	0x038
 #define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039
+#define APPLE_CPU_PART_M3_SAWTOOTH	0x042
+#define APPLE_CPU_PART_M3_EVEREST	0x043
+#define APPLE_CPU_PART_M3_SAWTOOTH_PRO	0x044
+#define APPLE_CPU_PART_M3_EVEREST_PRO	0x045
+#define APPLE_CPU_PART_M3_SAWTOOTH_MAX	0x048
+#define APPLE_CPU_PART_M3_EVEREST_MAX	0x049
+#define APPLE_CPU_PART_M4_DONAN_ECORE	0x052
+#define APPLE_CPU_PART_M4_DONAN_PCORE	0x053
+#define APPLE_CPU_PART_A18_PRO_TAHITI_ECORE	0x060
+#define APPLE_CPU_PART_A18_PRO_TAHITI_PCORE	0x061
+#define APPLE_CPU_PART_M5_PRO_SOTRA_MCORE	0x064
+#define APPLE_CPU_PART_M5_PRO_SOTRA_PCORE	0x065
 
 #define AMPERE_CPU_PART_AMPERE1		0xAC3
 #define AMPERE_CPU_PART_AMPERE1A	0xAC4
@@ -250,6 +262,22 @@
 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
+#define MIDR_APPLE_M3_SAWTOOTH MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH)
+#define MIDR_APPLE_M3_EVEREST MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST)
+#define MIDR_APPLE_M3_SAWTOOTH_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_PRO)
+#define MIDR_APPLE_M3_EVEREST_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_PRO)
+#define MIDR_APPLE_M3_SAWTOOTH_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_MAX)
+#define MIDR_APPLE_M3_EVEREST_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_MAX)
+#define MIDR_APPLE_M4_DONAN_ECORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_ECORE)
+#define MIDR_APPLE_M4_DONAN_PCORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_PCORE)
+#define MIDR_APPLE_A18_PRO_TAHITI_ECORE \
+	MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A18_PRO_TAHITI_ECORE)
+#define MIDR_APPLE_A18_PRO_TAHITI_PCORE \
+	MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A18_PRO_TAHITI_PCORE)
+#define MIDR_APPLE_M5_PRO_SOTRA_MCORE \
+	MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M5_PRO_SOTRA_MCORE)
+#define MIDR_APPLE_M5_PRO_SOTRA_PCORE \
+	MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M5_PRO_SOTRA_PCORE)
 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 #define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

-- 
2.56.0

[PATCH v2 2/2] arm64: Apply existing Apple Silicon CPU workarounds to newer CPUs

[Michael Reeves via B4 Relay]

From: Michael Reeves <michael.reeves077@gmail.com>

Add M3, M3 Pro, M3 Max, base M4, A18 Pro and M5 Pro to apple_cpus
so they receive the existing PMU trap and broken SEIS workarounds.

Add these CPUs to has_vgic_v3 so KVM detects TDIR support and can
trap guest DIR accesses without trapping all common registers.

Co-developed-by: Yureka Lilian <yureka@cyberchaos.dev>
Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/kernel/cpu_errata.c | 12 ++++++++++++
 arch/arm64/kernel/cpufeature.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e0c094025..bc91bc13b 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -288,6 +288,18 @@ static const struct midr_range apple_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_A18_PRO_TAHITI_ECORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_A18_PRO_TAHITI_PCORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M5_PRO_SOTRA_MCORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M5_PRO_SOTRA_PCORE),
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3ae3ad1a1..bb82b80b3 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2357,6 +2357,18 @@ static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry,
 		MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
 		MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
 		MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_A18_PRO_TAHITI_ECORE),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_A18_PRO_TAHITI_PCORE),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M5_PRO_SOTRA_MCORE),
+		MIDR_ALL_VERSIONS(MIDR_APPLE_M5_PRO_SOTRA_PCORE),
 		{},
 	};
 	struct arm_smccc_res res = {};

-- 
2.56.0

Re: [PATCH v2 1/2] arm64: Add CPU part numbers for newer Apple Silicon CPUs

[Catalin Marinas]

On Wed, Oct 21, 2026 at 10:53:20AM +1100, Michael Reeves via B4 Relay wrote:
> From: Myria Sarvay <myrialsarvay@gmail.com>
> 
> Add CPU part numbers and MIDR definitions for M3, M3 Pro, M3 Max,
> base M4, A18 Pro and M5 Pro so CPU workarounds can identify these cores.
> 
> Use the SoC codenames for M4, A18 Pro and M5 Pro, with suffixes for
> their core types, as separate core codenames are not known.
> 
> Signed-off-by: Myria Sarvay <myrialsarvay@gmail.com>
> Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Re: [PATCH v2 2/2] arm64: Apply existing Apple Silicon CPU workarounds to newer CPUs

[Catalin Marinas]

On Wed, Oct 21, 2026 at 10:53:21AM +1100, Michael Reeves via B4 Relay wrote:
> From: Michael Reeves <michael.reeves077@gmail.com>
> 
> Add M3, M3 Pro, M3 Max, base M4, A18 Pro and M5 Pro to apple_cpus
> so they receive the existing PMU trap and broken SEIS workarounds.
> 
> Add these CPUs to has_vgic_v3 so KVM detects TDIR support and can
> trap guest DIR accesses without trapping all common registers.
> 
> Co-developed-by: Yureka Lilian <yureka@cyberchaos.dev>
> Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
> Tested-by: Yureka Lilian <yureka@cyberchaos.dev>
> Tested-by: Myria Sarvay <myrialsarvay@gmail.com>
> Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>