[PATCH 0/3] nvmem: mtk-efuse: mt6572 support

[PATCH 0/3] nvmem: mtk-efuse: mt6572 support

[Roman Vivchar via B4 Relay]

This patch series adds MediaTek mt6572 efuse support. Unlike newer SoCs,
its efuse controller doesn't work properly with 8-bit reads, leading to
invalid data with current mtk-efuse driver implementation.

This behavior can be observed with devmem (0x10009174 and 0x10009178 are
thermal calibration cells):
~ # devmem 0x10009174 32
0x00CDD4CD
~ # devmem 0x10009178 32
0x0F76865D
~ # devmem 0x10009174 8
0xCD
~ # devmem 0x10009175 8
0x00
~ # devmem 0x10009176 8
0x00
~ # devmem 0x10009177 8
0x00
~ # devmem 0x10009178 8
0x5D
~ # devmem 0x10009179 8
0x00
~ # devmem 0x1000917a 8
0x00
~ # devmem 0x1000917b 8
0x00

Patch 1 adds dt-bindings compatible for the mt6572,
Patch 2 adds platform data option to use aligned 32-bit reads instead
of plain readb().
Patch 3 adds platform data for mt6572 SoC.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Roman Vivchar (3):
      dt-bindings: nvmem: mediatek: efuse: add mt6572
      nvmem: mtk-efuse: add support for 32-bit aligned reads
      nvmem: mtk-efuse: add mt6572 support

 .../devicetree/bindings/nvmem/mediatek,efuse.yaml  |  1 +
 drivers/nvmem/mtk-efuse.c                          | 37 ++++++++++++++++++++--
 2 files changed, 35 insertions(+), 3 deletions(-)
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260710-6572-nvmem-eb98c7a73351

Best regards,
--  
Roman Vivchar <rva333@protonmail.com>

[PATCH 1/3] dt-bindings: nvmem: mediatek: efuse: add mt6572

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

Add a compatible string for the mt6572 SoC efuse controller.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
index f9323b3ecfc8..269e2b09f5c8 100644
--- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
@@ -44,6 +44,7 @@ properties:
 
       - items:
           - enum:
+              - mediatek,mt6572-efuse
               - mediatek,mt7622-efuse
               - mediatek,mt7623-efuse
               - mediatek,mt7981-efuse

-- 
2.54.0

Re: [PATCH 1/3] dt-bindings: nvmem: mediatek: efuse: add mt6572

[AngeloGioacchino Del Regno]

On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> Add a compatible string for the mt6572 SoC efuse controller.
> 

Please, avoid adding this to the list of compatibles that need you do specify

"mediatek,mt6572-efuse", "mediatek,efuse";

The "generic" compatible should disappear.. and plus, the MT6572 SoC seems to
be pretty special, as you had to implement aligned read just for that.

This won't be the only SoC as well, as probably all of the legacy one from the
same era will be affected... so please, add it as a const so that you can have
a devicetree with an efuse node declaring

compatible = "mediatek,mt6572-efuse";

Cheers,
Angelo

> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
>   Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> index f9323b3ecfc8..269e2b09f5c8 100644
> --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> @@ -44,6 +44,7 @@ properties:
>   
>         - items:
>             - enum:
> +              - mediatek,mt6572-efuse
>                 - mediatek,mt7622-efuse
>                 - mediatek,mt7623-efuse
>                 - mediatek,mt7981-efuse
> 

[PATCH 2/3] nvmem: mtk-efuse: add support for 32-bit aligned reads

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

Some MediaTek SoCs, such as mt6572, don't support 8-bit reads, leading
to zeroes or garbage data. 32-bit aligned reads must be used instead.

Introduce an 'needs_aligned_read' field to the platform data to enforce
32-bit aligned register access. All reads will be performed by reading
4-byte words and masking them.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 drivers/nvmem/mtk-efuse.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
index af953e1d9230..1462f2760818 100644
--- a/drivers/nvmem/mtk-efuse.c
+++ b/drivers/nvmem/mtk-efuse.c
@@ -4,6 +4,7 @@
  * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
  */
 
+#include <linux/align.h>
 #include <linux/device.h>
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
@@ -14,10 +15,12 @@
 
 struct mtk_efuse_pdata {
 	bool uses_post_processing;
+	bool needs_aligned_read;
 };
 
 struct mtk_efuse_priv {
 	void __iomem *base;
+	const struct mtk_efuse_pdata *data;
 };
 
 static int mtk_reg_read(void *context,
@@ -28,6 +31,26 @@ static int mtk_reg_read(void *context,
 	u8 *val = _val;
 	int i;
 
+	if (priv->data->needs_aligned_read) {
+		u32 pos, shift, val32;
+
+		for (i = 0; i < bytes; i++, val++) {
+			pos = reg + i;
+
+			/*
+			 * Read on 32-bit word boundary or if it's the first
+			 * iteration
+			 */
+			if (i == 0 || IS_ALIGNED(pos, 4))
+				val32 = readl(priv->base + (pos & ~3));
+
+			shift = (pos & 3) * 8;
+			*val = (val32 >> shift) & 0xff;
+		}
+
+		return 0;
+	}
+
 	for (i = 0; i < bytes; i++, val++)
 		*val = readb(addr + i);
 
@@ -67,7 +90,6 @@ static int mtk_efuse_probe(struct platform_device *pdev)
 	struct nvmem_device *nvmem;
 	struct nvmem_config econfig = {};
 	struct mtk_efuse_priv *priv;
-	const struct mtk_efuse_pdata *pdata;
 	struct platform_device *socinfo;
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -78,7 +100,8 @@ static int mtk_efuse_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
 
-	pdata = device_get_match_data(dev);
+	priv->data = device_get_match_data(dev);
+
 	econfig.add_legacy_fixed_of_cells = true;
 	econfig.stride = 1;
 	econfig.word_size = 1;
@@ -86,7 +109,7 @@ static int mtk_efuse_probe(struct platform_device *pdev)
 	econfig.size = resource_size(res);
 	econfig.priv = priv;
 	econfig.dev = dev;
-	if (pdata->uses_post_processing)
+	if (priv->data->uses_post_processing)
 		econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
 	nvmem = devm_nvmem_register(dev, &econfig);
 	if (IS_ERR(nvmem))
@@ -103,10 +126,12 @@ static int mtk_efuse_probe(struct platform_device *pdev)
 
 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
 	.uses_post_processing = true,
+	.needs_aligned_read = false,
 };
 
 static const struct mtk_efuse_pdata mtk_efuse_pdata = {
 	.uses_post_processing = false,
+	.needs_aligned_read = false,
 };
 
 static const struct of_device_id mtk_efuse_of_match[] = {

-- 
2.54.0

Re: [PATCH 2/3] nvmem: mtk-efuse: add support for 32-bit aligned reads

[AngeloGioacchino Del Regno]

On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> Some MediaTek SoCs, such as mt6572, don't support 8-bit reads, leading
> to zeroes or garbage data. 32-bit aligned reads must be used instead.
> 
> Introduce an 'needs_aligned_read' field to the platform data to enforce
> 32-bit aligned register access. All reads will be performed by reading
> 4-byte words and masking them.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>

You're effectively overriding the entire mtk_reg_read function when
needs_aligned_read==true... so.... (check below)

> ---
>   drivers/nvmem/mtk-efuse.c | 31 ++++++++++++++++++++++++++++---
>   1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> index af953e1d9230..1462f2760818 100644
> --- a/drivers/nvmem/mtk-efuse.c
> +++ b/drivers/nvmem/mtk-efuse.c
> @@ -4,6 +4,7 @@
>    * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
>    */
>   
> +#include <linux/align.h>
>   #include <linux/device.h>
>   #include <linux/module.h>
>   #include <linux/mod_devicetable.h>
> @@ -14,10 +15,12 @@
>   
>   struct mtk_efuse_pdata {
>   	bool uses_post_processing;
> +	bool needs_aligned_read;
>   };
>   
>   struct mtk_efuse_priv {
>   	void __iomem *base;
> +	const struct mtk_efuse_pdata *data;

...instead of adding pdata here...

>   };
>   
>   static int mtk_reg_read(void *context,
> @@ -28,6 +31,26 @@ static int mtk_reg_read(void *context,
>   	u8 *val = _val;
>   	int i;
>   
> +	if (priv->data->needs_aligned_read) {
> +		u32 pos, shift, val32;
> +
> +		for (i = 0; i < bytes; i++, val++) {
> +			pos = reg + i;
> +
> +			/*
> +			 * Read on 32-bit word boundary or if it's the first
> +			 * iteration
> +			 */
> +			if (i == 0 || IS_ALIGNED(pos, 4))
> +				val32 = readl(priv->base + (pos & ~3));
> +
> +			shift = (pos & 3) * 8;
> +			*val = (val32 >> shift) & 0xff;
> +		}
> +
> +		return 0;
> +	}
> +
>   	for (i = 0; i < bytes; i++, val++)
>   		*val = readb(addr + i);
>   
> @@ -67,7 +90,6 @@ static int mtk_efuse_probe(struct platform_device *pdev)
>   	struct nvmem_device *nvmem;
>   	struct nvmem_config econfig = {};
>   	struct mtk_efuse_priv *priv;
> -	const struct mtk_efuse_pdata *pdata;
>   	struct platform_device *socinfo;
>   
>   	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> @@ -78,7 +100,8 @@ static int mtk_efuse_probe(struct platform_device *pdev)
>   	if (IS_ERR(priv->base))
>   		return PTR_ERR(priv->base);
>   
> -	pdata = device_get_match_data(dev);
> +	priv->data = device_get_match_data(dev);
> +

...and instead of changing a bunch of lines here...

>   	econfig.add_legacy_fixed_of_cells = true;
>   	econfig.stride = 1;
>   	econfig.word_size = 1;

it's easier at this point if you simply do

	if (pdata->needs_aligned_read) {
		econfig.stride = 4;
		econfig.reg_read = mtk_reg_read_aligned;
	} else {
		econfig.stride = 1;
		econfig.reg_read = mtk_reg_read;
	}

and you avoid touching mtk_reg_read entirely.

Though it's not going to be used in any performance path, that's also faster as
there's one less branch per execution.

Cheers,
Angelo

Re: [PATCH 2/3] nvmem: mtk-efuse: add support for 32-bit aligned reads

[Roman Vivchar]

On Monday, July 20th, 2026 at 3:48 PM, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:

> On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:

...
 
> it's easier at this point if you simply do
> 
> 	if (pdata->needs_aligned_read) {
> 		econfig.stride = 4;
> 		econfig.reg_read = mtk_reg_read_aligned;
> 	} else {
> 		econfig.stride = 1;
> 		econfig.reg_read = mtk_reg_read;
> 	}
> 
> and you avoid touching mtk_reg_read entirely.

stride = 4 means we can't do something like reg = <0x1 0x1>;
For example, CPU speedbin is sitting at 0x181, but we can model that as
0x180.
cpu_speedbin: cpu-speedbin@180 {
    /* This is technically reg = <0x181 0x1> and bits = <0 2> */
    reg = <0x180 0x4>;
    bits = <8 2>;
};

I'm not sure what are mediatek preferences in the devicetree since
things change quite frequently... Downstream never triggers this hw bug
because it uses readl everywhere for each efuse.

I would keep the stride = 1 so we don't need workarounds in the DT, but
the reg_read indeed sounds better :)

Let me know if you have any objections.

Best regards,
Roman

[PATCH 3/3] nvmem: mtk-efuse: add mt6572 support

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

Add a platform data struct for the efuse controller.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 drivers/nvmem/mtk-efuse.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
index 1462f2760818..a79434608465 100644
--- a/drivers/nvmem/mtk-efuse.c
+++ b/drivers/nvmem/mtk-efuse.c
@@ -124,6 +124,11 @@ static int mtk_efuse_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct mtk_efuse_pdata mtk_mt6572_efuse_pdata = {
+	.uses_post_processing = false,
+	.needs_aligned_read = true,
+};
+
 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
 	.uses_post_processing = true,
 	.needs_aligned_read = false,
@@ -135,6 +140,7 @@ static const struct mtk_efuse_pdata mtk_efuse_pdata = {
 };
 
 static const struct of_device_id mtk_efuse_of_match[] = {
+	{ .compatible = "mediatek,mt6572-efuse", .data = &mtk_mt6572_efuse_pdata },
 	{ .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
 	{ .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
 	{ .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },

-- 
2.54.0

Re: [PATCH 3/3] nvmem: mtk-efuse: add mt6572 support

[AngeloGioacchino Del Regno]

On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> Add a platform data struct for the efuse controller.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
>   drivers/nvmem/mtk-efuse.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> index 1462f2760818..a79434608465 100644
> --- a/drivers/nvmem/mtk-efuse.c
> +++ b/drivers/nvmem/mtk-efuse.c
> @@ -124,6 +124,11 @@ static int mtk_efuse_probe(struct platform_device *pdev)
>   	return 0;
>   }
>   
> +static const struct mtk_efuse_pdata mtk_mt6572_efuse_pdata = {
> +	.uses_post_processing = false,

Are you sure this SoC (or any other compatible with it) doesn't have any GPU speed
binning?

If you're really sure

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> +	.needs_aligned_read = true,
> +};
> +
>   static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
>   	.uses_post_processing = true,
>   	.needs_aligned_read = false,
> @@ -135,6 +140,7 @@ static const struct mtk_efuse_pdata mtk_efuse_pdata = {
>   };
>   
>   static const struct of_device_id mtk_efuse_of_match[] = {
> +	{ .compatible = "mediatek,mt6572-efuse", .data = &mtk_mt6572_efuse_pdata },
>   	{ .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
>   	{ .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
>   	{ .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
> 

Re: [PATCH 3/3] nvmem: mtk-efuse: add mt6572 support

[Roman Vivchar]

Hi Angelo,

On Monday, July 20th, 2026 at 3:48 PM, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:

> On 7/15/26 16:27, Roman Vivchar via B4 Relay wrote:
> > From: Roman Vivchar <rva333@protonmail.com>
> >
> > Add a platform data struct for the efuse controller.
> >
> > Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> > ---
> >   drivers/nvmem/mtk-efuse.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> > index 1462f2760818..a79434608465 100644
> > --- a/drivers/nvmem/mtk-efuse.c
> > +++ b/drivers/nvmem/mtk-efuse.c
> > @@ -124,6 +124,11 @@ static int mtk_efuse_probe(struct platform_device *pdev)
> >   	return 0;
> >   }
> >
> > +static const struct mtk_efuse_pdata mtk_mt6572_efuse_pdata = {
> > +	.uses_post_processing = false,
>
> Are you sure this SoC (or any other compatible with it) doesn't have any GPU speed
> binning?
>
> If you're really sure
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

It does, but we can't really rely on it. The GPU is complicated here...

Something like this:
- mfgcfg
  ^- mfg_pre ('safe' UNIVPLL div or 'unsafe' mfg mux)
     ^- mfg (if you're here and your chip is NOT mt6572w then be prepared
	         for crashes)
        ^- whpll (or any other parent, but downstream uses WHPLL as GPU
                  clock source)

There is GPU speedbin, but it means either GPU scaling is fine and mfg
mux is safe (0, unfused) or that the GPU must stay at UNIVPLL divider
(1, fused off).

My current solution is using assigned-clocks and assigned-clock-parents
in the each board which we've tested manually.
&gpu {
        /* Switch to WHPLL */
        assigned-clocks = <&topckgen CLK_TOP_MFG_SEL>,
                          <&topckgen CLK_TOP_MFG_PRE_SEL>;
        assigned-clock-parents = <&topckgen CLK_TOP_MFG_PRE_500M>,
                                 <&topckgen CLK_TOP_MFG_SEL>;

        operating-points-v2 = <&gpu_opp_table>;
        nvmem-cells = <&gpu_speedbin>;
        nvmem-cell-names = "speedbin";
		status = "okay";
};

On boards with GPU frequency fused off the entire setup is omitted
except status = "okay";

Let me know if you have some other idea how this should be handled.

Best regards,
Roman

Re: [PATCH 3/3] nvmem: mtk-efuse: add mt6572 support

[Roman Vivchar]

On Monday, July 20th, 2026 at 4:33 PM, Roman Vivchar <rva333@protonmail.com> wrote:

...
 
> Something like this:
> - mfgcfg
>   ^- mfg_pre ('safe' UNIVPLL div or 'unsafe' mfg mux)
>      ^- mfg (if you're here and your chip is NOT mt6572w then be prepared
> 	         for crashes)
>         ^- whpll (or any other parent, but downstream uses WHPLL as GPU
>                   clock source)

Oops, WHPLL sits behind the gate, so the clock tree is this:
- mfgcfg
  ^- mfg_pre ('safe' UNIVPLL div or 'unsafe' mfg mux)
     ^- mfg (if you're here and your chip is NOT mt6572w then be prepared
             for crashes)
        ^- mfg_pre_whpll_500m (or any other parent, but downstream uses
                               WHPLL as GPU clock source)
           ^- whpll

(Using 500m is a bad idea for the PLL which can change frequency, but
I have to revisit clock tree once again to make a better decision before
sending mt6572 clocks to the upstream).