* [PATCH v2 1/2] ipmi: kcs_bmc_aspeed: g6: Add KCS Channel 4 over PCIe
2026-07-22 15:11 [PATCH v2 0/2] soc: aspeed: ipmi: add KCS Channel 4 over PCIe Grégoire Layet
@ 2026-07-22 15:11 ` Grégoire Layet
2026-07-22 15:11 ` [PATCH v2 2/2] ARM: dts: aspeed-g6: add pcie-kcs4 Grégoire Layet
1 sibling, 0 replies; 3+ messages in thread
From: Grégoire Layet @ 2026-07-22 15:11 UTC (permalink / raw)
To: joel, andrew, robh, krzk+dt, conor+dt, corey, devicetree
Cc: openipmi-developer, linux-aspeed, linux-arm-kernel, linux-kernel,
Grégoire Layet
Created a 5th KCS channel to match against the KCS 4 over PCIe addresses.
The ASPEED AST2600 has a PCIe to LPC controller. It includes a KCS
interface on channel 4. This is a fully KCS-compatible interface
that is exposed over PCIe.
The 5th channel created is only valid on the AST2600.
This cannot be used for AST2400 and AST2500 chips, as they don't have LPC
over PCIE.
Signed-off-by: Grégoire Layet <gregoire.layet@9elements.com>
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 39 ++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c
index a13a3470c17a..4d93af2455b8 100644
--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
@@ -26,7 +26,7 @@
#define DEVICE_NAME "ast-kcs-bmc"
-#define KCS_CHANNEL_MAX 4
+#define KCS_CHANNEL_MAX 5
/*
* Field class descriptions
@@ -102,6 +102,12 @@
#define LPC_LSADR12_LSADR2_SHIFT 16
#define LPC_LSADR12_LSADR1_MASK GENMASK(15, 0)
#define LPC_LSADR12_LSADR1_SHIFT 0
+#define PCIE_LPC_HICRB 0x900
+#define PCIE_LPC_HICRC 0x904
+#define PCIE_LPC_LADR4 0x910
+#define PCIE_LPC_IDR4 0x914
+#define PCIE_LPC_ODR4 0x918
+#define PCIE_LPC_STR4 0x91C
#define OBE_POLL_PERIOD (HZ / 2)
@@ -191,6 +197,9 @@ static void aspeed_kcs_outb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 data)
case 4:
regmap_update_bits(priv->map, LPC_HICRC, LPC_HICRC_IRQXE4, LPC_HICRC_IRQXE4);
break;
+ case 5:
+ regmap_update_bits(priv->map, PCIE_LPC_HICRC, LPC_HICRC_IRQXE4, LPC_HICRC_IRQXE4);
+ break;
default:
break;
}
@@ -278,6 +287,14 @@ static int aspeed_kcs_set_address(struct kcs_bmc_device *kcs_bmc, u32 addrs[2],
break;
+ case 5:
+ if (nr_addrs == 1)
+ regmap_write(priv->map, PCIE_LPC_LADR4, ((addrs[0] + 1) << 16) | addrs[0]);
+ else
+ regmap_write(priv->map, PCIE_LPC_LADR4, (addrs[1] << 16) | addrs[0]);
+
+ break;
+
default:
return -EINVAL;
}
@@ -344,6 +361,11 @@ static int aspeed_kcs_config_upstream_irq(struct aspeed_kcs_bmc *priv, u32 id, u
val = (id << LPC_HICRC_ID4IRQX_SHIFT) | (hw_type << LPC_HICRC_TY4IRQX_SHIFT);
regmap_update_bits(priv->map, LPC_HICRC, mask, val);
break;
+ case 5:
+ mask = LPC_HICRC_ID4IRQX_MASK | LPC_HICRC_TY4IRQX_MASK | LPC_HICRC_OBF4_AUTO_CLR;
+ val = (id << LPC_HICRC_ID4IRQX_SHIFT) | (hw_type << LPC_HICRC_TY4IRQX_SHIFT);
+ regmap_update_bits(priv->map, PCIE_LPC_HICRC, mask, val);
+ break;
default:
dev_warn(priv->kcs_bmc.dev,
"SerIRQ configuration not supported on KCS channel %d\n",
@@ -373,6 +395,9 @@ static void aspeed_kcs_enable_channel(struct kcs_bmc_device *kcs_bmc, bool enabl
case 4:
regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_LPC4E, enable * LPC_HICRB_LPC4E);
return;
+ case 5:
+ regmap_update_bits(priv->map, PCIE_LPC_HICRB, LPC_HICRB_LPC4E, enable * LPC_HICRB_LPC4E);
+ return;
default:
pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
return;
@@ -452,6 +477,10 @@ static void aspeed_kcs_irq_mask_update(struct kcs_bmc_device *kcs_bmc, u8 mask,
regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_IBFIE4,
enable * LPC_HICRB_IBFIE4);
return;
+ case 5:
+ regmap_update_bits(priv->map, PCIE_LPC_HICRB, LPC_HICRB_IBFIE4,
+ enable * LPC_HICRB_IBFIE4);
+ return;
default:
pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
return;
@@ -492,6 +521,7 @@ static const struct kcs_ioreg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = {
{ .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 },
{ .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 },
{ .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 },
+ { .idr = PCIE_LPC_IDR4, .odr = PCIE_LPC_ODR4, .str = PCIE_LPC_STR4 },
};
static int aspeed_kcs_of_get_channel(struct platform_device *pdev)
@@ -575,11 +605,16 @@ static int aspeed_kcs_probe(struct platform_device *pdev)
if (channel < 0)
return channel;
+ np = pdev->dev.of_node;
+ if (channel == 5 && !of_device_is_compatible(np, "aspeed,ast2600-kcs-bmc")) {
+ dev_err(&pdev->dev, "LPC over PCIE KCS4 only supported on ast2600\n");
+ return -ENODEV;
+ }
+
nr_addrs = aspeed_kcs_of_get_io_address(pdev, addrs);
if (nr_addrs < 0)
return nr_addrs;
- np = pdev->dev.of_node;
rc = of_property_read_u32_array(np, "aspeed,lpc-interrupts", upstream_irq, 2);
if (rc && rc != -EINVAL)
return -EINVAL;
--
2.54.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v2 2/2] ARM: dts: aspeed-g6: add pcie-kcs4
2026-07-22 15:11 [PATCH v2 0/2] soc: aspeed: ipmi: add KCS Channel 4 over PCIe Grégoire Layet
2026-07-22 15:11 ` [PATCH v2 1/2] ipmi: kcs_bmc_aspeed: g6: Add " Grégoire Layet
@ 2026-07-22 15:11 ` Grégoire Layet
1 sibling, 0 replies; 3+ messages in thread
From: Grégoire Layet @ 2026-07-22 15:11 UTC (permalink / raw)
To: joel, andrew, robh, krzk+dt, conor+dt, corey, devicetree
Cc: openipmi-developer, linux-aspeed, linux-arm-kernel, linux-kernel,
Grégoire Layet
Add pcie_kcs4 node to the LPC bus in the ast2600 g6 common dtsi.
The ASPEED AST2600 has a PCIe to LPC controller. It includes a KCS
interface on channel 4. This is a fully KCS-compatible interface
that is exposed over PCIe.
This can be used by the host for IPMI when the PCIe BMC Device is
activated.
While the datasheet provides interrupt numbers for KCS channels 1, 2,
3 and 4 over PCI, not all 4 are described in the "PCIe to LPC Controller"
section. Since only the KCS channel 4 is described, only this channel is
added.
The pcie_kcs4 uses existing "aspeed,ast2600-kcs-bmc" compatible as it's a
standard KCS interface.
Signed-off-by: Grégoire Layet <gregoire.layet@9elements.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 56bb3b0444f7..a93fa4cf5d8f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -617,6 +617,13 @@ kcs4: kcs@114 {
status = "disabled";
};
+ pcie_kcs4: kcs@914 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ reg = <0x914 0x1>, <0x918 0x1>, <0x91c 0x1>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
lpc_ctrl: lpc-ctrl@80 {
compatible = "aspeed,ast2600-lpc-ctrl";
reg = <0x80 0x80>;
--
2.54.0
^ permalink raw reply related [flat|nested] 3+ messages in thread