* [PATCH v3 1/6] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 2/6] dt-bindings: power: Document Renesas R-Car X5H Module Controller Geert Uytterhoeven
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven, Conor Dooley
Document support for the Renesas R-Car X5H Clock Pulse Generator, and
add binding definitions for a limited initial set of clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v3:
- Add Acked-by,
v2:
- Add Reviewed-by, Tested-by,
- Drop preliminary,
- Expand CPG acronym,
- Drop R8A78000_CPG_MSOCK_PERW_BUS,
- Add R8A78000_CPG_SGASYNCD8_PERW_BUS, to avoid holes in the
SGASYNCDn_PERW_BUS sequence,
- Drop firmware property.
---
.../bindings/clock/renesas,r8a78000-cpg.yaml | 55 +++++++++++++++++++
.../dt-bindings/clock/renesas,r8a78000-cpg.h | 14 +++++
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
create mode 100644 include/dt-bindings/clock/renesas,r8a78000-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
new file mode 100644
index 0000000000000000..4e23bba334382346
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car X5H Clock Pulse Generator
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators,
+ PLL circuits, clock dividers and clock control circuits. It provides various
+ clocks for other modules.
+
+properties:
+ compatible:
+ const: renesas,r8a78000-cpg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: extal
+ - const: extalr
+
+ '#clock-cells':
+ description:
+ The single clock specifier cell must be the clock number, as defined in
+ <dt-bindings/clock/renesas,r8a78000-cpg.h>.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@c1320000 {
+ compatible = "renesas,r8a78000-cpg";
+ reg = <0xc1320000 0x10000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
new file mode 100644
index 0000000000000000..7fd09a3fb353d952
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Glider bv
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
+
+/* R-Car X5H Clock Pulse Generator Clocks */
+
+#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0
+#define R8A78000_CPG_SGASYNCD8_PERW_BUS 1
+#define R8A78000_CPG_SGASYNCD16_PERW_BUS 2
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 2/6] dt-bindings: power: Document Renesas R-Car X5H Module Controller
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 1/6] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver Geert Uytterhoeven
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven, Conor Dooley
Document support for Renesas R-Car X5H Module Controllers, and add
binding definitions for power domains not backed by registers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v3:
- Add Reviewed-by, Acked-by,
v2:
- Clarify the meaning of the two power domain cells and the reset
cell,
- Drop R8A78000_MDLC_PD_CMN, as CMN is backed by MDPG bits,
- Expand MDLC acronym,
- Add a comment stating that all R8A78000_MDLC_PD_* definitions are
for always-on power domains,
- Drop firmware property.
---
.../bindings/power/renesas,r8a78000-mdlc.yaml | 61 +++++++++++++++++++
.../dt-bindings/power/renesas,r8a78000-mdlc.h | 15 +++++
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
create mode 100644 include/dt-bindings/power/renesas,r8a78000-mdlc.h
diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
new file mode 100644
index 0000000000000000..1dba1e1b1c5b52d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/renesas,r8a78000-mdlc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car X5H Module Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provides
+ Power Gating for up to 64 Power Domains, and Module Standby and Reset for up
+ to 256 modules in the Power Domain of each Module hierarchy.
+
+properties:
+ compatible:
+ const: renesas,r8a78000-mdlc
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ description: |
+ - The first power domain specifier cell is the power domain part, and
+ must be either the Module Power Domain Gating (MPDG) register index
+ (0x00-0x3f) from the datasheet, for power domains which are backed by
+ MPDG bits and which can be controlled in that manner, or a Power
+ Domain number, as defined in
+ <dt-bindings/power/renesas,r8a78000-mdlc.h>, for power domains which
+ are always on, and for which there are no MPDG bits to control them.
+
+ - The second power domain specifier cell is the module standby part, and
+ must be the module number (0x00-0xff), composed of the Module System
+ Reset (MSRES) register index in the high nibble, and the Module Reset
+ Destination bitfield index in the low nibble.
+ const: 2
+
+ '#reset-cells':
+ description:
+ The single reset specifier cell must be the module number (0x00-0xff),
+ and thus identical to the second power domain specifier cell.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ system-controller@c3060000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0xc3060000 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/power/renesas,r8a78000-mdlc.h b/include/dt-bindings/power/renesas,r8a78000-mdlc.h
new file mode 100644
index 0000000000000000..6f3d1ae23648e55b
--- /dev/null
+++ b/include/dt-bindings/power/renesas,r8a78000-mdlc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Glider bv
+ */
+#ifndef __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
+#define __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
+
+/* R-Car X5H Module Controller Always-On Power Domains */
+
+#define R8A78000_MDLC_PD_AON 0x40
+#define R8A78000_MDLC_PD_SCP 0x41
+#define R8A78000_MDLC_PD_APL 0x42
+#define R8A78000_MDLC_PD_ACL 0x43
+
+#endif /* __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 1/6] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 2/6] dt-bindings: power: Document Renesas R-Car X5H Module Controller Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
2026-08-05 22:22 ` Marek Vasut
2026-08-05 15:20 ` [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver Geert Uytterhoeven
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven
Add a minimal Clock Pulse Generator driver for the R-Car X5H (R8A78000)
SoC. For now this supports just the few fixed-rate clocks that are
needed by the current minimal DTS.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add fixed-rate clocks to kerneldoc of r8a78000_cpg_priv.map,
- Use devm_clk_hw_register_fixed_rate(), drop unregister_fixed_clks(),
- Drop fill_clk_map(), as it is not really needed until SCMI remapping
support is added later,
- Replace <linux/mod_devicetable.h> by more specific
<linux/device-id/of.h> in v7.2-rc2,
v2:
- Spin off from "clk: renesas: Add R-Car X5H CPG SCMI remapping
driver",
- Add default support not using SCMI,
- Drop all SCMI remapping support,
- Document use of -1 as a sentinel,
- Document use of FIXED_CLK() IDs.
---
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a78000-cpg.c | 166 +++++++++++++++++++++++++++++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clk/renesas/r8a78000-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 0203ecbb38825f13..f0482bdfc4616cfa 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -34,6 +34,7 @@ config CLK_RENESAS
select CLK_R8A779F0 if ARCH_R8A779F0
select CLK_R8A779G0 if ARCH_R8A779G0
select CLK_R8A779H0 if ARCH_R8A779H0
+ select CLK_R8A78000 if ARCH_R8A78000
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G043 if ARCH_R9A07G043
select CLK_R9A07G044 if ARCH_R9A07G044
@@ -176,6 +177,9 @@ config CLK_R8A779H0
bool "R-Car V4M clock support" if COMPILE_TEST
select CLK_RCAR_GEN4_CPG
+config CLK_R8A78000
+ bool "R-Car X5H clock support" if COMPILE_TEST
+
config CLK_R9A06G032
bool "RZ/N1D clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index bd2bed91ab291d72..4f76f8c402ffe9a3 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A78000) += r8a78000-cpg.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
new file mode 100644
index 0000000000000000..7946f9d0b423def1
--- /dev/null
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car X5H Clock Pulse Generator
+ *
+ * Copyright (C) 2026 Glider bv
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/dev_printk.h>
+#include <linux/device-id/of.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
+
+struct clk_map {
+ int dt_id; /* DT binding clock ID or -1 sentinel */
+ u32 fw_id; /* FIXED_CLK() ID */
+};
+
+enum fixed_clk {
+ FIXED_CLK_66M,
+ FIXED_CLK_266M,
+ NUM_FIXED_CLKS
+};
+
+static const unsigned long fixed_clk_rates[NUM_FIXED_CLKS] = {
+ [FIXED_CLK_66M] = 66666000,
+ [FIXED_CLK_266M] = 266660000,
+};
+
+#define FIXED_CLK(rate) FIXED_CLK_ ## rate
+
+/**
+ * struct r8a78000_cpg_priv - Clock Pulse Generator Private Data
+ *
+ * @dev: CPG device
+ * @map: Mapping from DT clock IDs to fixed-rate clocks
+ * @fixed_hws: Fixed rate clocks
+ */
+struct r8a78000_cpg_priv {
+ struct device *dev;
+ const struct clk_map *map;
+ struct clk_hw *fixed_hws[NUM_FIXED_CLKS];
+};
+
+static const struct clk_map *clk_map_find(const struct clk_map *map, u32 id)
+{
+ if (!map)
+ return NULL;
+
+ for (; map->dt_id >= 0; map++) {
+ if (map->dt_id == id)
+ return map;
+ }
+
+ return NULL;
+}
+
+static struct clk_hw *r8a78000_clk_get(struct of_phandle_args *spec,
+ void *data)
+{
+ struct r8a78000_cpg_priv *priv = data;
+ struct device *dev = priv->dev;
+ const struct clk_map *map;
+ struct clk_hw *hw;
+ u32 id;
+
+ if (spec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ id = spec->args[0];
+
+ map = clk_map_find(priv->map, id);
+ if (!map) {
+ dev_err(dev, "Unknown clock %u\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+
+ dev_dbg(dev, "Mapping DT clock %u to fixed clock %u\n", id, map->fw_id);
+
+ hw = priv->fixed_hws[map->fw_id];
+
+ dev_dbg(dev, "clock %u is %s at %lu Hz\n", id, clk_hw_get_name(hw),
+ clk_hw_get_rate(hw));
+
+ return hw;
+}
+
+static int register_fixed_clks(struct r8a78000_cpg_priv *priv)
+{
+ struct device *dev = priv->dev;
+ unsigned long rate;
+ struct clk_hw *hw;
+ const char *name;
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(fixed_clk_rates); i++) {
+ rate = fixed_clk_rates[i];
+ name = devm_kasprintf(dev, GFP_KERNEL, "cpg-%lu", rate);
+ if (!name)
+ return -ENOMEM;
+
+ hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed_hws[i] = hw;
+ }
+
+ return 0;
+}
+
+static int r8a78000_cpg_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct r8a78000_cpg_priv *priv;
+ const struct clk_map *map;
+ int ret;
+
+ map = of_device_get_match_data(dev);
+ if (!map)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->map = map;
+
+ ret = register_fixed_clks(priv);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, r8a78000_clk_get, priv);
+}
+
+static const struct clk_map r8a78000_cpg_default[] = {
+ { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) },
+ { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) },
+ { -1 }
+};
+
+static const struct of_device_id r8a78000_cpg_match[] = {
+ {
+ .compatible = "renesas,r8a78000-cpg",
+ .data = &r8a78000_cpg_default,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver r8a78000_cpg_driver = {
+ .probe = r8a78000_cpg_probe,
+ .driver = {
+ .name = "r8a78000-cpg",
+ .of_match_table = r8a78000_cpg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(r8a78000_cpg_driver)
+
+MODULE_DESCRIPTION("R-Car X5H CPG Driver");
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver
2026-08-05 15:20 ` [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver Geert Uytterhoeven
@ 2026-08-05 22:22 ` Marek Vasut
0 siblings, 0 replies; 13+ messages in thread
From: Marek Vasut @ 2026-08-05 22:22 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Brian Masney,
Ulf Hansson, Philipp Zabel, Wolfram Sang, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel
On 8/5/26 5:20 PM, Geert Uytterhoeven wrote:
> Add a minimal Clock Pulse Generator driver for the R-Car X5H (R8A78000)
> SoC. For now this supports just the few fixed-rate clocks that are
> needed by the current minimal DTS.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
` (2 preceding siblings ...)
2026-08-05 15:20 ` [PATCH v3 3/6] clk: renesas: Add R-Car X5H CPG driver Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
2026-08-05 22:38 ` Marek Vasut
2026-08-06 8:13 ` Philipp Zabel
2026-08-05 15:20 ` [PATCH v3 5/6] arm64: dts: renesas: r8a78000: Add CPG node Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes Geert Uytterhoeven
5 siblings, 2 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven
Add a minimal Module Controller driver for the R-Car X5H (R8A78000) SoC.
For now this just supports the always-on power domains, and dummy module
clocks and resets for the serial console (which is enabled by the boot
loader).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Replace <linux/mod_devicetable.h> by more specific
<linux/device-id/of.h> in v7.2-rc2,
- Add a comment to document only always-on domains are supported,
- Consistently use /* sentinel */ for zero sentinels,
- Drop trailing commas from sentinels,
v2:
- Spin off from "pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping
driver",
- Add default support not using SCMI,
- Drop all SCMI remapping support,
- Document use of -1 as a sentinel,
- Rename struct r8a78000_mdlc_info to mdlc_info,
- Print HW IDs in hexadecimal,
- Reduce log level for unsupported MDLC instances from warn to dbg,
---
drivers/pmdomain/renesas/Kconfig | 4 +
drivers/pmdomain/renesas/Makefile | 1 +
drivers/pmdomain/renesas/r8a78000-mdlc.c | 330 +++++++++++++++++++++++
drivers/soc/renesas/Kconfig | 1 +
4 files changed, 336 insertions(+)
create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c
diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kconfig
index b507c3e0d723efc6..f2f52d3c29a083f1 100644
--- a/drivers/pmdomain/renesas/Kconfig
+++ b/drivers/pmdomain/renesas/Kconfig
@@ -13,6 +13,10 @@ config SYSC_RMOBILE
bool "System Controller support for R-Mobile" if COMPILE_TEST
# SoC
+config MDLC_R8A78000
+ bool "Module Controller support for R8A78000 (R-Car X5H)" if COMPILE_TEST
+ select RESET_CONTROLLER
+
config SYSC_R8A7742
bool "System Controller support for R8A7742 (RZ/G1H)" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/Makefile
index 0391e6e67440a786..17849aad37a5ac4f 100644
--- a/drivers/pmdomain/renesas/Makefile
+++ b/drivers/pmdomain/renesas/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
# SoC
+obj-$(CONFIG_MDLC_R8A78000) += r8a78000-mdlc.o
obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
new file mode 100644
index 0000000000000000..5c8acead7cff9bdd
--- /dev/null
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car X5H Module Controller
+ *
+ * Copyright (C) 2026 Glider bv
+ */
+
+#include <linux/dev_printk.h>
+#include <linux/device-id/of.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/power/renesas,r8a78000-mdlc.h>
+
+struct mod_map {
+ int hw_id; /* Hardware module ID or -1 sentinel */
+};
+
+struct mdlc_info {
+ u32 base;
+ const struct mod_map *mod_map;
+};
+
+/**
+ * struct r8a78000_mdlc_priv - Module Controller Private Data
+ *
+ * @link: Link into list of MDLC instances
+ * @genpd_data: PM domain provider data
+ * @rcdev: Reset controller entity
+ * @dev: MDLC device
+ * @np: Device node in DT representing the MDLC
+ * @mod_map: Mapping from hardware module IDs
+ */
+struct r8a78000_mdlc_priv {
+ struct hlist_node link;
+ struct genpd_onecell_data genpd_data;
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct device_node *np;
+ const struct mod_map *mod_map;
+};
+
+static struct generic_pm_domain *r8a78000_genpd_always_on;
+static HLIST_HEAD(r8a78000_mdlc_list);
+static DEFINE_MUTEX(r8a78000_mdlc_lock); /* protects the two above */
+
+static struct generic_pm_domain *r8a78000_genpd_xlate(
+ const struct of_phandle_args *spec, void *data)
+{
+ struct r8a78000_mdlc_priv *priv = container_of(data,
+ struct r8a78000_mdlc_priv, genpd_data);
+ struct device *dev = priv->dev;
+ u32 id;
+
+ if (spec->args_count != 2)
+ return ERR_PTR(-EINVAL);
+
+ id = spec->args[0];
+
+ if (id >= R8A78000_MDLC_PD_AON) {
+ dev_dbg(dev,
+ "Mapping HW power domain 0x%x to always-on domain\n",
+ id);
+ return r8a78000_genpd_always_on;
+ }
+
+ /* For now only always-on domains are supported */
+ dev_err(dev, "Unknown power domain 0x%x\n", id);
+ return ERR_PTR(-ENOENT);
+}
+
+#define rcdev_to_priv(_rcdev) \
+ container_of(_rcdev, struct r8a78000_mdlc_priv, rcdev)
+
+static const struct mod_map *mod_map_find(const struct mod_map *map, u32 id)
+{
+ if (!map)
+ return NULL;
+
+ for (; map->hw_id >= 0; map++) {
+ if (map->hw_id == id)
+ return map;
+ }
+
+ return NULL;
+}
+
+static int r8a78000_mdlc_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *spec)
+{
+ struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev);
+ struct device *dev = priv->dev;
+ const struct mod_map *map;
+ u32 id;
+
+ if (spec->args_count != 1)
+ return -EINVAL;
+
+ id = spec->args[0];
+
+ map = mod_map_find(priv->mod_map, id);
+ if (!map) {
+ dev_err(dev, "Unknown reset 0x%x\n", id);
+ return -ENOENT;
+ }
+
+ dev_dbg(dev, "Ignoring HW reset 0x%x\n", id);
+ return id;
+}
+
+#define DEFINE_MDLC_RESET_WRAPPER(op) \
+ static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \
+ unsigned long id) \
+ { \
+ struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev); \
+ \
+ dev_dbg(priv->dev, "%s: Ignoring\n", __func__); \
+ return 0; \
+ }
+
+DEFINE_MDLC_RESET_WRAPPER(reset)
+DEFINE_MDLC_RESET_WRAPPER(assert)
+DEFINE_MDLC_RESET_WRAPPER(deassert)
+DEFINE_MDLC_RESET_WRAPPER(status)
+
+static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
+ .reset = r8a78000_mdlc_reset,
+ .assert = r8a78000_mdlc_assert,
+ .deassert = r8a78000_mdlc_deassert,
+ .status = r8a78000_mdlc_status,
+};
+
+static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct r8a78000_mdlc_priv *priv;
+ struct of_phandle_args pd_spec;
+ const struct mod_map *map;
+ unsigned int id;
+ int ret;
+
+ ret = of_parse_phandle_with_args(np, "power-domains",
+ "#power-domain-cells", 0, &pd_spec);
+ if (ret < 0)
+ return ret;
+
+ if (pd_spec.args_count != 2) {
+ of_node_put(pd_spec.np);
+ return -EINVAL;
+ }
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) {
+ if (priv->np == pd_spec.np)
+ break;
+ }
+ }
+
+ if (!priv) {
+ dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np);
+ of_node_put(pd_spec.np);
+ return -ENODEV;
+ }
+
+ id = pd_spec.args[1];
+ of_node_put(pd_spec.np);
+
+ map = mod_map_find(priv->mod_map, id);
+ if (!map) {
+ dev_err(dev, "Unknown module 0x%x\n", id);
+ return -ENOENT;
+ }
+
+ dev_dbg(dev, "Ignoring HW module 0x%x\n", id);
+ return 0;
+}
+
+static void r8a78000_mdlc_unlink(void *data)
+{
+ struct r8a78000_mdlc_priv *priv = data;
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_del(&priv->link);
+ }
+}
+
+static void r8a78000_genpd_del_provider(void *data)
+{
+ of_genpd_del_provider(data);
+}
+
+static int r8a78000_genpd_always_on_singleton(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ int ret;
+
+ guard(mutex)(&r8a78000_mdlc_lock);
+
+ if (r8a78000_genpd_always_on)
+ return 0;
+
+ genpd = kzalloc_obj(*genpd);
+ if (!genpd)
+ return -ENOMEM;
+
+ genpd->name = "always-on";
+ genpd->attach_dev = r8a78000_mdlc_attach_dev;
+
+ ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ if (ret) {
+ kfree(genpd);
+ return dev_err_probe(dev, ret,
+ "Failed to create always-on domain\n");
+ }
+
+ r8a78000_genpd_always_on = genpd;
+ return 0;
+}
+
+static int r8a78000_mdlc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct r8a78000_mdlc_priv *priv;
+ const struct mdlc_info *info;
+ struct resource *res;
+ int ret;
+
+ ret = r8a78000_genpd_always_on_singleton(dev);
+ if (ret)
+ return ret;
+
+ info = of_device_get_match_data(dev);
+ if (!info)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->np = np;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ for (; info->base; info++) {
+ if (info->base == res->start)
+ break;
+ }
+
+ if (!info->base) {
+ dev_dbg(dev, "Unsupported MDLC instance 0x%pa\n", &res->start);
+ return -ENODEV;
+ }
+
+ priv->mod_map = info->mod_map;
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_add_head(&priv->link, &r8a78000_mdlc_list);
+ }
+
+ ret = devm_add_action_or_reset(dev, r8a78000_mdlc_unlink, priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add action\n");
+
+ /* Note that no actual domains are registered, just need translation */
+ priv->genpd_data.xlate = r8a78000_genpd_xlate;
+ ret = of_genpd_add_provider_onecell(np, &priv->genpd_data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register genpd provider\n");
+
+ ret = devm_add_action_or_reset(dev, r8a78000_genpd_del_provider, np);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to add unregister action\n");
+
+ priv->rcdev.ops = &r8a78000_mdlc_reset_ops;
+ priv->rcdev.of_node = np;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.of_xlate = r8a78000_mdlc_reset_xlate;
+
+ ret = devm_reset_controller_register(dev, &priv->rcdev);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register reset controller\n");
+
+ return 0;
+}
+
+static const struct mod_map r8a78000_mdlc_perw_mod_default[] = {
+ { 0x54 }, /* HSCIF0 */
+ { -1 }
+};
+
+static const struct mdlc_info r8a78000_mdlc_default[] = {
+ {
+ .base = 0xc05d0000 /* mdlc_perw */,
+ .mod_map = r8a78000_mdlc_perw_mod_default,
+ },
+ { /* sentinel */ }
+};
+
+static const struct of_device_id r8a78000_mdlc_match[] = {
+ {
+ .compatible = "renesas,r8a78000-mdlc",
+ .data = &r8a78000_mdlc_default,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver r8a78000_mdlc_driver = {
+ .probe = r8a78000_mdlc_probe,
+ .driver = {
+ .name = "r8a78000-mdlc",
+ .of_match_table = r8a78000_mdlc_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(r8a78000_mdlc_driver)
+
+MODULE_DESCRIPTION("R-Car X5H MDLC Driver");
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdf18ed2dfc2186d..eb8ac0d47d9d42b1 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -357,6 +357,7 @@ config ARCH_R8A78000
bool "ARM64 Platform support for R8A78000 (R-Car X5H)"
default y if ARCH_RENESAS
select ARCH_RCAR_GEN5
+ select MDLC_R8A78000
help
This enables support for the Renesas R-Car X5H SoC.
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-05 15:20 ` [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver Geert Uytterhoeven
@ 2026-08-05 22:38 ` Marek Vasut
2026-08-06 7:49 ` Geert Uytterhoeven
2026-08-06 8:13 ` Philipp Zabel
1 sibling, 1 reply; 13+ messages in thread
From: Marek Vasut @ 2026-08-05 22:38 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Brian Masney,
Ulf Hansson, Philipp Zabel, Wolfram Sang, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel
On 8/5/26 5:20 PM, Geert Uytterhoeven wrote:
Hello Geert,
[...]
> +DEFINE_MDLC_RESET_WRAPPER(reset)
> +DEFINE_MDLC_RESET_WRAPPER(assert)
> +DEFINE_MDLC_RESET_WRAPPER(deassert)
> +DEFINE_MDLC_RESET_WRAPPER(status)
> +
> +static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
> + .reset = r8a78000_mdlc_reset,
> + .assert = r8a78000_mdlc_assert,
> + .deassert = r8a78000_mdlc_deassert,
> + .status = r8a78000_mdlc_status,
> +};
Please keep the list sorted alphabetically.
> +static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain,
> + struct device *dev)
> +{
> + struct device_node *np = dev->of_node;
> + struct r8a78000_mdlc_priv *priv;
> + struct of_phandle_args pd_spec;
> + const struct mod_map *map;
> + unsigned int id;
> + int ret;
> +
> + ret = of_parse_phandle_with_args(np, "power-domains",
> + "#power-domain-cells", 0, &pd_spec);
> + if (ret < 0)
> + return ret;
> +
> + if (pd_spec.args_count != 2) {
> + of_node_put(pd_spec.np);
Maybe some "goto error" fail path which does of_node_put() wouldn't hurt
here, since the of_node_put() is duplicated in here multiple times.
> + return -EINVAL;
> + }
> +
> + scoped_guard(mutex, &r8a78000_mdlc_lock) {
> + hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) {
> + if (priv->np == pd_spec.np)
> + break;
> + }
> + }
> +
> + if (!priv) {
> + dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np);
> + of_node_put(pd_spec.np);
> + return -ENODEV;
> + }
> +
> + id = pd_spec.args[1];
> + of_node_put(pd_spec.np);
> +
> + map = mod_map_find(priv->mod_map, id);
> + if (!map) {
> + dev_err(dev, "Unknown module 0x%x\n", id);
> + return -ENOENT;
> + }
> +
> + dev_dbg(dev, "Ignoring HW module 0x%x\n", id);
> + return 0;
> +}
[...]
> +static int r8a78000_mdlc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct r8a78000_mdlc_priv *priv;
> + const struct mdlc_info *info;
> + struct resource *res;
> + int ret;
> +
> + ret = r8a78000_genpd_always_on_singleton(dev);
> + if (ret)
> + return ret;
> +
> + info = of_device_get_match_data(dev);
> + if (!info)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = dev;
> + priv->np = np;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> +
> + for (; info->base; info++) {
> + if (info->base == res->start)
> + break;
> + }
> +
> + if (!info->base) {
> + dev_dbg(dev, "Unsupported MDLC instance 0x%pa\n", &res->start);
return dev_err_probe() might be more appropriate here, even if that
would be more chatty until the support for various MDLC nodes lands.
Some dev_info_probe() would be even better, but we don't have that.
[...]
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-05 22:38 ` Marek Vasut
@ 2026-08-06 7:49 ` Geert Uytterhoeven
2026-08-06 12:53 ` Marek Vasut
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-06 7:49 UTC (permalink / raw)
To: Marek Vasut
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Kuninori Morimoto, devicetree, linux-clk, linux-pm,
linux-renesas-soc, linux-arm-kernel, linux-kernel
Hi Marek,
Thanks for your comments!
On Thu, 6 Aug 2026 at 00:38, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 8/5/26 5:20 PM, Geert Uytterhoeven wrote:
> > +DEFINE_MDLC_RESET_WRAPPER(reset)
> > +DEFINE_MDLC_RESET_WRAPPER(assert)
> > +DEFINE_MDLC_RESET_WRAPPER(deassert)
> > +DEFINE_MDLC_RESET_WRAPPER(status)
> > +
> > +static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
> > + .reset = r8a78000_mdlc_reset,
> > + .assert = r8a78000_mdlc_assert,
> > + .deassert = r8a78000_mdlc_deassert,
> > + .status = r8a78000_mdlc_status,
> > +};
>
> Please keep the list sorted alphabetically.
This matches the order in which the members of struct reset_control_ops
are defined.
> > +static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain,
> > + struct device *dev)
> > +{
> > + struct device_node *np = dev->of_node;
> > + struct r8a78000_mdlc_priv *priv;
> > + struct of_phandle_args pd_spec;
> > + const struct mod_map *map;
> > + unsigned int id;
> > + int ret;
> > +
> > + ret = of_parse_phandle_with_args(np, "power-domains",
> > + "#power-domain-cells", 0, &pd_spec);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (pd_spec.args_count != 2) {
> > + of_node_put(pd_spec.np);
>
> Maybe some "goto error" fail path which does of_node_put() wouldn't hurt
> here, since the of_node_put() is duplicated in here multiple times.
I'd rather keep it like this, as of_node_put() must not be called in all
error paths. Moreover, SCMI remapping will add more error paths,
and multiple fail* labels.
>
> > + return -EINVAL;
> > + }
> > +
> > + scoped_guard(mutex, &r8a78000_mdlc_lock) {
> > + hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) {
> > + if (priv->np == pd_spec.np)
> > + break;
> > + }
> > + }
> > +
> > + if (!priv) {
> > + dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np);
> > + of_node_put(pd_spec.np);
> > + return -ENODEV;
> > + }
> > +
> > + id = pd_spec.args[1];
> > + of_node_put(pd_spec.np);
> > +
> > + map = mod_map_find(priv->mod_map, id);
> > + if (!map) {
> > + dev_err(dev, "Unknown module 0x%x\n", id);
> > + return -ENOENT;
> > + }
> > +
> > + dev_dbg(dev, "Ignoring HW module 0x%x\n", id);
> > + return 0;
> > +}
>
> [...]
>
> > +static int r8a78000_mdlc_probe(struct platform_device *pdev)
> > +{
> > + if (!info->base) {
> > + dev_dbg(dev, "Unsupported MDLC instance 0x%pa\n", &res->start);
>
> return dev_err_probe() might be more appropriate here, even if that
> would be more chatty until the support for various MDLC nodes lands.
Indeed, it would be very chatty, and may confuse users, that's why
I used dev_dbg(). We can revisit that later.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-06 7:49 ` Geert Uytterhoeven
@ 2026-08-06 12:53 ` Marek Vasut
0 siblings, 0 replies; 13+ messages in thread
From: Marek Vasut @ 2026-08-06 12:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Kuninori Morimoto, devicetree, linux-clk, linux-pm,
linux-renesas-soc, linux-arm-kernel, linux-kernel
On 8/6/26 9:49 AM, Geert Uytterhoeven wrote:
Hello Geert,
>>> + if (!info->base) {
>>> + dev_dbg(dev, "Unsupported MDLC instance 0x%pa\n", &res->start);
>>
>> return dev_err_probe() might be more appropriate here, even if that
>> would be more chatty until the support for various MDLC nodes lands.
>
> Indeed, it would be very chatty, and may confuse users, that's why
> I used dev_dbg(). We can revisit that later.
All right.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-05 15:20 ` [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver Geert Uytterhoeven
2026-08-05 22:38 ` Marek Vasut
@ 2026-08-06 8:13 ` Philipp Zabel
2026-08-06 8:58 ` Geert Uytterhoeven
1 sibling, 1 reply; 13+ messages in thread
From: Philipp Zabel @ 2026-08-06 8:13 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd, Brian Masney,
Ulf Hansson, Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel
On Mi, 2026-08-05 at 17:20 +0200, Geert Uytterhoeven wrote:
> Add a minimal Module Controller driver for the R-Car X5H (R8A78000) SoC.
> For now this just supports the always-on power domains, and dummy module
> clocks and resets for the serial console (which is enabled by the boot
> loader).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
> - Replace <linux/mod_devicetable.h> by more specific
> <linux/device-id/of.h> in v7.2-rc2,
> - Add a comment to document only always-on domains are supported,
> - Consistently use /* sentinel */ for zero sentinels,
> - Drop trailing commas from sentinels,
>
> v2:
> - Spin off from "pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping
> driver",
> - Add default support not using SCMI,
> - Drop all SCMI remapping support,
> - Document use of -1 as a sentinel,
> - Rename struct r8a78000_mdlc_info to mdlc_info,
> - Print HW IDs in hexadecimal,
> - Reduce log level for unsupported MDLC instances from warn to dbg,
> ---
> drivers/pmdomain/renesas/Kconfig | 4 +
> drivers/pmdomain/renesas/Makefile | 1 +
> drivers/pmdomain/renesas/r8a78000-mdlc.c | 330 +++++++++++++++++++++++
> drivers/soc/renesas/Kconfig | 1 +
> 4 files changed, 336 insertions(+)
> create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c
>
> diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> new file mode 100644
> index 0000000000000000..5c8acead7cff9bdd
> --- /dev/null
> +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> @@ -0,0 +1,330 @@
[...]
> +#define DEFINE_MDLC_RESET_WRAPPER(op) \
> + static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \
> + unsigned long id) \
> + { \
> + struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev); \
> + \
> + dev_dbg(priv->dev, "%s: Ignoring\n", __func__); \
> + return 0; \
> + }
> +
> +DEFINE_MDLC_RESET_WRAPPER(reset)
> +DEFINE_MDLC_RESET_WRAPPER(assert)
> +DEFINE_MDLC_RESET_WRAPPER(deassert)
> +DEFINE_MDLC_RESET_WRAPPER(status)
> +
> +static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
> + .reset = r8a78000_mdlc_reset,
> + .assert = r8a78000_mdlc_assert,
> + .deassert = r8a78000_mdlc_deassert,
> + .status = r8a78000_mdlc_status,
Are .reset and .status needed by any consumers?
I'd leave them -ENOTSUPP otherwise.
regards
Philipp
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver
2026-08-06 8:13 ` Philipp Zabel
@ 2026-08-06 8:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-06 8:58 UTC (permalink / raw)
To: Philipp Zabel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Wolfram Sang,
Marek Vasut, Kuninori Morimoto, devicetree, linux-clk, linux-pm,
linux-renesas-soc, linux-arm-kernel, linux-kernel
Hi Philipp,
On Thu, 6 Aug 2026 at 10:13, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> On Mi, 2026-08-05 at 17:20 +0200, Geert Uytterhoeven wrote:
> > Add a minimal Module Controller driver for the R-Car X5H (R8A78000) SoC.
> > For now this just supports the always-on power domains, and dummy module
> > clocks and resets for the serial console (which is enabled by the boot
> > loader).
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v3:
> > - Replace <linux/mod_devicetable.h> by more specific
> > <linux/device-id/of.h> in v7.2-rc2,
> > - Add a comment to document only always-on domains are supported,
> > - Consistently use /* sentinel */ for zero sentinels,
> > - Drop trailing commas from sentinels,
> >
> > v2:
> > - Spin off from "pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping
> > driver",
> > - Add default support not using SCMI,
> > - Drop all SCMI remapping support,
> > - Document use of -1 as a sentinel,
> > - Rename struct r8a78000_mdlc_info to mdlc_info,
> > - Print HW IDs in hexadecimal,
> > - Reduce log level for unsupported MDLC instances from warn to dbg,
> > ---
> > drivers/pmdomain/renesas/Kconfig | 4 +
> > drivers/pmdomain/renesas/Makefile | 1 +
> > drivers/pmdomain/renesas/r8a78000-mdlc.c | 330 +++++++++++++++++++++++
> > drivers/soc/renesas/Kconfig | 1 +
> > 4 files changed, 336 insertions(+)
> > create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c
> >
> > diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> > new file mode 100644
> > index 0000000000000000..5c8acead7cff9bdd
> > --- /dev/null
> > +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> > @@ -0,0 +1,330 @@
> [...]
> > +#define DEFINE_MDLC_RESET_WRAPPER(op) \
> > + static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \
> > + unsigned long id) \
> > + { \
> > + struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev); \
> > + \
> > + dev_dbg(priv->dev, "%s: Ignoring\n", __func__); \
> > + return 0; \
> > + }
> > +
> > +DEFINE_MDLC_RESET_WRAPPER(reset)
> > +DEFINE_MDLC_RESET_WRAPPER(assert)
> > +DEFINE_MDLC_RESET_WRAPPER(deassert)
> > +DEFINE_MDLC_RESET_WRAPPER(status)
> > +
> > +static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
> > + .reset = r8a78000_mdlc_reset,
> > + .assert = r8a78000_mdlc_assert,
> > + .deassert = r8a78000_mdlc_deassert,
> > + .status = r8a78000_mdlc_status,
>
> Are .reset and .status needed by any consumers?
> I'd leave them -ENOTSUPP otherwise.
.reset is used by a variety of R-Car drivers.
.status is used by the R-Car I2C and PCIe drivers.
So both will be used later.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 5/6] arm64: dts: renesas: r8a78000: Add CPG node
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
` (3 preceding siblings ...)
2026-08-05 15:20 ` [PATCH v3 4/6] pmdomain: renesas: Add R-Car X5H MDLC driver Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
2026-08-05 15:20 ` [PATCH v3 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes Geert Uytterhoeven
5 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven
Add a device node for the Clock Pulse Generator (CPG) on the R-Car X5H
(R8A78000) SoC.
Convert all (H)SCIF serial ports from dummy to CPG clocks, removing the
need for any dummy clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
v3:
- Add Reviewed-by,
v2:
- Split in separate CPG and MDLC patches.
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 59 +++++++++++++----------
1 file changed, 34 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index fb71974ef390509d..1fe078c7822c01a5 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
+#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -668,23 +669,6 @@ L3_CA720_7: cache-controller-37 {
};
};
- /*
- * In the early phase, there is no clock control support,
- * so assume that the clocks are enabled by default.
- * Therefore, dummy clocks are used.
- */
- dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <66666000>;
- };
-
- dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <266660000>;
- };
-
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -882,7 +866,9 @@ scif0: serial@c0700000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0700000 0 0x40>;
interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -892,7 +878,9 @@ scif1: serial@c0704000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0704000 0 0x40>;
interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -902,7 +890,9 @@ scif3: serial@c0708000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0708000 0 0x40>;
interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -912,7 +902,9 @@ scif4: serial@c070c000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc070c000 0 0x40>;
interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -922,7 +914,9 @@ hscif0: serial@c0710000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0710000 0 0x60>;
interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -932,7 +926,9 @@ hscif1: serial@c0714000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0714000 0 0x60>;
interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -942,7 +938,9 @@ hscif2: serial@c0718000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0718000 0 0x60>;
interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -952,7 +950,9 @@ hscif3: serial@c071c000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc071c000 0 0x60>;
interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@@ -965,6 +965,15 @@ stcm_transport: sram@c1060000 {
ranges = <0 0x0 0xc1060000 0x1c00>;
/* actual transport nodes must be set per board file */
};
+
+ cpg: clock-controller@c1320000 {
+ compatible = "renesas,r8a78000-cpg";
+ reg = <0 0xc1320000 0 0x10000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <1>;
+ bootph-all;
+ };
};
timer {
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes
2026-08-05 15:20 [PATCH v3 0/6] R-Car X5H CPG/MDLC support Geert Uytterhoeven
` (4 preceding siblings ...)
2026-08-05 15:20 ` [PATCH v3 5/6] arm64: dts: renesas: r8a78000: Add CPG node Geert Uytterhoeven
@ 2026-08-05 15:20 ` Geert Uytterhoeven
5 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2026-08-05 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Brian Masney, Ulf Hansson, Philipp Zabel,
Wolfram Sang, Marek Vasut, Kuninori Morimoto
Cc: devicetree, linux-clk, linux-pm, linux-renesas-soc,
linux-arm-kernel, linux-kernel, Geert Uytterhoeven
Add device nodes for the Module Control (MDLC) blocks on the R-Car X5H
(R8A78000) SoC.
Complete hardware desciption of all (H)SCIF serial ports, by linking
them to an MDLC for power domains and resets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
v3:
- Add Reviewed-by,
- Sort MDLC nodes (alphabetically, by label),
v2:
- Split in separate CPG and MDLC patches.
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 241 ++++++++++++++++++++++
1 file changed, 241 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 1fe078c7822c01a5..9a07753b221541ed 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
+#include <dt-bindings/power/renesas,r8a78000-mdlc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -870,6 +871,8 @@ scif0: serial@c0700000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x40>;
+ resets = <&mdlc_perw 0x40>;
status = "disabled";
};
@@ -882,6 +885,8 @@ scif1: serial@c0704000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x41>;
+ resets = <&mdlc_perw 0x41>;
status = "disabled";
};
@@ -894,6 +899,8 @@ scif3: serial@c0708000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x42>;
+ resets = <&mdlc_perw 0x42>;
status = "disabled";
};
@@ -906,6 +913,8 @@ scif4: serial@c070c000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x43>;
+ resets = <&mdlc_perw 0x43>;
status = "disabled";
};
@@ -918,6 +927,8 @@ hscif0: serial@c0710000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x54>;
+ resets = <&mdlc_perw 0x54>;
status = "disabled";
};
@@ -930,6 +941,8 @@ hscif1: serial@c0714000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x55>;
+ resets = <&mdlc_perw 0x55>;
status = "disabled";
};
@@ -942,6 +955,8 @@ hscif2: serial@c0718000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x56>;
+ resets = <&mdlc_perw 0x56>;
status = "disabled";
};
@@ -954,6 +969,8 @@ hscif3: serial@c071c000 {
<&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x57>;
+ resets = <&mdlc_perw 0x57>;
status = "disabled";
};
@@ -974,6 +991,230 @@ cpg: clock-controller@c1320000 {
#clock-cells = <1>;
bootph-all;
};
+
+ mdlc_aon: system-controller@c1338000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1338000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmnn: system-controller@ca410000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca410000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmns: system-controller@ca510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr0: system-controller@e8000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr1: system-controller@e8080000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8080000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr2: system-controller@e8100000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8100000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr3: system-controller@e8180000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8180000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr4: system-controller@e8200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr5: system-controller@e8280000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8280000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr6: system-controller@e8300000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8300000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr7: system-controller@e8380000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8380000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_dsp: system-controller@cbe90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcbe90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_gpc: system-controller@cb510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcb510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscn: system-controller@c9c90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc9c90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscs: system-controller@de200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xde200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_imn: system-controller@c1990000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1990000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ims: system-controller@c1d90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1d90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_mm: system-controller@e9980000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe9980000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu0: system-controller@d2c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd2c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu1: system-controller@d6c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd6c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_pere: system-controller@c08f0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc08f0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_perw: system-controller@c05d0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc05d0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_rt: system-controller@19440000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0x19440000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_scp: system-controller@c1330000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1330000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_top: system-controller@c6480000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc6480000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vio: system-controller@c5000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc5000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vipn: system-controller@c3060000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3060000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vips: system-controller@c3460000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3460000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
};
timer {
--
2.43.0
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