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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Linu Cherian <linu.cherian@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] arm64: cputype: Add C1-Nano definitions
Date: Fri, 3 Jul 2026 10:40:11 +0530	[thread overview]
Message-ID: <e155f25b-fe7b-4432-8615-126e71d2543a@arm.com> (raw)
In-Reply-To: <20260701094131.677636-5-linu.cherian@arm.com>

On 01/07/26 3:11 PM, Linu Cherian wrote:
> Add cputype definitions for C1-Nano.
> 
> The definition can be found in C1-Nano TRM,
> https://developer.arm.com/documentation/107753/0002
> as part of MIDR_EL1 bit descriptions.
> 
> This is going to be used in the bbml3 support list.
> 
> Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> ---
>  arch/arm64/include/asm/cputype.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index e41fae46426b..1fa29616e586 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -100,6 +100,7 @@
>  #define ARM_CPU_PART_CORTEX_A720AE	0xD89
>  #define ARM_CPU_PART_C1_ULTRA		0xD8C
>  #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
> +#define ARM_CPU_PART_C1_NANO		0xD8A

Part number checks out in the TRM.
>  #define ARM_CPU_PART_C1_PRO		0xD8B
>  #define ARM_CPU_PART_C1_PREMIUM		0xD90
>  
> @@ -195,6 +196,7 @@
>  #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
>  #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
>  #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
>  #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
>  #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
>  #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>



  reply	other threads:[~2026-07-03  5:10 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-01  9:41 [PATCH 0/5] Add BBML3 cpu feature Linu Cherian
2026-07-01  9:41 ` [PATCH 1/5] arm64: cpufeature: Add BBML3 Linu Cherian
2026-07-01  9:41 ` [PATCH 2/5] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Linu Cherian
2026-07-02 10:45   ` Mark Rutland
2026-07-03  3:06     ` Linu Cherian
2026-07-03  4:36     ` Anshuman Khandual
2026-07-01  9:41 ` [PATCH 3/5] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-03  5:07   ` Anshuman Khandual
2026-07-01  9:41 ` [PATCH 4/5] arm64: cputype: Add C1-Nano definitions Linu Cherian
2026-07-03  5:10   ` Anshuman Khandual [this message]
2026-07-01  9:41 ` [PATCH 5/5] arm64: cpufeature: Extend bbml3 support list Linu Cherian
2026-07-02 10:47   ` Mark Rutland
2026-07-03  3:03     ` Linu Cherian
2026-07-01 10:11 ` [PATCH 0/5] Add BBML3 cpu feature Suzuki K Poulose
2026-07-03  3:16   ` Linu Cherian
2026-07-03  4:15     ` Linu Cherian
2026-07-03  4:42       ` Anshuman Khandual

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