From: Linu Cherian <linu.cherian@arm.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/5] arm64: cpufeature: Detect BBML3 based on MMFR2 ID
Date: Fri, 3 Jul 2026 08:36:13 +0530 [thread overview]
Message-ID: <akcnJXF59mH8_P7P@a079125.arm.com> (raw)
In-Reply-To: <akZBOkMSH77C6MH5@J2N7QTR9R3>
Hi Mark,
On Thu, Jul 02, 2026 at 11:45:14AM +0100, Mark Rutland wrote:
> On Wed, Jul 01, 2026 at 03:11:28PM +0530, Linu Cherian wrote:
> > Add MMFR2 ID based BBML3 feature detection, so
> > that compliant cpus doesn't need to be added to the
> > midr list.
> >
> > Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> > ---
> > arch/arm64/kernel/cpufeature.c | 14 +++++++-------
> > arch/arm64/tools/sysreg | 1 +
> > 2 files changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 9986eb7b379c..d754b1b7da77 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -2133,6 +2133,7 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
> >
> > bool cpu_supports_bbml3(void)
> > {
> > + u64 mmfr2;
> > /* CPUs that support BBML3 but dont advertise through MMFR2 ID */
> > static const struct midr_range supports_bbml3_list[] = {
> > MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
> > @@ -2144,15 +2145,14 @@ bool cpu_supports_bbml3(void)
> > {}
> > };
> >
> > - if (!is_midr_in_range_list(supports_bbml3_list))
> > - return false;
> > + if (is_midr_in_range_list(supports_bbml3_list))
> > + return true;
> >
> > - /*
> > - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care
> > - * about whether the MIDR check passes.
> > - */
> > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1);
> > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) == ID_AA64MMFR2_EL1_BBM_3)
> > + return true;
>
> This needs to be '>=', so that if there's a future BBML4, we correctly
> detect that CPUs with BBML4 also have the BBML3 behaviour.
>
> It would also be better to check the ID field first, before falling back
> to the MIDR check. That way a reader can more clearly see that
> supports_bbml3_list catches older parts that don't advertised BBML3, and
> the comment above supports_bbml3_list would be clearer.
Okay, agree.
--
Thanks,
Linu Cherian.
next prev parent reply other threads:[~2026-07-03 3:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 9:41 [PATCH 0/5] Add BBML3 cpu feature Linu Cherian
2026-07-01 9:41 ` [PATCH 1/5] arm64: cpufeature: Add BBML3 Linu Cherian
2026-07-01 9:41 ` [PATCH 2/5] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Linu Cherian
2026-07-02 10:45 ` Mark Rutland
2026-07-03 3:06 ` Linu Cherian [this message]
2026-07-03 4:36 ` Anshuman Khandual
2026-07-01 9:41 ` [PATCH 3/5] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-03 5:07 ` Anshuman Khandual
2026-07-01 9:41 ` [PATCH 4/5] arm64: cputype: Add C1-Nano definitions Linu Cherian
2026-07-03 5:10 ` Anshuman Khandual
2026-07-01 9:41 ` [PATCH 5/5] arm64: cpufeature: Extend bbml3 support list Linu Cherian
2026-07-02 10:47 ` Mark Rutland
2026-07-03 3:03 ` Linu Cherian
2026-07-01 10:11 ` [PATCH 0/5] Add BBML3 cpu feature Suzuki K Poulose
2026-07-03 3:16 ` Linu Cherian
2026-07-03 4:15 ` Linu Cherian
2026-07-03 4:42 ` Anshuman Khandual
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