Re: [PATCH net-next] net: airoha: Fix EGRESS_RATE_METER_EN_MASK definition

[Jacob Keller <jacob.e.keller@intel.com>]

On 10/4/2024 2:51 PM, Lorenzo Bianconi wrote:
> Fix typo in EGRESS_RATE_METER_EN_MASK mask definition. This bus was not
> introducing any user visible problem.
> 

I'm not sure I follow. This bit is used by airoha_qdma_init_qos which
sets the REG_EGRESS_RATE_METER_CFG register?

How does this not provide any user visible issues? It seems like an
incorrect enable bit likely means that QOS is not enabled? I'm guessing
bit 29 is reserved?

It would be good to understand why this is not considered a fix?  The
offending commit is in the net branch already.

> Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
> for EN7581 SoC")
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  drivers/net/ethernet/mediatek/airoha_eth.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/airoha_eth.c b/drivers/net/ethernet/mediatek/airoha_eth.c
> index 2e01abc70c170f32f4206b34e116b441c14c628e..a1cfdc146a41610a3a6b060bfdc6e1d9aad97d5d 100644
> --- a/drivers/net/ethernet/mediatek/airoha_eth.c
> +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
> @@ -554,7 +554,7 @@
>  #define FWD_DSCP_LOW_THR_MASK		GENMASK(17, 0)
>  
>  #define REG_EGRESS_RATE_METER_CFG		0x100c
> -#define EGRESS_RATE_METER_EN_MASK		BIT(29)
> +#define EGRESS_RATE_METER_EN_MASK		BIT(31)
>  #define EGRESS_RATE_METER_EQ_RATE_EN_MASK	BIT(17)
>  #define EGRESS_RATE_METER_WINDOW_SZ_MASK	GENMASK(16, 12)
>  #define EGRESS_RATE_METER_TIMESLICE_MASK	GENMASK(10, 0)
> 
> ---
> base-commit: c55ff46aeebed1704a9a6861777b799f15ce594d
> change-id: 20241004-airoha-fixes-8aaa8177b234
> 
> Best regards,