Re: [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards

[Patrice CHOTARD <patrice.chotard@foss.st.com>]

Hi Marek

Have you some remarks about DHCOR DT update ?

Thanks
Patrice

On 1/23/26 11:14, Patrice Chotard wrote:
> The bootph-all flag was introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across
> different boot phases.
> 
> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
> present in all boot stages, so add missing bootph-all phase flag
> to these nodes to support SD boot.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
>  arch/arm/boot/dts/st/stm32mp131.dtsi             |   4 +-
>  arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts |  21 ++++
>  arch/arm/boot/dts/st/stm32mp135f-dk.dts          | 101 ++++++++++++++++
>  arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi  | 145 +++++++++++++++++++----
>  4 files changed, 247 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
> index fd730aa37c22..80c97bc830eb 100644
> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
> @@ -30,7 +30,7 @@ arm-pmu {
>  	};
>  
>  	firmware {
> -		optee {
> +		optee: optee {
>  			method = "smc";
>  			compatible = "linaro,optee-tz";
>  			interrupt-parent = <&intc>;
> @@ -85,7 +85,7 @@ intc: interrupt-controller@a0021000 {
>  		      <0xa0022000 0x2000>;
>  	};
>  
> -	psci {
> +	psci: psci {
>  		compatible = "arm,psci-1.0";
>  		method = "smc";
>  	};
> diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> index 9902849ed040..526ab2e1a93c 100644
> --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> @@ -350,6 +350,21 @@ timer@12 {
>  	};
>  };
>  
> +&uart4 {
> +	bootph-all;
> +};
> +
> +&uart4_pins_b {
> +	bootph-all;
> +
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> +
>  &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
>  	pinctrl-names = "default", "sleep", "idle";
>  	pinctrl-0 = <&usart1_pins_b>;
> @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
>  	status = "okay";
>  };
>  
> +&usbphyc {
> +	bootph-all;
> +};
> +
>  &usbh_ehci {
>  	phys = <&usbphyc_port0>;
>  	status = "okay";
> @@ -432,6 +451,7 @@ connector {
>  
>  /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
>  &vdd_ldo2 {
> +	bootph-all;
>  	regulator-always-on;
>  	regulator-boot-on;
>  	regulator-min-microvolt = <3300000>;
> @@ -440,6 +460,7 @@ &vdd_ldo2 {
>  
>  /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
>  &vdd_sd {
> +	bootph-all;
>  	regulator-always-on;
>  	regulator-boot-on;
>  	regulator-min-microvolt = <3300000>;
> diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> index 9764a6bfa5b4..83bc5ea90c3a 100644
> --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> @@ -161,6 +161,10 @@ channel@12 {
>  	};
>  };
>  
> +&bsec {
> +	bootph-all;
> +};
> +
>  &crc1 {
>  	status = "okay";
>  };
> @@ -208,6 +212,42 @@ phy0_eth1: ethernet-phy@0 {
>  	};
>  };
>  
> +&gpioa {
> +	bootph-all;
> +};
> +
> +&gpiob {
> +	bootph-all;
> +};
> +
> +&gpioc {
> +	bootph-all;
> +};
> +
> +&gpiod {
> +	bootph-all;
> +};
> +
> +&gpioe {
> +	bootph-all;
> +};
> +
> +&gpiof {
> +	bootph-all;
> +};
> +
> +&gpiog {
> +	bootph-all;
> +};
> +
> +&gpioh {
> +	bootph-all;
> +};
> +
> +&gpioi {
> +	bootph-all;
> +};
> +
>  &i2c1 {
>  	pinctrl-names = "default", "sleep";
>  	pinctrl-0 = <&i2c1_pins_a>;
> @@ -342,6 +382,7 @@ goodix: goodix-ts@5d {
>  
>  &iwdg2 {
>  	timeout-sec = <32>;
> +	bootph-all;
>  	status = "okay";
>  };
>  
> @@ -349,6 +390,7 @@ &ltdc {
>  	pinctrl-names = "default", "sleep";
>  	pinctrl-0 = <&ltdc_pins_a>;
>  	pinctrl-1 = <&ltdc_sleep_pins_a>;
> +	bootph-some-ram;
>  	status = "okay";
>  
>  	port {
> @@ -358,6 +400,22 @@ ltdc_out_rgb: endpoint {
>  	};
>  };
>  
> +&optee {
> +	bootph-all;
> +};
> +
> +&pinctrl {
> +	bootph-all;
> +};
> +
> +&psci {
> +	bootph-some-ram;
> +};
> +
> +&rcc {
> +	bootph-all;
> +};
> +
>  &rtc {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&rtc_rsvd_pins_a>;
> @@ -369,6 +427,14 @@ rtc_lsco_pins_a: rtc-lsco-0 {
>  	};
>  };
>  
> +&scmi {
> +	bootph-all;
> +};
> +
> +&scmi_clk {
> +	bootph-all;
> +};
> +
>  &scmi_regu {
>  	scmi_vdd_adc: regulator@10 {
>  		reg = <VOLTD_SCMI_STPMIC1_LDO1>;
> @@ -392,6 +458,10 @@ scmi_v3v3_sw: regulator@19 {
>  	};
>  };
>  
> +&scmi_reset {
> +	bootph-all;
> +};
> +
>  &sdmmc1 {
>  	pinctrl-names = "default", "opendrain", "sleep";
>  	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
> @@ -402,9 +472,24 @@ &sdmmc1 {
>  	st,neg-edge;
>  	bus-width = <4>;
>  	vmmc-supply = <&scmi_vdd_sd>;
> +	bootph-pre-ram;
>  	status = "okay";
>  };
>  
> +&sdmmc1_b4_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&sdmmc1_clk_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
>  /* Wifi */
>  &sdmmc2 {
>  	pinctrl-names = "default", "opendrain", "sleep";
> @@ -436,6 +521,10 @@ &spi5 {
>  	status = "disabled";
>  };
>  
> +&syscfg {
> +	bootph-all;
> +};
> +
>  &timers3 {
>  	/delete-property/dmas;
>  	/delete-property/dma-names;
> @@ -517,9 +606,20 @@ &uart4 {
>  	pinctrl-2 = <&uart4_idle_pins_a>;
>  	/delete-property/dmas;
>  	/delete-property/dma-names;
> +	bootph-all;
>  	status = "okay";
>  };
>  
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> +
>  &uart8 {
>  	pinctrl-names = "default", "sleep", "idle";
>  	pinctrl-0 = <&uart8_pins_a>;
> @@ -583,6 +683,7 @@ usbotg_hs_ep: endpoint {
>  };
>  
>  &usbphyc {
> +	bootph-all;
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> index c18156807027..4efaca84a72c 100644
> --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> @@ -54,6 +54,46 @@ vin: vin {
>  	};
>  };
>  
> +&bsec {
> +	bootph-all;
> +};
> +
> +&gpioa {
> +	bootph-all;
> +};
> +
> +&gpiob {
> +	bootph-all;
> +};
> +
> +&gpioc {
> +	bootph-all;
> +};
> +
> +&gpiod {
> +	bootph-all;
> +};
> +
> +&gpioe {
> +	bootph-all;
> +};
> +
> +&gpiof {
> +	bootph-all;
> +};
> +
> +&gpiog {
> +	bootph-all;
> +};
> +
> +&gpioh {
> +	bootph-all;
> +};
> +
> +&gpioi {
> +	bootph-all;
> +};
> +
>  &i2c3 {
>  	i2c-scl-rising-time-ns = <96>;
>  	i2c-scl-falling-time-ns = <3>;
> @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 {
>  
>  &iwdg2 {
>  	timeout-sec = <32>;
> +	bootph-all;
>  	status = "okay";
>  };
>  
> +&pinctrl {
> +	bootph-all;
> +};
> +
> +&psci {
> +	bootph-some-ram;
> +};
> +
>  &qspi {
>  	pinctrl-names = "default", "sleep";
>  	pinctrl-0 = <&qspi_clk_pins_a
> @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a
>  		     &qspi_cs1_sleep_pins_a>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	bootph-all;
>  	status = "okay";
>  
>  	flash0: flash@0 {
> @@ -238,37 +288,35 @@ flash0: flash@0 {
>  		spi-max-frequency = <108000000>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> +		bootph-all;
>  	};
>  };
>  
> -/* Console UART */
> -&uart4 {
> -	pinctrl-names = "default", "sleep", "idle";
> -	pinctrl-0 = <&uart4_pins_b>;
> -	pinctrl-1 = <&uart4_sleep_pins_b>;
> -	pinctrl-2 = <&uart4_idle_pins_b>;
> -	/delete-property/dmas;
> -	/delete-property/dma-names;
> -	status = "okay";
> +&qspi_clk_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
> +	};
>  };
>  
> -/* Bluetooth */
> -&uart7 {
> -	pinctrl-names = "default", "sleep", "idle";
> -	pinctrl-0 = <&uart7_pins_a>;
> -	pinctrl-1 = <&uart7_sleep_pins_a>;
> -	pinctrl-2 = <&uart7_idle_pins_a>;
> -	uart-has-rtscts;
> -	status = "okay";
> +&qspi_bk1_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
> +	};
> +};
>  
> -	bluetooth {
> -		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
> -		max-speed = <3000000>;
> -		device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
> -		shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
> +&qspi_cs1_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
>  	};
>  };
>  
> +&rcc {
> +	bootph-all;
> +};
> +
>  /* SDIO WiFi */
>  &sdmmc1 {
>  	pinctrl-names = "default", "opendrain", "sleep";
> @@ -312,3 +360,56 @@ &sdmmc2 {
>  	vqmmc-supply = <&vdd>;
>  	status = "okay";
>  };
> +
> +&syscfg {
> +	bootph-all;
> +};
> +
> +/* Console UART */
> +&uart4 {
> +	pinctrl-names = "default", "sleep", "idle";
> +	pinctrl-0 = <&uart4_pins_b>;
> +	pinctrl-1 = <&uart4_sleep_pins_b>;
> +	pinctrl-2 = <&uart4_idle_pins_b>;
> +	/delete-property/dmas;
> +	/delete-property/dma-names;
> +	status = "okay";
> +};
> +
> +/* Bluetooth */
> +&uart7 {
> +	pinctrl-names = "default", "sleep", "idle";
> +	pinctrl-0 = <&uart7_pins_a>;
> +	pinctrl-1 = <&uart7_sleep_pins_a>;
> +	pinctrl-2 = <&uart7_idle_pins_a>;
> +	uart-has-rtscts;
> +	status = "okay";
> +
> +	bluetooth {
> +		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
> +		max-speed = <3000000>;
> +		device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
> +		shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&vdd {
> +	bootph-all;
> +};
> +
> +&vddcpu {
> +	bootph-all;
> +};
> +
> +
> +&vddcore {
> +	bootph-all;
> +};
> +
> +&vdd_ddr {
> +	bootph-all;
> +};
> +
> +&vref_ddr {
> +	bootph-all;
> +};
>