* [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards
@ 2026-01-23 10:14 Patrice Chotard
2026-01-23 10:14 ` [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier,
Marek Vasut
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel,
Patrice Chotard
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
Changes in v5:
- Initial implementation allows to factorize and add bootph-* properties in a limited number of DT files.
After internal discussion with Alexandre, choice has been done to add bootph-* properties only
in board DT files instead of SoCs/pinctrl/boards DT files.This impacts a greater number of DT boards files.
- Link to v4: https://lore.kernel.org/r/20260109-upstream_uboot_properties-v4-0-75e06657c600@foss.st.com
Changes in v4:
- Remove useless nodes in stm32mp15-scmi.dtsi
- Link to v3: https://lore.kernel.org/r/20260108-upstream_uboot_properties-v3-0-c1b9d4f2ce8d@foss.st.com
Changes in v3:
- Remove duplicate bootph-all property in ltdc node
- Link to v2: https://lore.kernel.org/r/20251114-upstream_uboot_properties-v2-0-3784ff668ae0@foss.st.com
Changes in v2:
- Fix 'pinmux' is a required property for arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dtb
- Add bootph-all property for lvds and ltdc nodes for stm32mp2
---
Patrice Chotard (6):
ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards
ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards
ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards
ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards
ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards
arch/arm/boot/dts/st/stm32429i-eval.dts | 80 ++++++++++
arch/arm/boot/dts/st/stm32746g-eval.dts | 10 ++
arch/arm/boot/dts/st/stm32f429-disco.dts | 80 ++++++++++
arch/arm/boot/dts/st/stm32f469-disco.dts | 72 +++++++++
arch/arm/boot/dts/st/stm32f746-disco.dts | 75 +++++++++
arch/arm/boot/dts/st/stm32f746.dtsi | 2 +-
arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++-
arch/arm/boot/dts/st/stm32h743i-disco.dts | 69 +++++++++
arch/arm/boot/dts/st/stm32h743i-eval.dts | 69 +++++++++
arch/arm/boot/dts/st/stm32h747i-disco.dts | 69 +++++++++
arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 69 +++++++++
arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +-
arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 +++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 ++++++++++++
arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 145 ++++++++++++++---
arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +-
arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++
.../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 +
.../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++
.../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++
.../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++
...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++
.../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++
.../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++
arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +
arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 +
arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++
arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++
arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +
arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++
arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 +
arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++
arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++
arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 +
arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 +
arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 +
arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 +
arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++++++
.../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++
.../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++
arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++++
.../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++
arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++
arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 25 +++
arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++
arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +-
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 ++++++++++++
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++
51 files changed, 2545 insertions(+), 37 deletions(-)
---
base-commit: 53c18dc078bb6d9e9dfe2cc0671ab78588c44723
change-id: 20251112-upstream_uboot_properties-22480b0b4b1c
Best regards,
--
Patrice Chotard <patrice.chotard@foss.st.com>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard ` (4 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32429i-eval.dts | 80 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 80 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 72 ++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index afa417b34b25..05cdc3d9d015 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -175,6 +175,15 @@ adc3: adc@200 { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; &crc { @@ -196,6 +205,50 @@ dcmi_0: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; @@ -265,6 +318,18 @@ phy1: ethernet-phy@1 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status = "okay"; }; @@ -280,6 +345,10 @@ &sdio { max-frequency = <12500000>; }; +&syscfg { + bootph-all; +}; + &timers1 { status = "okay"; @@ -312,6 +381,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -326,6 +396,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "host"; phys = <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts index a3cb4aabdd5a..75c1de0b0496 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -102,12 +102,65 @@ vcc5v_otg: vcc5v-otg-regulator { &clk_hse { clock-frequency = <8000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; &crc { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -165,6 +218,18 @@ ltdc_out_rgb: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; @@ -205,10 +270,15 @@ panel_in_rgb: endpoint { }; }; +&syscfg { + bootph-all; +}; + &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -223,6 +293,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible = "st,stm32f4x9-fsotg"; dr_mode = "host"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts index 8a4f8ddd083d..8d089546c0cf 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -168,7 +168,52 @@ dsi_panel_in: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + <dc { + bootph-all; status = "okay"; port { @@ -178,10 +223,26 @@ ltdc_out_dsi: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status = "okay"; }; +&syscfg { + bootph-all; +}; + &timers1 { status = "okay"; @@ -225,6 +286,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -239,6 +301,16 @@ &usart3 { status = "okay"; }; +&usart3_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode = "host"; pinctrl-0 = <&usbotg_fs_pins_a>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 +++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 75 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f746.dtsi | 2 +- arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++++++++++++++++++++++++-- 4 files changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index e9ac37b6eca0..26c5796a81fb 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -213,6 +213,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "otg"; phys = <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index b57dbdce2f40..ed0facce5841 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -140,6 +140,51 @@ panel_in_rgb: endpoint { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; &i2c1 { @@ -169,6 +214,7 @@ touchscreen@38 { <dc { pinctrl-0 = <<dc_pins_a>; pinctrl-names = "default"; + bootph-all; status = "okay"; port { @@ -178,6 +224,22 @@ ltdc_out_rgb: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&soc { + bootph-all; +}; + &sdio1 { status = "okay"; vmmc-supply = <&vcc_3v3>; @@ -193,6 +255,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -204,9 +267,21 @@ &timers5 { &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode = "host"; pinctrl-0 = <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 208f8c6dfc9d..1fede5bdc347 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -75,7 +75,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; }; - soc { + soc: soc { timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 535cfdc4681c..b3a9e31f1da6 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -116,10 +116,6 @@ vcc_3v3: vcc-3v3 { }; }; -&rcc { - compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - &cec { pinctrl-0 = <&cec_pins_a>; pinctrl-names = "default"; @@ -128,11 +124,13 @@ &cec { &clk_hse { clock-frequency = <25000000>; + bootph-all; }; &dsi { #address-cells = <1>; #size-cells = <0>; + bootph-all; status = "okay"; ports { @@ -169,6 +167,50 @@ dsi_panel_in: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -178,6 +220,7 @@ &i2c1 { }; <dc { + bootph-all; status = "okay"; port { @@ -187,6 +230,19 @@ ltdc_out_dsi: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; + bootph-all; +}; + &rtc { status = "okay"; }; @@ -207,6 +263,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -218,9 +275,20 @@ &timers5 { &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "otg"; phys = <&usbotg_hs_phy>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32h743i-disco.dts | 69 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32h743i-eval.dts | 69 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32h747i-disco.dts | 69 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 69 ++++++++++++++++++++++++++++++ 4 files changed, 276 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index 8451a54a9a08..368035d96158 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -73,6 +73,59 @@ v3v3: regulator-v3v3 { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; &mac { @@ -92,6 +145,18 @@ phy0: ethernet-phy@0 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -104,6 +169,10 @@ &sdmmc1 { status = "okay"; }; +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 4b0ced27b80e..ec525411431a 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -99,6 +99,59 @@ adc1: adc@0 { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; &i2c1 { @@ -130,6 +183,18 @@ phy0: ethernet-phy@0 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; @@ -144,6 +209,10 @@ &sdmmc1 { status = "okay"; }; +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts index 99f0255dae8e..a481326ad9e6 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -91,6 +91,59 @@ button-5 { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; &mac { @@ -110,6 +163,18 @@ phy0: ethernet-phy@0 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -123,6 +188,10 @@ &sdmmc1 { status = "okay"; }; +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts index 56c53e262da7..8dddc70c37a1 100644 --- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -114,6 +114,15 @@ wlan_pwr: regulator-wlan { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; }; &dma1 { @@ -124,6 +133,50 @@ &dma2 { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &mac { status = "disabled"; pinctrl-0 = <ðernet_rmii>; @@ -141,6 +194,18 @@ phy0: ethernet-phy@0 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -196,6 +261,10 @@ partition@0 { }; }; +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard ` (2 preceding siblings ...) 2026-01-23 10:14 ` [PATCH v5 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 2026-03-25 14:18 ` Patrice CHOTARD 2026-01-23 10:14 ` [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard 5 siblings, 1 reply; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 ++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 ++++++++++++++++ arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 145 +++++++++++++++++++---- 4 files changed, 247 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index fd730aa37c22..80c97bc830eb 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -30,7 +30,7 @@ arm-pmu { }; firmware { - optee { + optee: optee { method = "smc"; compatible = "linaro,optee-tz"; interrupt-parent = <&intc>; @@ -85,7 +85,7 @@ intc: interrupt-controller@a0021000 { <0xa0022000 0x2000>; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 9902849ed040..526ab2e1a93c 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -350,6 +350,21 @@ timer@12 { }; }; +&uart4 { + bootph-all; +}; + +&uart4_pins_b { + bootph-all; + + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&usart1_pins_b>; @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ status = "okay"; }; +&usbphyc { + bootph-all; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; @@ -432,6 +451,7 @@ connector { /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_ldo2 { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; @@ -440,6 +460,7 @@ &vdd_ldo2 { /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_sd { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 9764a6bfa5b4..83bc5ea90c3a 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -161,6 +161,10 @@ channel@12 { }; }; +&bsec { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -208,6 +212,42 @@ phy0_eth1: ethernet-phy@0 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -342,6 +382,7 @@ goodix: goodix-ts@5d { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -349,6 +390,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>; + bootph-some-ram; status = "okay"; port { @@ -358,6 +400,22 @@ ltdc_out_rgb: endpoint { }; }; +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rtc { pinctrl-names = "default"; pinctrl-0 = <&rtc_rsvd_pins_a>; @@ -369,6 +427,14 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vdd_adc: regulator@10 { reg = <VOLTD_SCMI_STPMIC1_LDO1>; @@ -392,6 +458,10 @@ scmi_v3v3_sw: regulator@19 { }; }; +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -402,9 +472,24 @@ &sdmmc1 { st,neg-edge; bus-width = <4>; vmmc-supply = <&scmi_vdd_sd>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc1_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; @@ -436,6 +521,10 @@ &spi5 { status = "disabled"; }; +&syscfg { + bootph-all; +}; + &timers3 { /delete-property/dmas; /delete-property/dma-names; @@ -517,9 +606,20 @@ &uart4 { pinctrl-2 = <&uart4_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; + bootph-all; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart8 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart8_pins_a>; @@ -583,6 +683,7 @@ usbotg_hs_ep: endpoint { }; &usbphyc { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index c18156807027..4efaca84a72c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -54,6 +54,46 @@ vin: vin { }; }; +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c3 { i2c-scl-rising-time-ns = <96>; i2c-scl-falling-time-ns = <3>; @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a &qspi_cs1_sleep_pins_a>; #address-cells = <1>; #size-cells = <0>; + bootph-all; status = "okay"; flash0: flash@0 { @@ -238,37 +288,35 @@ flash0: flash@0 { spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; + bootph-all; }; }; -/* Console UART */ -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_b>; - pinctrl-1 = <&uart4_sleep_pins_b>; - pinctrl-2 = <&uart4_idle_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; }; -/* Bluetooth */ -&uart7 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart7_pins_a>; - pinctrl-1 = <&uart7_sleep_pins_a>; - pinctrl-2 = <&uart7_idle_pins_a>; - uart-has-rtscts; - status = "okay"; +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; - bluetooth { - compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; - max-speed = <3000000>; - device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; }; }; +&rcc { + bootph-all; +}; + /* SDIO WiFi */ &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; @@ -312,3 +360,56 @@ &sdmmc2 { vqmmc-supply = <&vdd>; status = "okay"; }; + +&syscfg { + bootph-all; +}; + +/* Console UART */ +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_b>; + pinctrl-1 = <&uart4_sleep_pins_b>; + pinctrl-2 = <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed = <3000000>; + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&vdd { + bootph-all; +}; + +&vddcpu { + bootph-all; +}; + + +&vddcore { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards 2026-01-23 10:14 ` [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard @ 2026-03-25 14:18 ` Patrice CHOTARD 0 siblings, 0 replies; 9+ messages in thread From: Patrice CHOTARD @ 2026-03-25 14:18 UTC (permalink / raw) To: Alexandre Torgue, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Patrick Delaunay, Christoph Niedermaier Hi Marek Have you some remarks about DHCOR DT update ? Thanks Patrice On 1/23/26 11:14, Patrice Chotard wrote: > The bootph-all flag was introduced in dt-schema > (dtschema/schemas/bootph.yaml) to define node usage across > different boot phases. > > To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be > present in all boot stages, so add missing bootph-all phase flag > to these nodes to support SD boot. > > Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> > --- > arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +- > arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 ++++ > arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 ++++++++++++++++ > arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 145 +++++++++++++++++++---- > 4 files changed, 247 insertions(+), 24 deletions(-) > > diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi > index fd730aa37c22..80c97bc830eb 100644 > --- a/arch/arm/boot/dts/st/stm32mp131.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi > @@ -30,7 +30,7 @@ arm-pmu { > }; > > firmware { > - optee { > + optee: optee { > method = "smc"; > compatible = "linaro,optee-tz"; > interrupt-parent = <&intc>; > @@ -85,7 +85,7 @@ intc: interrupt-controller@a0021000 { > <0xa0022000 0x2000>; > }; > > - psci { > + psci: psci { > compatible = "arm,psci-1.0"; > method = "smc"; > }; > diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > index 9902849ed040..526ab2e1a93c 100644 > --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts > @@ -350,6 +350,21 @@ timer@12 { > }; > }; > > +&uart4 { > + bootph-all; > +}; > + > +&uart4_pins_b { > + bootph-all; > + > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&usart1_pins_b>; > @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ > status = "okay"; > }; > > +&usbphyc { > + bootph-all; > +}; > + > &usbh_ehci { > phys = <&usbphyc_port0>; > status = "okay"; > @@ -432,6 +451,7 @@ connector { > > /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ > &vdd_ldo2 { > + bootph-all; > regulator-always-on; > regulator-boot-on; > regulator-min-microvolt = <3300000>; > @@ -440,6 +460,7 @@ &vdd_ldo2 { > > /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ > &vdd_sd { > + bootph-all; > regulator-always-on; > regulator-boot-on; > regulator-min-microvolt = <3300000>; > diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts > index 9764a6bfa5b4..83bc5ea90c3a 100644 > --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts > +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts > @@ -161,6 +161,10 @@ channel@12 { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > &crc1 { > status = "okay"; > }; > @@ -208,6 +212,42 @@ phy0_eth1: ethernet-phy@0 { > }; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > &i2c1 { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c1_pins_a>; > @@ -342,6 +382,7 @@ goodix: goodix-ts@5d { > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -349,6 +390,7 @@ <dc { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <<dc_pins_a>; > pinctrl-1 = <<dc_sleep_pins_a>; > + bootph-some-ram; > status = "okay"; > > port { > @@ -358,6 +400,22 @@ ltdc_out_rgb: endpoint { > }; > }; > > +&optee { > + bootph-all; > +}; > + > +&pinctrl { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > +&rcc { > + bootph-all; > +}; > + > &rtc { > pinctrl-names = "default"; > pinctrl-0 = <&rtc_rsvd_pins_a>; > @@ -369,6 +427,14 @@ rtc_lsco_pins_a: rtc-lsco-0 { > }; > }; > > +&scmi { > + bootph-all; > +}; > + > +&scmi_clk { > + bootph-all; > +}; > + > &scmi_regu { > scmi_vdd_adc: regulator@10 { > reg = <VOLTD_SCMI_STPMIC1_LDO1>; > @@ -392,6 +458,10 @@ scmi_v3v3_sw: regulator@19 { > }; > }; > > +&scmi_reset { > + bootph-all; > +}; > + > &sdmmc1 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; > @@ -402,9 +472,24 @@ &sdmmc1 { > st,neg-edge; > bus-width = <4>; > vmmc-supply = <&scmi_vdd_sd>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_clk_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > /* Wifi */ > &sdmmc2 { > pinctrl-names = "default", "opendrain", "sleep"; > @@ -436,6 +521,10 @@ &spi5 { > status = "disabled"; > }; > > +&syscfg { > + bootph-all; > +}; > + > &timers3 { > /delete-property/dmas; > /delete-property/dma-names; > @@ -517,9 +606,20 @@ &uart4 { > pinctrl-2 = <&uart4_idle_pins_a>; > /delete-property/dmas; > /delete-property/dma-names; > + bootph-all; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &uart8 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart8_pins_a>; > @@ -583,6 +683,7 @@ usbotg_hs_ep: endpoint { > }; > > &usbphyc { > + bootph-all; > status = "okay"; > }; > > diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi > index c18156807027..4efaca84a72c 100644 > --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi > @@ -54,6 +54,46 @@ vin: vin { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > &i2c3 { > i2c-scl-rising-time-ns = <96>; > i2c-scl-falling-time-ns = <3>; > @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 { > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > &qspi { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&qspi_clk_pins_a > @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a > &qspi_cs1_sleep_pins_a>; > #address-cells = <1>; > #size-cells = <0>; > + bootph-all; > status = "okay"; > > flash0: flash@0 { > @@ -238,37 +288,35 @@ flash0: flash@0 { > spi-max-frequency = <108000000>; > #address-cells = <1>; > #size-cells = <1>; > + bootph-all; > }; > }; > > -/* Console UART */ > -&uart4 { > - pinctrl-names = "default", "sleep", "idle"; > - pinctrl-0 = <&uart4_pins_b>; > - pinctrl-1 = <&uart4_sleep_pins_b>; > - pinctrl-2 = <&uart4_idle_pins_b>; > - /delete-property/dmas; > - /delete-property/dma-names; > - status = "okay"; > +&qspi_clk_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > }; > > -/* Bluetooth */ > -&uart7 { > - pinctrl-names = "default", "sleep", "idle"; > - pinctrl-0 = <&uart7_pins_a>; > - pinctrl-1 = <&uart7_sleep_pins_a>; > - pinctrl-2 = <&uart7_idle_pins_a>; > - uart-has-rtscts; > - status = "okay"; > +&qspi_bk1_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > > - bluetooth { > - compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; > - max-speed = <3000000>; > - device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; > - shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; > +&qspi_cs1_pins_a { > + bootph-all; > + pins { > + bootph-all; > }; > }; > > +&rcc { > + bootph-all; > +}; > + > /* SDIO WiFi */ > &sdmmc1 { > pinctrl-names = "default", "opendrain", "sleep"; > @@ -312,3 +360,56 @@ &sdmmc2 { > vqmmc-supply = <&vdd>; > status = "okay"; > }; > + > +&syscfg { > + bootph-all; > +}; > + > +/* Console UART */ > +&uart4 { > + pinctrl-names = "default", "sleep", "idle"; > + pinctrl-0 = <&uart4_pins_b>; > + pinctrl-1 = <&uart4_sleep_pins_b>; > + pinctrl-2 = <&uart4_idle_pins_b>; > + /delete-property/dmas; > + /delete-property/dma-names; > + status = "okay"; > +}; > + > +/* Bluetooth */ > +&uart7 { > + pinctrl-names = "default", "sleep", "idle"; > + pinctrl-0 = <&uart7_pins_a>; > + pinctrl-1 = <&uart7_sleep_pins_a>; > + pinctrl-2 = <&uart7_idle_pins_a>; > + uart-has-rtscts; > + status = "okay"; > + > + bluetooth { > + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; > + max-speed = <3000000>; > + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; > + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; > + }; > +}; > + > +&vdd { > + bootph-all; > +}; > + > +&vddcpu { > + bootph-all; > +}; > + > + > +&vddcore { > + bootph-all; > +}; > + > +&vdd_ddr { > + bootph-all; > +}; > + > +&vref_ddr { > + bootph-all; > +}; > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard ` (3 preceding siblings ...) 2026-01-23 10:14 ` [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 2026-03-25 14:25 ` Patrice CHOTARD 2026-01-23 10:14 ` [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard 5 siblings, 1 reply; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++ .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 + .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++ .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++ .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++ ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++ .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++ .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++ arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++ arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 + arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 + arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++++++ .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++ .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++++ .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++ 28 files changed, 1297 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b1b568dfd126..ada55b2c1aa2 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -30,7 +30,7 @@ arm-pmu { interrupt-parent = <&intc>; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index 847b360f02fc..b81b6e168b67 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -65,6 +65,7 @@ &m4_rproc { &optee { interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + bootph-some-ram; }; &rcc { @@ -85,3 +86,21 @@ &rng1 { &rtc { clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index df97e03d2a5a..4ad1313efca9 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -92,6 +92,7 @@ bridge_out: endpoint { }; <dc { + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts index 60ce4425a7fd..ac4e313ca371 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -35,15 +35,40 @@ &sdmmc1 { pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply = <&v3v3>; + bootph-all; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index f8e404346396..cc24a29fba15 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -92,6 +92,7 @@ bridge_out_panel: endpoint { }; <dc { + bootph-some-ram; status = "okay"; port { @@ -110,15 +111,40 @@ &sdmmc1 { pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply = <&v3v3>; + bootph-all; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi index 569a7e940ecc..db93934019d1 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi @@ -61,6 +61,7 @@ vddcore: regulator-vddcore { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; + bootph-all; }; vdd: regulator-vdd { @@ -69,6 +70,7 @@ vdd: regulator-vdd { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-all; }; vdd_usb: regulator-vdd-usb { @@ -77,6 +79,7 @@ vdd_usb: regulator-vdd-usb { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-all; }; vdda: regulator-vdda { @@ -85,6 +88,7 @@ vdda: regulator-vdda { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-all; }; vdd_ddr: regulator-vdd-ddr { @@ -93,6 +97,7 @@ vdd_ddr: regulator-vdd-ddr { regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; + bootph-all; }; vtt_ddr: regulator-vtt-ddr { @@ -102,6 +107,7 @@ vtt_ddr: regulator-vtt-ddr { regulator-max-microvolt = <675000>; regulator-always-on; vin-supply = <&vdd>; + bootph-all; }; vref_ddr: regulator-vref-ddr { @@ -111,6 +117,7 @@ vref_ddr: regulator-vref-ddr { regulator-max-microvolt = <675000>; regulator-always-on; vin-supply = <&vdd>; + bootph-all; }; vdd_sd: regulator-vdd-sd { @@ -119,6 +126,7 @@ vdd_sd: regulator-vdd-sd { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-all; }; v3v3: regulator-v3v3 { @@ -127,6 +135,7 @@ v3v3: regulator-v3v3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-all; }; v2v8: regulator-v2v8 { @@ -136,6 +145,7 @@ v2v8: regulator-v2v8 { regulator-max-microvolt = <2800000>; regulator-always-on; vin-supply = <&v3v3>; + bootph-all; }; v1v8: regulator-v1v8 { @@ -145,13 +155,86 @@ v1v8: regulator-v1v8 { regulator-max-microvolt = <1800000>; regulator-always-on; vin-supply = <&v3v3>; + bootph-all; }; }; +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { i2c-scl-falling-time-ns = <20>; i2c-scl-rising-time-ns = <185>; @@ -167,6 +250,7 @@ &ipcc { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -180,6 +264,22 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5116a7785201..7bfd7da4a8db 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -78,6 +78,7 @@ &i2c2 { <dc { pinctrl-names = "default"; pinctrl-0 = <<dc_pins>; + bootph-some-ram; status = "okay"; port { @@ -134,19 +135,45 @@ &sdmmc1 { pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply = <&vdd>; + bootph-all; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index d949559be020..a1f79659d7c5 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -36,19 +36,46 @@ &sdmmc1 { pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply = <&vdd>; + bootph-all; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi index a75f50cf7123..4f6f4712d634 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi @@ -61,6 +61,7 @@ vin: regulator-vin { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; + bootph-all; }; vddcore: regulator-vddcore { @@ -70,6 +71,7 @@ vddcore: regulator-vddcore { regulator-max-microvolt = <1200000>; regulator-always-on; vin-supply = <&vin>; + bootph-all; }; vdd: regulator-vdd { @@ -79,6 +81,7 @@ vdd: regulator-vdd { regulator-max-microvolt = <3300000>; regulator-always-on; vin-supply = <&vin>; + bootph-all; }; vddq_ddr: regulator-vddq-ddr { @@ -88,9 +91,34 @@ vddq_ddr: regulator-vddq-ddr { regulator-max-microvolt = <1350000>; regulator-always-on; vin-supply = <&vin>; + bootph-all; }; }; +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status = "okay"; }; @@ -113,12 +141,61 @@ nand@0 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &ipcc { status = "okay"; }; &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -132,6 +209,26 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 43280289759d..e192d033626e 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -71,6 +71,7 @@ &m4_rproc { &optee { interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + bootph-some-ram; }; &rcc { @@ -91,3 +92,7 @@ &rng1 { &rtc { clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 1ec3b8f2faa9..bf9fdf0d611c 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -80,6 +80,7 @@ touchscreen@38 { }; <dc { + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 6f27d794d270..f053a70cb254 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -70,6 +70,7 @@ &m4_rproc { &optee { interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + bootph-some-ram; }; &rcc { @@ -90,3 +91,21 @@ &rng1 { &rtc { clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index f6c478dbd041..86919bb642fa 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -132,6 +132,31 @@ channel@6 { }; }; + +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -157,6 +182,54 @@ &dts { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &hash1 { status = "okay"; }; @@ -168,7 +241,9 @@ &i2c4 { i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; + bootph-all; status = "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -179,6 +254,7 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + bootph-all; status = "okay"; regulators { @@ -314,12 +390,20 @@ watchdog { }; }; +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status = "okay"; }; &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -335,9 +419,26 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; &rng1 { @@ -365,9 +466,30 @@ &sdmmc1 { sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; @@ -381,9 +503,27 @@ &sdmmc2 { vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &timers6 { status = "okay"; /* spare dmas for other usage */ @@ -399,11 +539,22 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { vbus-supply = <&vbus_otg>; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 6ae391bffee5..17295d67ab85 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -75,6 +75,7 @@ &m4_rproc { &optee { interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + bootph-some-ram; }; &rcc { @@ -95,3 +96,7 @@ &rng1 { &rtc { clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 8f99c30f1af1..d43bddc42ad9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -231,6 +231,7 @@ &i2c5 { }; <dc { + bootph-some-ram; status = "okay"; port { @@ -262,6 +263,7 @@ &qspi_bk2_sleep_pins_a reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; status = "okay"; flash0: flash@0 { @@ -271,6 +273,7 @@ flash0: flash@0 { spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; + bootph-pre-ram; }; flash1: flash@1 { @@ -283,6 +286,41 @@ flash1: flash@1 { }; }; +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc3_b4_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts index eada9cf257be..9f513045c559 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts @@ -158,6 +158,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_c>; pinctrl-1 = <<dc_sleep_pins_c>; + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi index cf7485251490..1c5517f57ecd 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -75,11 +75,84 @@ led-blue { }; }; +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + bootph-all; status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -91,6 +164,7 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + bootph-all; regulators { compatible = "st,stpmic1-regulators"; @@ -218,12 +292,20 @@ watchdog { }; }; +&i2c2_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status = "okay"; }; &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -237,6 +319,26 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status = "okay"; }; @@ -258,6 +360,23 @@ &sdmmc2 { vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_d { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts index a8b3f7a54703..92bc25b3f563 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts @@ -75,14 +75,35 @@ &sdmmc1 { st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 36e6055b5665..b404ea3752d9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -131,6 +131,7 @@ i2s2_endpoint: endpoint { }; <dc { + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi index 89de85a2eff3..5d29c2154b46 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi @@ -87,6 +87,7 @@ &mdma1 { &optee { interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + bootph-some-ram; }; &pwr_regulators { @@ -114,6 +115,10 @@ &rtc { clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; +&scmi { + bootph-some-ram; +}; + &scmi_reguls { scmi_vddcore: regulator@3 { reg = <VOLTD_SCMI_STPMIC1_BUCK1>; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts index 8fa61e54d026..4d857b3575fd 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -97,6 +97,7 @@ stpmic@33 { }; <dc { + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 5c77202ee196..2e02cd8e7e0d 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -201,6 +201,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_b>; pinctrl-1 = <<dc_sleep_pins_b>; + bootph-some-ram; status = "okay"; port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index 4cc633683c6b..2c40ceaf1f33 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -103,6 +103,10 @@ channel@1 { }; }; +&bsec { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -121,6 +125,26 @@ dac2: dac@2 { }; }; +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status = "okay"; }; @@ -190,6 +214,7 @@ &gpioa { "", "", "DHCOM-K", "", "", "", "", "", "", "", "", ""; + bootph-all; }; &gpiob { @@ -197,6 +222,7 @@ &gpiob { "", "", "", "", "DHCOM-Q", "", "", "", "", "", "", ""; + bootph-all; }; &gpioc { @@ -204,6 +230,7 @@ &gpioc { "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; + bootph-all; }; &gpiod { @@ -211,6 +238,7 @@ &gpiod { "", "", "DHCOM-B", "", "", "", "", "DHCOM-F", "DHCOM-D", "", "", ""; + bootph-all; }; &gpioe { @@ -218,6 +246,7 @@ &gpioe { "", "", "DHCOM-P", "", "", "", "", "", "", "", "", ""; + bootph-all; }; &gpiof { @@ -225,6 +254,7 @@ &gpiof { "", "", "", "", "", "", "", "", "", "", "", ""; + bootph-all; }; &gpiog { @@ -232,6 +262,7 @@ &gpiog { "", "", "", "", "DHCOM-L", "", "", "", "", "", "", ""; + bootph-all; }; &gpioh { @@ -239,6 +270,7 @@ &gpioh { "", "", "", "DHCOM-N", "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", "", "DHCOM-S", ""; + bootph-all; }; &gpioi { @@ -246,6 +278,20 @@ &gpioi { "DHCOM-R", "DHCOM-M", "", "", "", "", "", "", "", "", "", ""; + bootph-all; +}; + +&gpioj { + bootph-all; + +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; }; &i2c4 { @@ -253,6 +299,8 @@ &i2c4 { pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + bootph-all; + bootph-pre-ram; status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -269,6 +317,8 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + bootph-all; + bootph-pre-ram; regulators { compatible = "st,stpmic1-regulators"; @@ -279,6 +329,7 @@ regulators { ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; + bootph-pre-ram; vddcore: buck1 { regulator-name = "vddcore"; @@ -409,12 +460,20 @@ eeprom@50 { }; }; +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status = "okay"; }; &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -428,9 +487,22 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; + bootph-all; }; &qspi { @@ -444,6 +516,7 @@ &qspi_bk1_sleep_pins_a reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; status = "okay"; flash0: flash@0 { @@ -453,6 +526,28 @@ flash0: flash@0 { spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; + bootph-pre-ram; + }; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; }; }; @@ -469,6 +564,15 @@ &rcc { assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; assigned-clock-parents = <&rcc PLL4_P>; assigned-clock-rates = <50000000>, <100000000>; + bootph-all; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; }; &rng1 { @@ -495,6 +599,7 @@ &sdmmc1 { st,ckin-gpios = <&gpioe 4 0>; bus-width = <4>; vmmc-supply = <&vdd_sd>; + bootph-pre-ram; status = "okay"; }; @@ -504,11 +609,24 @@ &sdmmc1_b4_pins_a { * - optional on SoMs with SD voltage translator * - mandatory on SoMs without SD voltage translator */ + bootph-pre-ram; pins1 { bias-pull-up; + bootph-pre-ram; }; pins2 { bias-pull-up; + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; }; }; @@ -525,9 +643,24 @@ &sdmmc2 { vmmc-supply = <&v3v3>; vqmmc-supply = <&v3v3>; mmc-ddr-3_3v; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc3_b4_pins_a>; @@ -545,7 +678,46 @@ &sdmmc3 { &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index aceeff6c38ba..e7e2203ab11a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -355,6 +355,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_d>; pinctrl-1 = <<dc_sleep_pins_d>; + bootph-some-ram; status = "okay"; port { @@ -402,9 +403,30 @@ &sdmmc1 { bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -418,9 +440,27 @@ &sdmmc2 { st,neg-edge; vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd_io>; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc3_b4_pins_b>; @@ -455,11 +495,22 @@ &uart4 { label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { /* On Low speed expansion header */ label = "LS-UART0"; @@ -512,3 +563,7 @@ &usbphyc_port0 { &usbphyc_port1 { phy-supply = <&vdd_usb>; }; + +&vdd_io { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi index bc4ddcbdd5cf..9c6a04b4c2e3 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi @@ -231,9 +231,30 @@ &sdmmc1 { /* MicroSD */ bus-width = <4>; vmmc-supply = <&vdd>; vqmmc-supply = <&vdd>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { /* eMMC */ pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -246,9 +267,27 @@ &sdmmc2 { /* eMMC */ st,neg-edge; vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { /* SDIO Wi-Fi */ pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc3_b4_pins_a>; @@ -276,11 +315,22 @@ &uart4 { label = "UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_d>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_d { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart5 { /* X11 UART */ label = "X11-UART5"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi index 89881a26c614..3d469e29d41a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -63,6 +63,30 @@ retram: retram@38000000 { }; }; +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -71,11 +95,61 @@ &dts { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + bootph-all; + bootph-pre-ram; status = "okay"; /delete-property/dmas; /delete-property/dma-names; @@ -86,6 +160,8 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + bootph-all; + bootph-pre-ram; status = "okay"; regulators { @@ -98,6 +174,7 @@ regulators { ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; + bootph-pre-ram; vddcore: buck1 { regulator-name = "vddcore"; @@ -215,12 +292,20 @@ watchdog { }; }; +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status = "okay"; }; &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -234,9 +319,23 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; + bootph-all; + bootph-pre-ram; }; &qspi { @@ -250,6 +349,7 @@ &qspi_bk1_sleep_pins_a reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; status = "okay"; flash0: flash@0 { @@ -262,6 +362,35 @@ flash0: flash@0 { }; }; +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; +}; + &rng1 { status = "okay"; }; @@ -269,3 +398,31 @@ &rng1 { &rtc { status = "okay"; }; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi index 6e79c4b6fe32..3b5debd0ffc9 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi @@ -131,9 +131,30 @@ &sdmmc1 { bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -147,17 +168,46 @@ &sdmmc2 { st,neg-edge; vmmc-supply = <&v3v3>; vqmmc-supply = <&v3v3>; + bootph-pre-ram; status = "okay"; }; +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 8cea6facd27b..62d6417ed422 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -129,6 +129,10 @@ channel@19 { }; }; +&bsec { + bootph-all; +}; + &cec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cec_pins_b>; @@ -136,6 +140,26 @@ &cec { status = "okay"; }; +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -144,6 +168,54 @@ &dts { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; @@ -249,6 +321,7 @@ &i2c4 { i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; + bootph-all; status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -284,6 +357,7 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + bootph-all; status = "okay"; regulators { @@ -422,6 +496,13 @@ watchdog { }; }; +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &i2c5 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_pins_a>; @@ -458,6 +539,7 @@ &ipcc { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -465,6 +547,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>; + bootph-some-ram; status = "okay"; port { @@ -486,9 +569,26 @@ &m4_rproc { status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; &rng1 { @@ -553,9 +653,20 @@ &sdmmc1 { st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc3_b4_pins_a>; @@ -676,11 +787,22 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart7_pins_c>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards 2026-01-23 10:14 ` [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard @ 2026-03-25 14:25 ` Patrice CHOTARD 0 siblings, 0 replies; 9+ messages in thread From: Patrice CHOTARD @ 2026-03-25 14:25 UTC (permalink / raw) To: Alexandre Torgue, Marek Vasut, Jagan Teki Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Patrick Delaunay, Christoph Niedermaier Hi Jagan, Marek Any remarks on these Engicam MicroGEA/ICORE/DHCOM/DHCOR dt update ? Thanks Patrice On 1/23/26 11:14, Patrice Chotard wrote: > The bootph-all flag was introduced in dt-schema > (dtschema/schemas/bootph.yaml) to define node usage across > different boot phases. > > To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be > present in all boot stages, so add missing bootph-all phase flag > to these nodes to support SD boot. > > Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> > --- > arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +- > arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++ > .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 + > .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++ > .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++ > .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++ > ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++ > .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++ > .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++ > arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 + > arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 + > arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++ > arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++ > arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 + > arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++ > arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 + > arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++ > arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++ > arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 + > arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 + > arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 + > arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 + > arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++++++ > .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++ > .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++ > arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++++ > .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++ > arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++ > 28 files changed, 1297 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi > index b1b568dfd126..ada55b2c1aa2 100644 > --- a/arch/arm/boot/dts/st/stm32mp151.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi > @@ -30,7 +30,7 @@ arm-pmu { > interrupt-parent = <&intc>; > }; > > - psci { > + psci: psci { > compatible = "arm,psci-1.0"; > method = "smc"; > }; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > index 847b360f02fc..b81b6e168b67 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > @@ -65,6 +65,7 @@ &m4_rproc { > &optee { > interrupt-parent = <&intc>; > interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + bootph-some-ram; > }; > > &rcc { > @@ -85,3 +86,21 @@ &rng1 { > &rtc { > clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; > }; > + > +&scmi { > + bootph-some-ram; > +}; > + > +&uart4 { > + bootph-all; > +}; > + > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts > index df97e03d2a5a..4ad1313efca9 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts > @@ -92,6 +92,7 @@ bridge_out: endpoint { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts > index 60ce4425a7fd..ac4e313ca371 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts > @@ -35,15 +35,40 @@ &sdmmc1 { > pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; > st,neg-edge; > vmmc-supply = <&v3v3>; > + bootph-all; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + }; > +}; > + > &uart4 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > + > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + bias-pull-up; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts > index f8e404346396..cc24a29fba15 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts > @@ -92,6 +92,7 @@ bridge_out_panel: endpoint { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > @@ -110,15 +111,40 @@ &sdmmc1 { > pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; > st,neg-edge; > vmmc-supply = <&v3v3>; > + bootph-all; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + }; > +}; > + > &uart4 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > + > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + bias-pull-up; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi > index 569a7e940ecc..db93934019d1 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi > @@ -61,6 +61,7 @@ vddcore: regulator-vddcore { > regulator-min-microvolt = <1200000>; > regulator-max-microvolt = <1200000>; > regulator-always-on; > + bootph-all; > }; > > vdd: regulator-vdd { > @@ -69,6 +70,7 @@ vdd: regulator-vdd { > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > regulator-always-on; > + bootph-all; > }; > > vdd_usb: regulator-vdd-usb { > @@ -77,6 +79,7 @@ vdd_usb: regulator-vdd-usb { > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > regulator-always-on; > + bootph-all; > }; > > vdda: regulator-vdda { > @@ -85,6 +88,7 @@ vdda: regulator-vdda { > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > regulator-always-on; > + bootph-all; > }; > > vdd_ddr: regulator-vdd-ddr { > @@ -93,6 +97,7 @@ vdd_ddr: regulator-vdd-ddr { > regulator-min-microvolt = <1350000>; > regulator-max-microvolt = <1350000>; > regulator-always-on; > + bootph-all; > }; > > vtt_ddr: regulator-vtt-ddr { > @@ -102,6 +107,7 @@ vtt_ddr: regulator-vtt-ddr { > regulator-max-microvolt = <675000>; > regulator-always-on; > vin-supply = <&vdd>; > + bootph-all; > }; > > vref_ddr: regulator-vref-ddr { > @@ -111,6 +117,7 @@ vref_ddr: regulator-vref-ddr { > regulator-max-microvolt = <675000>; > regulator-always-on; > vin-supply = <&vdd>; > + bootph-all; > }; > > vdd_sd: regulator-vdd-sd { > @@ -119,6 +126,7 @@ vdd_sd: regulator-vdd-sd { > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > regulator-always-on; > + bootph-all; > }; > > v3v3: regulator-v3v3 { > @@ -127,6 +135,7 @@ v3v3: regulator-v3v3 { > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > regulator-always-on; > + bootph-all; > }; > > v2v8: regulator-v2v8 { > @@ -136,6 +145,7 @@ v2v8: regulator-v2v8 { > regulator-max-microvolt = <2800000>; > regulator-always-on; > vin-supply = <&v3v3>; > + bootph-all; > }; > > v1v8: regulator-v1v8 { > @@ -145,13 +155,86 @@ v1v8: regulator-v1v8 { > regulator-max-microvolt = <1800000>; > regulator-always-on; > vin-supply = <&v3v3>; > + bootph-all; > }; > }; > > +&bsec { > + bootph-all; > +}; > + > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &dts { > status = "okay"; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > &i2c2 { > i2c-scl-falling-time-ns = <20>; > i2c-scl-rising-time-ns = <185>; > @@ -167,6 +250,7 @@ &ipcc { > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -180,6 +264,22 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > +&rcc { > + bootph-all; > +}; > + > &rng1 { > status = "okay"; > }; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts > index 5116a7785201..7bfd7da4a8db 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts > @@ -78,6 +78,7 @@ &i2c2 { > <dc { > pinctrl-names = "default"; > pinctrl-0 = <<dc_pins>; > + bootph-some-ram; > status = "okay"; > > port { > @@ -134,19 +135,45 @@ &sdmmc1 { > pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; > st,neg-edge; > vmmc-supply = <&vdd>; > + bootph-all; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-all; > + > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + }; > +}; > + > &uart4 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + }; > +}; > + > /* J31: RS323 */ > &uart8 { > pinctrl-names = "default"; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts > index d949559be020..a1f79659d7c5 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts > @@ -36,19 +36,46 @@ &sdmmc1 { > pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; > st,neg-edge; > vmmc-supply = <&vdd>; > + bootph-all; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-all; > + > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + }; > +}; > + > &uart4 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + > + pins1 { > + bootph-all; > + }; > + > + pins2 { > + bootph-all; > + bias-pull-up; > + }; > +}; > + > /* J31: RS323 */ > &uart8 { > pinctrl-names = "default"; > diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi > index a75f50cf7123..4f6f4712d634 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi > @@ -61,6 +61,7 @@ vin: regulator-vin { > regulator-min-microvolt = <5000000>; > regulator-max-microvolt = <5000000>; > regulator-always-on; > + bootph-all; > }; > > vddcore: regulator-vddcore { > @@ -70,6 +71,7 @@ vddcore: regulator-vddcore { > regulator-max-microvolt = <1200000>; > regulator-always-on; > vin-supply = <&vin>; > + bootph-all; > }; > > vdd: regulator-vdd { > @@ -79,6 +81,7 @@ vdd: regulator-vdd { > regulator-max-microvolt = <3300000>; > regulator-always-on; > vin-supply = <&vin>; > + bootph-all; > }; > > vddq_ddr: regulator-vddq-ddr { > @@ -88,9 +91,34 @@ vddq_ddr: regulator-vddq-ddr { > regulator-max-microvolt = <1350000>; > regulator-always-on; > vin-supply = <&vin>; > + bootph-all; > }; > }; > > +&bsec { > + bootph-all; > +}; > + > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &dts { > status = "okay"; > }; > @@ -113,12 +141,61 @@ nand@0 { > }; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > &ipcc { > status = "okay"; > }; > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -132,6 +209,26 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > +&pwr_regulators { > + bootph-all; > +}; > + > +&rcc { > + bootph-all; > +}; > + > &rng1 { > status = "okay"; > }; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts > index 43280289759d..e192d033626e 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts > @@ -71,6 +71,7 @@ &m4_rproc { > &optee { > interrupt-parent = <&intc>; > interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + bootph-some-ram; > }; > > &rcc { > @@ -91,3 +92,7 @@ &rng1 { > &rtc { > clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; > }; > + > +&scmi { > + bootph-some-ram; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts > index 1ec3b8f2faa9..bf9fdf0d611c 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts > @@ -80,6 +80,7 @@ touchscreen@38 { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts > index 6f27d794d270..f053a70cb254 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts > @@ -70,6 +70,7 @@ &m4_rproc { > &optee { > interrupt-parent = <&intc>; > interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + bootph-some-ram; > }; > > &rcc { > @@ -90,3 +91,21 @@ &rng1 { > &rtc { > clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; > }; > + > +&scmi { > + bootph-some-ram; > +}; > + > +&uart4 { > + bootph-all; > +}; > + > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts > index f6c478dbd041..86919bb642fa 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts > @@ -132,6 +132,31 @@ channel@6 { > }; > }; > > + > +&bsec { > + bootph-all; > +}; > + > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &crc1 { > status = "okay"; > }; > @@ -157,6 +182,54 @@ &dts { > status = "okay"; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > &hash1 { > status = "okay"; > }; > @@ -168,7 +241,9 @@ &i2c4 { > i2c-scl-rising-time-ns = <185>; > i2c-scl-falling-time-ns = <20>; > clock-frequency = <400000>; > + bootph-all; > status = "okay"; > + > /* spare dmas for other usage */ > /delete-property/dmas; > /delete-property/dma-names; > @@ -179,6 +254,7 @@ pmic: stpmic@33 { > interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; > interrupt-controller; > #interrupt-cells = <2>; > + bootph-all; > status = "okay"; > > regulators { > @@ -314,12 +390,20 @@ watchdog { > }; > }; > > +&i2c4_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > + > &ipcc { > status = "okay"; > }; > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -335,9 +419,26 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > &pwr_regulators { > vdd-supply = <&vdd>; > vdd_3v3_usbfs-supply = <&vdd_usb>; > + bootph-all; > +}; > + > +&rcc { > + bootph-all; > }; > > &rng1 { > @@ -365,9 +466,30 @@ &sdmmc1 { > sd-uhs-sdr25; > sd-uhs-sdr50; > sd-uhs-ddr50; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_dir_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc2 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; > @@ -381,9 +503,27 @@ &sdmmc2 { > vmmc-supply = <&v3v3>; > vqmmc-supply = <&vdd>; > mmc-ddr-3_3v; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &timers6 { > status = "okay"; > /* spare dmas for other usage */ > @@ -399,11 +539,22 @@ &uart4 { > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &usbotg_hs { > vbus-supply = <&vbus_otg>; > }; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts > index 6ae391bffee5..17295d67ab85 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts > @@ -75,6 +75,7 @@ &m4_rproc { > &optee { > interrupt-parent = <&intc>; > interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + bootph-some-ram; > }; > > &rcc { > @@ -95,3 +96,7 @@ &rng1 { > &rtc { > clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; > }; > + > +&scmi { > + bootph-some-ram; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts > index 8f99c30f1af1..d43bddc42ad9 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts > @@ -231,6 +231,7 @@ &i2c5 { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > @@ -262,6 +263,7 @@ &qspi_bk2_sleep_pins_a > reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; > #address-cells = <1>; > #size-cells = <0>; > + bootph-pre-ram; > status = "okay"; > > flash0: flash@0 { > @@ -271,6 +273,7 @@ flash0: flash@0 { > spi-max-frequency = <108000000>; > #address-cells = <1>; > #size-cells = <1>; > + bootph-pre-ram; > }; > > flash1: flash@1 { > @@ -283,6 +286,41 @@ flash1: flash@1 { > }; > }; > > +&qspi_clk_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_bk1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_cs1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_bk2_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_cs2_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc3 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc3_b4_pins_a>; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts > index eada9cf257be..9f513045c559 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts > @@ -158,6 +158,7 @@ <dc { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <<dc_pins_c>; > pinctrl-1 = <<dc_sleep_pins_c>; > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi > index cf7485251490..1c5517f57ecd 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi > @@ -75,11 +75,84 @@ led-blue { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > &i2c2 { > pinctrl-names = "default"; > pinctrl-0 = <&i2c2_pins_a>; > i2c-scl-rising-time-ns = <185>; > i2c-scl-falling-time-ns = <20>; > + bootph-all; > status = "okay"; > /* spare dmas for other usage */ > /delete-property/dmas; > @@ -91,6 +164,7 @@ pmic: stpmic@33 { > interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; > interrupt-controller; > #interrupt-cells = <2>; > + bootph-all; > > regulators { > compatible = "st,stpmic1-regulators"; > @@ -218,12 +292,20 @@ watchdog { > }; > }; > > +&i2c2_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > + > &ipcc { > status = "okay"; > }; > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -237,6 +319,26 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > +&pwr_regulators { > + bootph-all; > +}; > + > +&rcc { > + bootph-all; > +}; > + > &rng1 { > status = "okay"; > }; > @@ -258,6 +360,23 @@ &sdmmc2 { > vmmc-supply = <&v3v3>; > vqmmc-supply = <&vdd>; > mmc-ddr-3_3v; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_d { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts > index a8b3f7a54703..92bc25b3f563 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts > @@ -75,14 +75,35 @@ &sdmmc1 { > st,neg-edge; > bus-width = <4>; > vmmc-supply = <&v3v3>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &uart4 { > pinctrl-names = "default"; > pinctrl-0 = <&uart4_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts > index 36e6055b5665..b404ea3752d9 100644 > --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts > +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts > @@ -131,6 +131,7 @@ i2s2_endpoint: endpoint { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi > index 89de85a2eff3..5d29c2154b46 100644 > --- a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi > @@ -87,6 +87,7 @@ &mdma1 { > &optee { > interrupt-parent = <&intc>; > interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + bootph-some-ram; > }; > > &pwr_regulators { > @@ -114,6 +115,10 @@ &rtc { > clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; > }; > > +&scmi { > + bootph-some-ram; > +}; > + > &scmi_reguls { > scmi_vddcore: regulator@3 { > reg = <VOLTD_SCMI_STPMIC1_BUCK1>; > diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts > index 8fa61e54d026..4d857b3575fd 100644 > --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts > +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts > @@ -97,6 +97,7 @@ stpmic@33 { > }; > > <dc { > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi > index 5c77202ee196..2e02cd8e7e0d 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi > @@ -201,6 +201,7 @@ <dc { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <<dc_pins_b>; > pinctrl-1 = <<dc_sleep_pins_b>; > + bootph-some-ram; > status = "okay"; > > port { > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi > index 4cc633683c6b..2c40ceaf1f33 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi > @@ -103,6 +103,10 @@ channel@1 { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > &crc1 { > status = "okay"; > }; > @@ -121,6 +125,26 @@ dac2: dac@2 { > }; > }; > > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &dts { > status = "okay"; > }; > @@ -190,6 +214,7 @@ &gpioa { > "", "", "DHCOM-K", "", > "", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpiob { > @@ -197,6 +222,7 @@ &gpiob { > "", "", "", "", > "DHCOM-Q", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpioc { > @@ -204,6 +230,7 @@ &gpioc { > "", "", "DHCOM-E", "", > "", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpiod { > @@ -211,6 +238,7 @@ &gpiod { > "", "", "DHCOM-B", "", > "", "", "", "DHCOM-F", > "DHCOM-D", "", "", ""; > + bootph-all; > }; > > &gpioe { > @@ -218,6 +246,7 @@ &gpioe { > "", "", "DHCOM-P", "", > "", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpiof { > @@ -225,6 +254,7 @@ &gpiof { > "", "", "", "", > "", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpiog { > @@ -232,6 +262,7 @@ &gpiog { > "", "", "", "", > "DHCOM-L", "", "", "", > "", "", "", ""; > + bootph-all; > }; > > &gpioh { > @@ -239,6 +270,7 @@ &gpioh { > "", "", "", "DHCOM-N", > "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", > "DHCOM-T", "", "DHCOM-S", ""; > + bootph-all; > }; > > &gpioi { > @@ -246,6 +278,20 @@ &gpioi { > "DHCOM-R", "DHCOM-M", "", "", > "", "", "", "", > "", "", "", ""; > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > + > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > }; > > &i2c4 { > @@ -253,6 +299,8 @@ &i2c4 { > pinctrl-0 = <&i2c4_pins_a>; > i2c-scl-rising-time-ns = <185>; > i2c-scl-falling-time-ns = <20>; > + bootph-all; > + bootph-pre-ram; > status = "okay"; > /* spare dmas for other usage */ > /delete-property/dmas; > @@ -269,6 +317,8 @@ pmic: stpmic@33 { > interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; > interrupt-controller; > #interrupt-cells = <2>; > + bootph-all; > + bootph-pre-ram; > > regulators { > compatible = "st,stpmic1-regulators"; > @@ -279,6 +329,7 @@ regulators { > ldo6-supply = <&v3v3>; > pwr_sw1-supply = <&bst_out>; > pwr_sw2-supply = <&bst_out>; > + bootph-pre-ram; > > vddcore: buck1 { > regulator-name = "vddcore"; > @@ -409,12 +460,20 @@ eeprom@50 { > }; > }; > > +&i2c4_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > + > &ipcc { > status = "okay"; > }; > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -428,9 +487,22 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > &pwr_regulators { > vdd-supply = <&vdd>; > vdd_3v3_usbfs-supply = <&vdd_usb>; > + bootph-all; > }; > > &qspi { > @@ -444,6 +516,7 @@ &qspi_bk1_sleep_pins_a > reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; > #address-cells = <1>; > #size-cells = <0>; > + bootph-pre-ram; > status = "okay"; > > flash0: flash@0 { > @@ -453,6 +526,28 @@ flash0: flash@0 { > spi-max-frequency = <108000000>; > #address-cells = <1>; > #size-cells = <1>; > + bootph-pre-ram; > + }; > +}; > + > +&qspi_clk_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_bk1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_cs1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > }; > }; > > @@ -469,6 +564,15 @@ &rcc { > assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; > assigned-clock-parents = <&rcc PLL4_P>; > assigned-clock-rates = <50000000>, <100000000>; > + bootph-all; > +}; > + > +®11 { > + bootph-pre-ram; > +}; > + > +®18 { > + bootph-pre-ram; > }; > > &rng1 { > @@ -495,6 +599,7 @@ &sdmmc1 { > st,ckin-gpios = <&gpioe 4 0>; > bus-width = <4>; > vmmc-supply = <&vdd_sd>; > + bootph-pre-ram; > status = "okay"; > }; > > @@ -504,11 +609,24 @@ &sdmmc1_b4_pins_a { > * - optional on SoMs with SD voltage translator > * - mandatory on SoMs without SD voltage translator > */ > + bootph-pre-ram; > pins1 { > bias-pull-up; > + bootph-pre-ram; > }; > pins2 { > bias-pull-up; > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_dir_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > }; > }; > > @@ -525,9 +643,24 @@ &sdmmc2 { > vmmc-supply = <&v3v3>; > vqmmc-supply = <&v3v3>; > mmc-ddr-3_3v; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc3 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc3_b4_pins_a>; > @@ -545,7 +678,46 @@ &sdmmc3 { > &uart4 { > pinctrl-names = "default"; > pinctrl-0 = <&uart4_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > + > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > +&usb33 { > + bootph-pre-ram; > +}; > + > +&usbotg_hs_pins_a { > + bootph-pre-ram; > +}; > + > +&usbotg_hs { > + bootph-pre-ram; > +}; > + > +&usbphyc { > + bootph-pre-ram; > +}; > + > +&usbphyc_port0 { > + bootph-pre-ram; > +}; > + > +&usbphyc_port1 { > + bootph-pre-ram; > +}; > + > +&vdd_usb { > + bootph-pre-ram; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi > index aceeff6c38ba..e7e2203ab11a 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi > @@ -355,6 +355,7 @@ <dc { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <<dc_pins_d>; > pinctrl-1 = <<dc_sleep_pins_d>; > + bootph-some-ram; > status = "okay"; > > port { > @@ -402,9 +403,30 @@ &sdmmc1 { > bus-width = <4>; > vmmc-supply = <&vdd_sd>; > vqmmc-supply = <&sd_switch>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_dir_pins_b { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc2 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; > @@ -418,9 +440,27 @@ &sdmmc2 { > st,neg-edge; > vmmc-supply = <&v3v3>; > vqmmc-supply = <&vdd_io>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_c { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc3 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc3_b4_pins_b>; > @@ -455,11 +495,22 @@ &uart4 { > label = "LS-UART1"; > pinctrl-names = "default"; > pinctrl-0 = <&uart4_pins_b>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_b { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &uart7 { > /* On Low speed expansion header */ > label = "LS-UART0"; > @@ -512,3 +563,7 @@ &usbphyc_port0 { > &usbphyc_port1 { > phy-supply = <&vdd_usb>; > }; > + > +&vdd_io { > + bootph-pre-ram; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi > index bc4ddcbdd5cf..9c6a04b4c2e3 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi > @@ -231,9 +231,30 @@ &sdmmc1 { /* MicroSD */ > bus-width = <4>; > vmmc-supply = <&vdd>; > vqmmc-supply = <&vdd>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_dir_pins_b { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc2 { /* eMMC */ > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; > @@ -246,9 +267,27 @@ &sdmmc2 { /* eMMC */ > st,neg-edge; > vmmc-supply = <&v3v3>; > vqmmc-supply = <&vdd>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_c { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc3 { /* SDIO Wi-Fi */ > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc3_b4_pins_a>; > @@ -276,11 +315,22 @@ &uart4 { > label = "UART0"; > pinctrl-names = "default"; > pinctrl-0 = <&uart4_pins_d>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_d { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &uart5 { /* X11 UART */ > label = "X11-UART5"; > pinctrl-names = "default"; > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi > index 89881a26c614..3d469e29d41a 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi > @@ -63,6 +63,30 @@ retram: retram@38000000 { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &crc1 { > status = "okay"; > }; > @@ -71,11 +95,61 @@ &dts { > status = "okay"; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > &i2c4 { > pinctrl-names = "default"; > pinctrl-0 = <&i2c4_pins_a>; > i2c-scl-rising-time-ns = <185>; > i2c-scl-falling-time-ns = <20>; > + bootph-all; > + bootph-pre-ram; > status = "okay"; > /delete-property/dmas; > /delete-property/dma-names; > @@ -86,6 +160,8 @@ pmic: stpmic@33 { > interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; > interrupt-controller; > #interrupt-cells = <2>; > + bootph-all; > + bootph-pre-ram; > status = "okay"; > > regulators { > @@ -98,6 +174,7 @@ regulators { > ldo6-supply = <&v3v3>; > pwr_sw1-supply = <&bst_out>; > pwr_sw2-supply = <&bst_out>; > + bootph-pre-ram; > > vddcore: buck1 { > regulator-name = "vddcore"; > @@ -215,12 +292,20 @@ watchdog { > }; > }; > > +&i2c4_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > + > &ipcc { > status = "okay"; > }; > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -234,9 +319,23 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > &pwr_regulators { > vdd-supply = <&vdd>; > vdd_3v3_usbfs-supply = <&vdd_usb>; > + bootph-all; > + bootph-pre-ram; > }; > > &qspi { > @@ -250,6 +349,7 @@ &qspi_bk1_sleep_pins_a > reg = <0x58003000 0x1000>, <0x70000000 0x200000>; > #address-cells = <1>; > #size-cells = <0>; > + bootph-pre-ram; > status = "okay"; > > flash0: flash@0 { > @@ -262,6 +362,35 @@ flash0: flash@0 { > }; > }; > > +&qspi_clk_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_bk1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +&qspi_cs1_pins_a { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > +®11 { > + bootph-pre-ram; > +}; > + > +®18 { > + bootph-pre-ram; > +}; > + > &rng1 { > status = "okay"; > }; > @@ -269,3 +398,31 @@ &rng1 { > &rtc { > status = "okay"; > }; > + > +&usb33 { > + bootph-pre-ram; > +}; > + > +&usbotg_hs_pins_a { > + bootph-pre-ram; > +}; > + > +&usbotg_hs { > + bootph-pre-ram; > +}; > + > +&usbphyc { > + bootph-pre-ram; > +}; > + > +&usbphyc_port0 { > + bootph-pre-ram; > +}; > + > +&usbphyc_port1 { > + bootph-pre-ram; > +}; > + > +&vdd_usb { > + bootph-pre-ram; > +}; > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi > index 6e79c4b6fe32..3b5debd0ffc9 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi > @@ -131,9 +131,30 @@ &sdmmc1 { > bus-width = <4>; > vmmc-supply = <&vdd_sd>; > vqmmc-supply = <&sd_switch>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc1_dir_pins_b { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc2 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; > @@ -147,17 +168,46 @@ &sdmmc2 { > st,neg-edge; > vmmc-supply = <&v3v3>; > vqmmc-supply = <&v3v3>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc2_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > +&sdmmc2_d47_pins_c { > + bootph-pre-ram; > + pins { > + bootph-pre-ram; > + }; > +}; > + > &uart4 { > pinctrl-names = "default"; > pinctrl-0 = <&uart4_pins_b>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_b { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &uart7 { > pinctrl-names = "default"; > pinctrl-0 = <&uart7_pins_a>; > diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi > index 8cea6facd27b..62d6417ed422 100644 > --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi > @@ -129,6 +129,10 @@ channel@19 { > }; > }; > > +&bsec { > + bootph-all; > +}; > + > &cec { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&cec_pins_b>; > @@ -136,6 +140,26 @@ &cec { > status = "okay"; > }; > > +&clk_hse { > + bootph-all; > +}; > + > +&clk_hsi { > + bootph-all; > +}; > + > +&clk_lse { > + bootph-all; > +}; > + > +&clk_lsi { > + bootph-all; > +}; > + > +&clk_csi { > + bootph-all; > +}; > + > &crc1 { > status = "okay"; > }; > @@ -144,6 +168,54 @@ &dts { > status = "okay"; > }; > > +&gpioa { > + bootph-all; > +}; > + > +&gpiob { > + bootph-all; > +}; > + > +&gpioc { > + bootph-all; > +}; > + > +&gpiod { > + bootph-all; > +}; > + > +&gpioe { > + bootph-all; > +}; > + > +&gpiof { > + bootph-all; > +}; > + > +&gpiog { > + bootph-all; > +}; > + > +&gpioh { > + bootph-all; > +}; > + > +&gpioi { > + bootph-all; > +}; > + > +&gpioj { > + bootph-all; > +}; > + > +&gpiok { > + bootph-all; > +}; > + > +&gpioz { > + bootph-all; > +}; > + > ðernet0 { > status = "okay"; > pinctrl-0 = <ðernet0_rgmii_pins_a>; > @@ -249,6 +321,7 @@ &i2c4 { > i2c-scl-rising-time-ns = <185>; > i2c-scl-falling-time-ns = <20>; > clock-frequency = <400000>; > + bootph-all; > status = "okay"; > /* spare dmas for other usage */ > /delete-property/dmas; > @@ -284,6 +357,7 @@ pmic: stpmic@33 { > interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; > interrupt-controller; > #interrupt-cells = <2>; > + bootph-all; > status = "okay"; > > regulators { > @@ -422,6 +496,13 @@ watchdog { > }; > }; > > +&i2c4_pins_a { > + bootph-all; > + pins { > + bootph-all; > + }; > +}; > + > &i2c5 { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c5_pins_a>; > @@ -458,6 +539,7 @@ &ipcc { > > &iwdg2 { > timeout-sec = <32>; > + bootph-all; > status = "okay"; > }; > > @@ -465,6 +547,7 @@ <dc { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <<dc_pins_a>; > pinctrl-1 = <<dc_sleep_pins_a>; > + bootph-some-ram; > status = "okay"; > > port { > @@ -486,9 +569,26 @@ &m4_rproc { > status = "okay"; > }; > > +&pinctrl { > + bootph-all; > +}; > + > +&pinctrl_z { > + bootph-all; > +}; > + > +&psci { > + bootph-some-ram; > +}; > + > &pwr_regulators { > vdd-supply = <&vdd>; > vdd_3v3_usbfs-supply = <&vdd_usb>; > + bootph-all; > +}; > + > +&rcc { > + bootph-all; > }; > > &rng1 { > @@ -553,9 +653,20 @@ &sdmmc1 { > st,neg-edge; > bus-width = <4>; > vmmc-supply = <&v3v3>; > + bootph-pre-ram; > status = "okay"; > }; > > +&sdmmc1_b4_pins_a { > + bootph-pre-ram; > + pins1 { > + bootph-pre-ram; > + }; > + pins2 { > + bootph-pre-ram; > + }; > +}; > + > &sdmmc3 { > pinctrl-names = "default", "opendrain", "sleep"; > pinctrl-0 = <&sdmmc3_b4_pins_a>; > @@ -676,11 +787,22 @@ &uart4 { > pinctrl-0 = <&uart4_pins_a>; > pinctrl-1 = <&uart4_sleep_pins_a>; > pinctrl-2 = <&uart4_idle_pins_a>; > + bootph-all; > /delete-property/dmas; > /delete-property/dma-names; > status = "okay"; > }; > > +&uart4_pins_a { > + bootph-all; > + pins1 { > + bootph-all; > + }; > + pins2 { > + bootph-all; > + }; > +}; > + > &uart7 { > pinctrl-names = "default", "sleep", "idle"; > pinctrl-0 = <&uart7_pins_c>; > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard ` (4 preceding siblings ...) 2026-01-23 10:14 ` [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard @ 2026-01-23 10:14 ` Patrice Chotard 5 siblings, 0 replies; 9+ messages in thread From: Patrice Chotard @ 2026-01-23 10:14 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Patrick Delaunay, Christoph Niedermaier, Marek Vasut Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel, Patrice Chotard The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 25 +++++++ arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++++++++++++++++++ 8 files changed, 335 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi index bf888d60cd4f..9e9f7f6a580f 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -47,7 +47,7 @@ ck_flexgen_51: clock-200000000 { }; firmware { - optee { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; }; @@ -70,7 +70,7 @@ scmi_reset: protocol@16 { }; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..2a003a7c3796 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,31 @@ &arm_wdt { status = "okay"; }; +&optee { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&scmi_reset { + bootph-all; +}; + &usart2 { + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 88e214d395ab..a2f93f6ccb84 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -59,7 +59,7 @@ optee: optee { interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; - scmi { + scmi: scmi { compatible = "linaro,scmi-optee"; #address-cells = <1>; #size-cells = <0>; @@ -111,7 +111,7 @@ scmi_vdda18adc: regulator@7 { }; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index c3e688068223..a055d8a2ee99 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -78,6 +78,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 = <ð1_rgmii_pins_b>; pinctrl-1 = <ð1_rgmii_sleep_pins_b>; @@ -100,6 +104,78 @@ phy1_eth1: ethernet-phy@1 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; @@ -111,6 +187,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -125,12 +205,27 @@ &sdmmc1 { status = "okay"; }; +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index a8e6e0f77b83..4eaf1de3d87f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -68,7 +68,7 @@ optee: optee { interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; - scmi { + scmi: scmi { compatible = "linaro,scmi-optee"; #address-cells = <1>; #size-cells = <0>; @@ -139,7 +139,7 @@ v2m0: v2m@48090000 { }; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 7a598f53a2a0..3ba4e6166586 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -40,4 +40,4 @@ venc: venc@480e0000 { clocks = <&rcc CK_BUS_VENC>; access-controllers = <&rifsc 90>; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index e718d888ce21..080358b134ce 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -78,6 +78,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 = <ð1_rgmii_pins_b>; pinctrl-1 = <ð1_rgmii_sleep_pins_b>; @@ -100,6 +104,86 @@ phy1_eth1: ethernet-phy@1 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; @@ -111,6 +195,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -125,12 +213,27 @@ &sdmmc1 { status = "okay"; }; +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 6e165073f732..61464076b8d5 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -130,6 +130,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + &combophy { clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>; clock-names = "apb", "ker", "pad"; @@ -216,6 +220,54 @@ phy0_eth2: ethernet-phy@1 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; @@ -300,6 +352,7 @@ timer { }; <dc { + bootph-all; status = "okay"; port { ltdc_ep0_out: endpoint { @@ -309,6 +362,7 @@ ltdc_ep0_out: endpoint { }; &lvds { + bootph-all; status = "okay"; ports { #address-cells = <1>; @@ -330,6 +384,10 @@ lvds_out0: endpoint { }; }; +&optee { + bootph-all; +}; + &pcie_ep { pinctrl-names = "default", "init"; pinctrl-0 = <&pcie_pins_a>; @@ -351,10 +409,38 @@ pcie@0,0 { }; }; +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status = "okay"; }; +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; @@ -386,6 +472,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -400,6 +490,10 @@ &sdmmc1 { status = "okay"; }; +&syscfg { + bootph-all; +}; + &spi3 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_pins_a>; @@ -477,11 +571,22 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart6_pins_a>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-03-25 14:26 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-01-23 10:14 [PATCH v5 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard 2026-01-23 10:14 ` [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard 2026-03-25 14:18 ` Patrice CHOTARD 2026-01-23 10:14 ` [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard 2026-03-25 14:25 ` Patrice CHOTARD 2026-01-23 10:14 ` [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard
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