[PATCH v1 0/2] arm64: dts: qcom: qcs8300: Add qcs8300 camss support

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* [PATCH v1 0/2] arm64: dts: qcom: qcs8300: Add qcs8300 camss support
@ 2025-02-14  9:47 Vikram Sharma
  2025-02-14  9:47 ` [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss Vikram Sharma
  2025-02-14  9:47 ` [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss Vikram Sharma
  0 siblings, 2 replies; 8+ messages in thread
From: Vikram Sharma @ 2025-02-14  9:47 UTC (permalink / raw)
  To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will
  Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
	devicetree, linux-kernel

QCS8300 is a Qualcomm SoC. This series adds bindings and devicetree to bring
up CSIPHY, TPG, CSID, VFE/RDI interfaces in QCS8300.

QCS8300 provides
- 2 x VFE, 3 RDI per VFE
- 5 x VFE Lite, 6 RDI per VFE
- 2 x CSID
- 5 x CSID Lite
- 3 x TPG
- 3 x CSIPHY

Used following tools for the sanity check of these changes.

- make CHECK_DTBS=y W=1 DT_SCHEMA_FILES=media/qcom,qcs8300-camss.yaml
- make DT_CHECKER_FLAGS=-m W=1
DT_SCHEMA_FILES=media/qcom,qcs8300-camss.yaml dt_binding_check
- make -j32 W=1
- ./scripts/checkpatch.pl

Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>

Vikram Sharma (2):
  media: dt-bindings: Add qcom,qcs8300-camss
  arm64: dts: qcom: qcs8300: Add support for camss

 .../bindings/media/qcom,qcs8300-camss.yaml    | 336 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 171 +++++++++
 2 files changed, 507 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml

-- 
2.25.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss
  2025-02-14  9:47 [PATCH v1 0/2] arm64: dts: qcom: qcs8300: Add qcs8300 camss support Vikram Sharma
@ 2025-02-14  9:47 ` Vikram Sharma
  2025-02-23 11:33   ` Krzysztof Kozlowski
  2025-02-14  9:47 ` [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss Vikram Sharma
  1 sibling, 1 reply; 8+ messages in thread
From: Vikram Sharma @ 2025-02-14  9:47 UTC (permalink / raw)
  To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will
  Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
	devicetree, linux-kernel

Add bindings for qcom,qcs8300-camss to support the camera subsystem
on QCS8300 platform.

Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
 .../bindings/media/qcom,qcs8300-camss.yaml    | 336 ++++++++++++++++++
 1 file changed, 336 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml

diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
new file mode 100644
index 000000000000..db630b91d176
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
@@ -0,0 +1,336 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS8300 CAMSS ISP
+
+maintainers:
+  - Vikram Sharma <quic_vikramsa@quicinc.com>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,qcs8300-camss
+
+  reg:
+    maxItems: 21
+
+  reg-names:
+    items:
+      - const: csid_wrapper
+      - const: csid0
+      - const: csid1
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: csid_lite2
+      - const: csid_lite3
+      - const: csid_lite4
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: tpg0
+      - const: tpg1
+      - const: tpg2
+      - const: vfe0
+      - const: vfe1
+      - const: vfe_lite0
+      - const: vfe_lite1
+      - const: vfe_lite2
+      - const: vfe_lite3
+      - const: vfe_lite4
+
+  clocks:
+    maxItems: 26
+
+  clock-names:
+    items:
+      - const: camnoc_axi
+      - const: core_ahb
+      - const: cpas_ahb
+      - const: cpas_fast_ahb_clk
+      - const: cpas_ife_lite
+      - const: cpas_vfe0
+      - const: cpas_vfe1
+      - const: csid
+      - const: csiphy0
+      - const: csiphy0_timer
+      - const: csiphy1
+      - const: csiphy1_timer
+      - const: csiphy2
+      - const: csiphy2_timer
+      - const: csiphy_rx
+      - const: gcc_axi_hf
+      - const: gcc_axi_sf
+      - const: icp_ahb
+      - const: vfe0
+      - const: vfe0_fast_ahb
+      - const: vfe1
+      - const: vfe1_fast_ahb
+      - const: vfe_lite
+      - const: vfe_lite_ahb
+      - const: vfe_lite_cphy_rx
+      - const: vfe_lite_csid
+
+  interrupts:
+    maxItems: 20
+
+  interrupt-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid-lite0
+      - const: csid-lite1
+      - const: csid-lite2
+      - const: csid-lite3
+      - const: csid-lite4
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: tpg0
+      - const: tpg1
+      - const: tpg2
+      - const: vfe0
+      - const: vfe1
+      - const: vfe-lite0
+      - const: vfe-lite1
+      - const: vfe-lite2
+      - const: vfe-lite3
+      - const: vfe-lite4
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ahb
+      - const: hf_0
+
+  iommus:
+    maxItems: 1
+
+  power-domains:
+    items:
+      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+  power-domain-names:
+    items:
+      - const: top
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    description:
+      CSI input ports.
+
+    patternProperties:
+      "^port@[0-2]+$":
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 0-2.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interrupts
+  - interrupt-names
+  - interconnects
+  - interconnect-names
+  - iommus
+  - power-domains
+  - power-domain-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        isp@ac78000 {
+            compatible = "qcom,qcs8300-camss";
+
+            reg = <0x0 0xac78000 0x0 0x1000>,
+                  <0x0 0xac7a000 0x0 0x0f01>,
+                  <0x0 0xac7c000 0x0 0x0f01>,
+                  <0x0 0xac84000 0x0 0x0f01>,
+                  <0x0 0xac88000 0x0 0x0f01>,
+                  <0x0 0xac8c000 0x0 0x0f01>,
+                  <0x0 0xac90000 0x0 0x0f01>,
+                  <0x0 0xac94000 0x0 0x0f01>,
+                  <0x0 0xac9c000 0x0 0x2000>,
+                  <0x0 0xac9e000 0x0 0x2000>,
+                  <0x0 0xaca0000 0x0 0x2000>,
+                  <0x0 0xacac000 0x0 0x0400>,
+                  <0x0 0xacad000 0x0 0x0400>,
+                  <0x0 0xacae000 0x0 0x0400>,
+                  <0x0 0xac4d000 0x0 0xd000>,
+                  <0x0 0xac5a000 0x0 0xd000>,
+                  <0x0 0xac85000 0x0 0x0d00>,
+                  <0x0 0xac89000 0x0 0x0d00>,
+                  <0x0 0xac8d000 0x0 0x0d00>,
+                  <0x0 0xac91000 0x0 0x0d00>,
+                  <0x0 0xac95000 0x0 0x0d00>;
+            reg-names = "csid_wrapper",
+                        "csid0",
+                        "csid1",
+                        "csid_lite0",
+                        "csid_lite1",
+                        "csid_lite2",
+                        "csid_lite3",
+                        "csid_lite4",
+                        "csiphy0",
+                        "csiphy1",
+                        "csiphy2",
+                        "tpg0",
+                        "tpg1",
+                        "tpg2",
+                        "vfe0",
+                        "vfe1",
+                        "vfe_lite0",
+                        "vfe_lite1",
+                        "vfe_lite2",
+                        "vfe_lite3",
+                        "vfe_lite4";
+
+            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                     <&camcc CAM_CC_CORE_AHB_CLK>,
+                     <&camcc CAM_CC_CPAS_AHB_CLK>,
+                     <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+                     <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+                     <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+                     <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+                     <&camcc CAM_CC_CSID_CLK>,
+                     <&camcc CAM_CC_CSIPHY0_CLK>,
+                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY1_CLK>,
+                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY2_CLK>,
+                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+                     <&gcc   GCC_CAMERA_HF_AXI_CLK>,
+                     <&gcc   GCC_CAMERA_SF_AXI_CLK>,
+                     <&camcc CAM_CC_ICP_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_0_CLK>,
+                     <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_1_CLK>,
+                     <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+            clock-names = "camnoc_axi",
+                          "core_ahb",
+                          "cpas_ahb",
+                          "cpas_fast_ahb_clk",
+                          "cpas_ife_lite",
+                          "cpas_vfe0",
+                          "cpas_vfe1",
+                          "csid",
+                          "csiphy0",
+                          "csiphy0_timer",
+                          "csiphy1",
+                          "csiphy1_timer",
+                          "csiphy2",
+                          "csiphy2_timer",
+                          "csiphy_rx",
+                          "gcc_axi_hf",
+                          "gcc_axi_sf",
+                          "icp_ahb",
+                          "vfe0",
+                          "vfe0_fast_ahb",
+                          "vfe1",
+                          "vfe1_fast_ahb",
+                          "vfe_lite",
+                          "vfe_lite_ahb",
+                          "vfe_lite_cphy_rx",
+                          "vfe_lite_csid";
+
+            interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "csid0",
+                              "csid1",
+                              "csid-lite0",
+                              "csid-lite1",
+                              "csid-lite2",
+                              "csid-lite3",
+                              "csid-lite4",
+                              "csiphy0",
+                              "csiphy1",
+                              "csiphy2",
+                              "tpg0",
+                              "tpg1",
+                              "tpg2",
+                              "vfe0",
+                              "vfe1",
+                              "vfe-lite0",
+                              "vfe-lite1",
+                              "vfe-lite2",
+                              "vfe-lite3",
+                              "vfe-lite4";
+
+            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+            interconnect-names = "ahb",
+                                 "hf_0";
+
+            iommus = <&apps_smmu 0x2400 0x20>;
+
+            power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+            power-domain-names = "top";
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+            };
+        };
+    };
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss
  2025-02-14  9:47 ` [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss Vikram Sharma
@ 2025-02-23 11:33   ` Krzysztof Kozlowski
       [not found]     ` <66c35bce-c657-4c12-ad02-58c995ae385a@quicinc.com>
  0 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-23 11:33 UTC (permalink / raw)
  To: Vikram Sharma
  Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
	linux-media, linux-arm-msm, devicetree, linux-kernel

On Fri, Feb 14, 2025 at 03:17:46PM +0530, Vikram Sharma wrote:
> +properties:
> +  compatible:
> +    const: qcom,qcs8300-camss
> +
> +  reg:
> +    maxItems: 21
> +
> +  reg-names:
> +    items:
> +      - const: csid_wrapper

Why different order of entries than sm8550?

> +      - const: csid0
> +      - const: csid1
> +      - const: csid_lite0
> +      - const: csid_lite1
> +      - const: csid_lite2
> +      - const: csid_lite3
> +      - const: csid_lite4
> +      - const: csiphy0
> +      - const: csiphy1
> +      - const: csiphy2
> +      - const: tpg0
> +      - const: tpg1
> +      - const: tpg2
> +      - const: vfe0
> +      - const: vfe1
> +      - const: vfe_lite0
> +      - const: vfe_lite1
> +      - const: vfe_lite2
> +      - const: vfe_lite3
> +      - const: vfe_lite4
> +
> +  clocks:
> +    maxItems: 26
> +
> +  clock-names:
> +    items:
> +      - const: camnoc_axi
> +      - const: core_ahb
> +      - const: cpas_ahb
> +      - const: cpas_fast_ahb_clk
> +      - const: cpas_ife_lite
> +      - const: cpas_vfe0
> +      - const: cpas_vfe1
> +      - const: csid
> +      - const: csiphy0
> +      - const: csiphy0_timer
> +      - const: csiphy1
> +      - const: csiphy1_timer
> +      - const: csiphy2
> +      - const: csiphy2_timer
> +      - const: csiphy_rx
> +      - const: gcc_axi_hf
> +      - const: gcc_axi_sf
> +      - const: icp_ahb
> +      - const: vfe0
> +      - const: vfe0_fast_ahb
> +      - const: vfe1
> +      - const: vfe1_fast_ahb
> +      - const: vfe_lite
> +      - const: vfe_lite_ahb
> +      - const: vfe_lite_cphy_rx
> +      - const: vfe_lite_csid
> +
> +  interrupts:
> +    maxItems: 20
> +
> +  interrupt-names:
> +    items:
> +      - const: csid0
> +      - const: csid1
> +      - const: csid-lite0
> +      - const: csid-lite1
> +      - const: csid-lite2
> +      - const: csid-lite3
> +      - const: csid-lite4

Different naming than existing variants. Keep it consistent.

> +      - const: csiphy0
> +      - const: csiphy1
> +      - const: csiphy2
> +      - const: tpg0
> +      - const: tpg1
> +      - const: tpg2
> +      - const: vfe0
> +      - const: vfe1
> +      - const: vfe-lite0
> +      - const: vfe-lite1
> +      - const: vfe-lite2
> +      - const: vfe-lite3
> +      - const: vfe-lite4

Best regards,
Krzysztof



^ permalink raw reply	[flat|nested] 8+ messages in thread

[parent not found: <66c35bce-c657-4c12-ad02-58c995ae385a@quicinc.com>]

* Re: [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss
       [not found]     ` <66c35bce-c657-4c12-ad02-58c995ae385a@quicinc.com>
@ 2025-03-18  7:16       ` Krzysztof Kozlowski
  2025-03-18 21:48         ` Bryan O'Donoghue
  0 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-03-18  7:16 UTC (permalink / raw)
  To: Vikram Sharma
  Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
	linux-media, linux-arm-msm, devicetree, linux-kernel

On 18/03/2025 06:52, Vikram Sharma wrote:
> 
> On 2/23/2025 5:03 PM, Krzysztof Kozlowski wrote:
>> On Fri, Feb 14, 2025 at 03:17:46PM +0530, Vikram Sharma wrote:
>>> +properties:
>>> +  compatible:
>>> +    const: qcom,qcs8300-camss
>>> +
>>> +  reg:
>>> +    maxItems: 21
>>> +
>>> +  reg-names:
>>> +    items:
>>> +      - const: csid_wrapper
>> Why different order of entries than sm8550?
> 
> Hi Krzysztof,
> 
> Thanks for your review.
> I did this change to address a comment from Bryan on another series.
> https://lore.kernel.org/linux-arm-msm/e152ff78-caa5-493a-88da-96a6670eb2a2@linaro.org/
> 
> Please suggest if I should keep the order same as sm8550?
If you chosen the same order as x1e80100 then it is fine, but that file
is not merged so it is your responsibility to track any differences and
be sure whatever you send is always in sync with x1e.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss
  2025-03-18  7:16       ` Krzysztof Kozlowski
@ 2025-03-18 21:48         ` Bryan O'Donoghue
  2025-03-19  6:24           ` Vikram Sharma
  0 siblings, 1 reply; 8+ messages in thread
From: Bryan O'Donoghue @ 2025-03-18 21:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Vikram Sharma
  Cc: rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, andersson,
	konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
	catalin.marinas, will, linux-arm-kernel, linux-media,
	linux-arm-msm, devicetree, linux-kernel

On 18/03/2025 07:16, Krzysztof Kozlowski wrote:
> On 18/03/2025 06:52, Vikram Sharma wrote:
>>
>> On 2/23/2025 5:03 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Feb 14, 2025 at 03:17:46PM +0530, Vikram Sharma wrote:
>>>> +properties:
>>>> +  compatible:
>>>> +    const: qcom,qcs8300-camss
>>>> +
>>>> +  reg:
>>>> +    maxItems: 21
>>>> +
>>>> +  reg-names:
>>>> +    items:
>>>> +      - const: csid_wrapper
>>> Why different order of entries than sm8550?
>>
>> Hi Krzysztof,
>>
>> Thanks for your review.
>> I did this change to address a comment from Bryan on another series.
>> https://lore.kernel.org/linux-arm-msm/e152ff78-caa5-493a-88da-96a6670eb2a2@linaro.org/
>>
>> Please suggest if I should keep the order same as sm8550?
> If you chosen the same order as x1e80100 then it is fine, but that file
> is not merged so it is your responsibility to track any differences and
> be sure whatever you send is always in sync with x1e.
> 
> Best regards,
> Krzysztof

My mistake, I hadn't realised/remembered what we merged for 8550.

Vikram, please follow latest committed example @ 8550.

---
bod


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss
  2025-03-18 21:48         ` Bryan O'Donoghue
@ 2025-03-19  6:24           ` Vikram Sharma
  0 siblings, 0 replies; 8+ messages in thread
From: Vikram Sharma @ 2025-03-19  6:24 UTC (permalink / raw)
  To: Bryan O'Donoghue, Krzysztof Kozlowski
  Cc: rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, andersson,
	konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
	catalin.marinas, will, linux-arm-kernel, linux-media,
	linux-arm-msm, devicetree, linux-kernel


On 3/19/2025 3:18 AM, Bryan O'Donoghue wrote:
> On 18/03/2025 07:16, Krzysztof Kozlowski wrote:
>> On 18/03/2025 06:52, Vikram Sharma wrote:
>>>
>>> On 2/23/2025 5:03 PM, Krzysztof Kozlowski wrote:
>>>> On Fri, Feb 14, 2025 at 03:17:46PM +0530, Vikram Sharma wrote:
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    const: qcom,qcs8300-camss
>>>>> +
>>>>> +  reg:
>>>>> +    maxItems: 21
>>>>> +
>>>>> +  reg-names:
>>>>> +    items:
>>>>> +      - const: csid_wrapper
>>>> Why different order of entries than sm8550?
>>>
>>> Hi Krzysztof,
>>>
>>> Thanks for your review.
>>> I did this change to address a comment from Bryan on another series.
>>> https://lore.kernel.org/linux-arm-msm/e152ff78-caa5-493a-88da-96a6670eb2a2@linaro.org/ 
>>>
>>>
>>> Please suggest if I should keep the order same as sm8550?
>> If you chosen the same order as x1e80100 then it is fine, but that file
>> is not merged so it is your responsibility to track any differences and
>> be sure whatever you send is always in sync with x1e.
>>
>> Best regards,
>> Krzysztof
>
> My mistake, I hadn't realised/remembered what we merged for 8550.
>
> Vikram, please follow latest committed example @ 8550.

Thanks Bryan for conclusion on this. Will keep reference dts as 8550.

>
> ---
> bod
>
Best regards,
Vikram


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss
  2025-02-14  9:47 [PATCH v1 0/2] arm64: dts: qcom: qcs8300: Add qcs8300 camss support Vikram Sharma
  2025-02-14  9:47 ` [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss Vikram Sharma
@ 2025-02-14  9:47 ` Vikram Sharma
  2025-02-23 11:34   ` Krzysztof Kozlowski
  1 sibling, 1 reply; 8+ messages in thread
From: Vikram Sharma @ 2025-02-14  9:47 UTC (permalink / raw)
  To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will
  Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
	devicetree, linux-kernel, Suresh Vankadara

Add changes to support the camera subsystem on the QCS8300.

Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 171 ++++++++++++++++++++++++++
 1 file changed, 171 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 4a057f7c0d9f..c628573d6f54 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -2942,6 +2942,177 @@ videocc: clock-controller@abf0000 {
 			#power-domain-cells = <1>;
 		};
 
+		camss: isp@ac78000 {
+			compatible = "qcom,qcs8300-camss";
+
+			reg = <0x0 0xac78000 0x0 0x1000>,
+			      <0x0 0xac7a000 0x0 0x0f01>,
+			      <0x0 0xac7c000 0x0 0x0f01>,
+			      <0x0 0xac84000 0x0 0x0f01>,
+			      <0x0 0xac88000 0x0 0x0f01>,
+			      <0x0 0xac8c000 0x0 0x0f01>,
+			      <0x0 0xac90000 0x0 0x0f01>,
+			      <0x0 0xac94000 0x0 0x0f01>,
+			      <0x0 0xac9c000 0x0 0x2000>,
+			      <0x0 0xac9e000 0x0 0x2000>,
+			      <0x0 0xaca0000 0x0 0x2000>,
+			      <0x0 0xacac000 0x0 0x0400>,
+			      <0x0 0xacad000 0x0 0x0400>,
+			      <0x0 0xacae000 0x0 0x0400>,
+			      <0x0 0xac4d000 0x0 0xf000>,
+			      <0x0 0xac60000 0x0 0xf000>,
+			      <0x0 0xac85000 0x0 0x0d00>,
+			      <0x0 0xac89000 0x0 0x0d00>,
+			      <0x0 0xac8d000 0x0 0x0d00>,
+			      <0x0 0xac91000 0x0 0x0d00>,
+			      <0x0 0xac95000 0x0 0x0d00>;
+			reg-names = "csid_wrapper",
+				    "csid0",
+				    "csid1",
+				    "csid_lite0",
+				    "csid_lite1",
+				    "csid_lite2",
+				    "csid_lite3",
+				    "csid_lite4",
+				    "csiphy0",
+				    "csiphy1",
+				    "csiphy2",
+				    "tpg0",
+				    "tpg1",
+				    "tpg2",
+				    "vfe0",
+				    "vfe1",
+				    "vfe_lite0",
+				    "vfe_lite1",
+				    "vfe_lite2",
+				    "vfe_lite3",
+				    "vfe_lite4";
+
+			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+				 <&camcc CAM_CC_CORE_AHB_CLK>,
+				 <&camcc CAM_CC_CPAS_AHB_CLK>,
+				 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+				 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+				 <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+				 <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+				 <&camcc CAM_CC_CSID_CLK>,
+				 <&camcc CAM_CC_CSIPHY0_CLK>,
+				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSIPHY1_CLK>,
+				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSIPHY2_CLK>,
+				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+				 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+				 <&gcc   GCC_CAMERA_HF_AXI_CLK>,
+				 <&gcc   GCC_CAMERA_SF_AXI_CLK>,
+				 <&camcc CAM_CC_ICP_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_0_CLK>,
+				 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_1_CLK>,
+				 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+				 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+			clock-names = "camnoc_axi",
+				      "core_ahb",
+				      "cpas_ahb",
+				      "cpas_fast_ahb_clk",
+				      "cpas_ife_lite",
+				      "cpas_vfe0",
+				      "cpas_vfe1",
+				      "csid",
+				      "csiphy0",
+				      "csiphy0_timer",
+				      "csiphy1",
+				      "csiphy1_timer",
+				      "csiphy2",
+				      "csiphy2_timer",
+				      "csiphy_rx",
+				      "gcc_axi_hf",
+				      "gcc_axi_sf",
+				      "icp_ahb",
+				      "vfe0",
+				      "vfe0_fast_ahb",
+				      "vfe1",
+				      "vfe1_fast_ahb",
+				      "vfe_lite",
+				      "vfe_lite_ahb",
+				      "vfe_lite_cphy_rx",
+				      "vfe_lite_csid";
+
+			interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "csid0",
+					  "csid1",
+					  "csid-lite0",
+					  "csid-lite1",
+					  "csid-lite2",
+					  "csid-lite3",
+					  "csid-lite4",
+					  "csiphy0",
+					  "csiphy1",
+					  "csiphy2",
+					  "tpg0",
+					  "tpg1",
+					  "tpg2",
+					  "vfe0",
+					  "vfe1",
+					  "vfe-lite0",
+					  "vfe-lite1",
+					  "vfe-lite2",
+					  "vfe-lite3",
+					  "vfe-lite4";
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ahb",
+					     "hf_0";
+
+			iommus = <&apps_smmu 0x2400 0x20>;
+
+			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+			power-domain-names = "top";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
 		camcc: clock-controller@ade0000 {
 			compatible = "qcom,qcs8300-camcc";
 			reg = <0x0 0x0ade0000 0x0 0x20000>;
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss
  2025-02-14  9:47 ` [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss Vikram Sharma
@ 2025-02-23 11:34   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-23 11:34 UTC (permalink / raw)
  To: Vikram Sharma
  Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
	conor+dt, andersson, konradybcio, hverkuil-cisco,
	cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
	linux-media, linux-arm-msm, devicetree, linux-kernel,
	Suresh Vankadara

On Fri, Feb 14, 2025 at 03:17:47PM +0530, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the QCS8300.
> 
> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 171 ++++++++++++++++++++++++++


I don't understand why DTS is combined here with media binding. There is
no driver, so this canno work.

The binding is no for arm-soc, but for media and it always goes with the
driver.

Best regards,
Krzysztof



^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2025-03-19  6:26 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-14  9:47 [PATCH v1 0/2] arm64: dts: qcom: qcs8300: Add qcs8300 camss support Vikram Sharma
2025-02-14  9:47 ` [PATCH v1 1/2] media: dt-bindings: Add qcom,qcs8300-camss Vikram Sharma
2025-02-23 11:33   ` Krzysztof Kozlowski
     [not found]     ` <66c35bce-c657-4c12-ad02-58c995ae385a@quicinc.com>
2025-03-18  7:16       ` Krzysztof Kozlowski
2025-03-18 21:48         ` Bryan O'Donoghue
2025-03-19  6:24           ` Vikram Sharma
2025-02-14  9:47 ` [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add support for camss Vikram Sharma
2025-02-23 11:34   ` Krzysztof Kozlowski

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