* [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200
@ 2026-07-21 15:57 Takuma Fujiwara
2026-07-22 4:45 ` Siddharth Vadapalli
2026-07-22 7:27 ` Manivannan Sadhasivam
0 siblings, 2 replies; 3+ messages in thread
From: Takuma Fujiwara @ 2026-07-21 15:57 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, lpieralisi, kwilczynski, mani, vigneshr, s-vadapalli,
linux-omap, linux-arm-kernel, linux-kernel
The PCIe Controller in the J7200 SoC supports a 4-lane configuration.
However, j7200_pcie_rc_data and j7200_pcie_ep_data incorrectly set
.max_lanes = 2, limiting operation to fewer lanes than the hardware
supports.
Set .max_lanes = 4 for both j7200_pcie_rc_data and j7200_pcie_ep_data to
match the hardware capability.
See J7200 Technical Reference Manual (SPRUIU1D), section 12.2.3.1.1
for further details: https://www.ti.com/lit/pdf/spruiu1d
Fixes: 3ac7f14084f5 ("PCI: j721e: Add per platform maximum lane settings")
Signed-off-by: Takuma Fujiwara <t-fujiwara1@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index b29a35fbfb5f9..a029c4e9c05f6 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -381,7 +381,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
- .max_lanes = 2,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
@@ -389,7 +389,7 @@ static const struct j721e_pcie_data j7200_pcie_ep_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.quirk_disable_flr = true,
- .max_lanes = 2,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200
2026-07-21 15:57 [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200 Takuma Fujiwara
@ 2026-07-22 4:45 ` Siddharth Vadapalli
2026-07-22 7:27 ` Manivannan Sadhasivam
1 sibling, 0 replies; 3+ messages in thread
From: Siddharth Vadapalli @ 2026-07-22 4:45 UTC (permalink / raw)
To: Takuma Fujiwara
Cc: linux-pci, bhelgaas, lpieralisi, kwilczynski, mani, vigneshr,
linux-omap, linux-arm-kernel, linux-kernel, s-vadapalli
On 21/07/26 21:27, Takuma Fujiwara wrote:
> The PCIe Controller in the J7200 SoC supports a 4-lane configuration.
> However, j7200_pcie_rc_data and j7200_pcie_ep_data incorrectly set
> .max_lanes = 2, limiting operation to fewer lanes than the hardware
> supports.
>
> Set .max_lanes = 4 for both j7200_pcie_rc_data and j7200_pcie_ep_data to
> match the hardware capability.
>
> See J7200 Technical Reference Manual (SPRUIU1D), section 12.2.3.1.1
> for further details: https://www.ti.com/lit/pdf/spruiu1d
Thank you for identifying and fixing this.
>
> Fixes: 3ac7f14084f5 ("PCI: j721e: Add per platform maximum lane settings")
> Signed-off-by: Takuma Fujiwara <t-fujiwara1@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index b29a35fbfb5f9..a029c4e9c05f6 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -381,7 +381,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> .quirk_detect_quiet_flag = true,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> - .max_lanes = 2,
> + .max_lanes = 4,
> };
>
> static const struct j721e_pcie_data j7200_pcie_ep_data = {
> @@ -389,7 +389,7 @@ static const struct j721e_pcie_data j7200_pcie_ep_data = {
> .quirk_detect_quiet_flag = true,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .quirk_disable_flr = true,
> - .max_lanes = 2,
> + .max_lanes = 4,
> };
>
> static const struct j721e_pcie_data am64_pcie_rc_data = {
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200
2026-07-21 15:57 [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200 Takuma Fujiwara
2026-07-22 4:45 ` Siddharth Vadapalli
@ 2026-07-22 7:27 ` Manivannan Sadhasivam
1 sibling, 0 replies; 3+ messages in thread
From: Manivannan Sadhasivam @ 2026-07-22 7:27 UTC (permalink / raw)
To: linux-pci, Takuma Fujiwara
Cc: bhelgaas, lpieralisi, kwilczynski, mani, vigneshr, s-vadapalli,
linux-omap, linux-arm-kernel, linux-kernel
On Tue, 21 Jul 2026 10:57:43 -0500, Takuma Fujiwara wrote:
> The PCIe Controller in the J7200 SoC supports a 4-lane configuration.
> However, j7200_pcie_rc_data and j7200_pcie_ep_data incorrectly set
> .max_lanes = 2, limiting operation to fewer lanes than the hardware
> supports.
>
> Set .max_lanes = 4 for both j7200_pcie_rc_data and j7200_pcie_ep_data to
> match the hardware capability.
>
> [...]
Applied, thanks!
[1/1] PCI: j721e: Fix incorrect max_lanes for J7200
commit: 7147a7bfce47acd48c3738130bf0bd692bfd80de
Best regards,
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-07-21 15:57 [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200 Takuma Fujiwara
2026-07-22 4:45 ` Siddharth Vadapalli
2026-07-22 7:27 ` Manivannan Sadhasivam
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