[PATCH 0/6] MediaTek MMSYS/Mute-X new-style part 1

[PATCH 0/6] MediaTek MMSYS/Mute-X new-style part 1

[AngeloGioacchino Del Regno]

This series part 1 of a huge restructuring of the entire multimedia
part of MediaTek SoCs, especially mediatek-drm, and contains only a
set of changes that don't require any simultaneous updates in the
mediatek-drm driver.

This adds support for correctly advertising the MediaTek Mute-X IP
as a source of trigger signals (because that's what it is), hence
for adding #trigger-source-cells in the Mute-X devicetree node and
for specifying a Mute-X trigger-source in all of the MTK Display
Controller components supporting or requiring one, as previously
it was kind of hacked up as a static array in the Mute-X driver,
for both MDP and DISP components, which is, well, depending on the
point of view, actually wrong.

Moreover, this goes on with the first part for a rework of MediaTek
MMSYS, which is a requirement for the upcoming huge restructuring
of the mediatek-drm driver; this starts adding boilerplate required
for setting up MMSYS entries with decoupling of "component type" to
"component instance number".

As of now, all of the components in MediaTek DRM, hence also in the
MMSYS driver, are thrown in a catch-all enumeration that does not
make any distinction between Type-Instance relationship, and it is
like so (mock-up names ahead):

DISPLAY_DITHER0
DISPLAY_DITHER1
DISPLAY_DSI0
DISPLAY_DSI1

... and so on.

Since the number of components is now becoming uncontrollably large,
the catch-all enumeration poses a big issue as the mediatek-drm driver
is allocating a huge array that will be only half full (optimistically,
because usually it's way less than half full) and with repeated ops
assignment for each and every instance of the very same Sub-IP,
effectively treating every instance of a Sub-IP like it is completely
different from one another (for example, like DSI0 and DSI1 are as
different as DITHER0 and DSI1).

This has to change. It had to change months ago, but now it has become
not only a maintenance burden, but also a... (sorry) big mess.

And well, that... especially looking forward to add support for newer
SoCs, using even more components in one pipeline, and using different
and newer components (of new types...), making the catch-all enum to
grow of another ~20 entries or more.

So, this is PART 1 of this huge restructuring, which will impact many
drivers, including soc/mediatek's mutex and mmsys, most of drm/mediatek
and, in the future, also media/mediatek/mtk-mdp3 (and eventually its
firmwareless implementation which, for components handling, will be
as complicated as mediatek-drm and, without this restructuring, would
be yet another boulder).

AngeloGioacchino Del Regno (6):
  dt-bindings: soc: mediatek: mutex: Improve title and description
  dt-bindings: soc: mediatek: mutex: Allow #trigger-source-cells
  dt-bindings: display: mediatek: Allow trigger-sources on relevant HW
  soc: mediatek: mtk-mutex: Add new functions to add/remove triggers
  soc: mediatek: mtk-mmsys: Rework routes to specify component ID
  soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table

 .../display/mediatek/mediatek,aal.yaml        |   3 +
 .../display/mediatek/mediatek,ccorr.yaml      |   3 +
 .../display/mediatek/mediatek,color.yaml      |   3 +
 .../display/mediatek/mediatek,dither.yaml     |   3 +
 .../display/mediatek/mediatek,dp.yaml         |   3 +
 .../display/mediatek/mediatek,dpi.yaml        |   3 +
 .../display/mediatek/mediatek,dsc.yaml        |   3 +
 .../display/mediatek/mediatek,dsi.yaml        |   3 +
 .../display/mediatek/mediatek,ethdr.yaml      |   3 +
 .../display/mediatek/mediatek,gamma.yaml      |   3 +
 .../display/mediatek/mediatek,merge.yaml      |   3 +
 .../display/mediatek/mediatek,od.yaml         |   3 +
 .../display/mediatek/mediatek,ovl-2l.yaml     |   3 +
 .../display/mediatek/mediatek,ovl.yaml        |   3 +
 .../display/mediatek/mediatek,padding.yaml    |   3 +
 .../display/mediatek/mediatek,postmask.yaml   |   3 +
 .../display/mediatek/mediatek,rdma.yaml       |   3 +
 .../display/mediatek/mediatek,split.yaml      |   3 +
 .../display/mediatek/mediatek,ufoe.yaml       |   3 +
 .../display/mediatek/mediatek,wdma.yaml       |   3 +
 .../bindings/soc/mediatek/mediatek,mutex.yaml |  21 +-
 drivers/soc/mediatek/mt6893-mmsys.h           |  34 +-
 drivers/soc/mediatek/mt8167-mmsys.h           |  21 +-
 drivers/soc/mediatek/mt8173-mmsys.h           |  28 +-
 drivers/soc/mediatek/mt8183-mmsys.h           |  14 +-
 drivers/soc/mediatek/mt8186-mmsys.h           |  22 +-
 drivers/soc/mediatek/mt8188-mmsys.h           |  78 ++---
 drivers/soc/mediatek/mt8192-mmsys.h           |  20 +-
 drivers/soc/mediatek/mt8195-mmsys.h           | 181 +++++------
 drivers/soc/mediatek/mt8365-mmsys.h           |  20 +-
 drivers/soc/mediatek/mtk-mmsys.h              | 299 ++++++++----------
 drivers/soc/mediatek/mtk-mutex.c              |  60 ++++
 include/linux/soc/mediatek/mtk-mutex.h        |   6 +
 33 files changed, 474 insertions(+), 390 deletions(-)

-- 
2.54.0

[PATCH 1/6] dt-bindings: soc: mediatek: mutex: Improve title and description

[AngeloGioacchino Del Regno]

Improve both the title and the description of this hardware to
disambiguate its functionality from a hardware mutex and/or from
a hwspinlock.

Though in datasheets this is called "DISP_MUTEX", the meaning is
is "Mute-X" (where "X" means "any hardware trigger signal") really
as this is what this piece of hardware does: muting or unmuting of
signals in each sub-IP of the display or other multimedia related
controllers.

Based on that, also clarify the description text, as to make sure
that the information is actually accurate.

While at it, also avoid forcing literal blocks in the description
as there is nothing in there needing that (no ascii graph or other
stuff that needs a literal block anyway), and add myself in the
list of maintainers.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../bindings/soc/mediatek/mediatek,mutex.yaml   | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 5267cfe92572..1ba086ad749d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -4,18 +4,21 @@
 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek mutex
+title: MediaTek Mute-X
 
 maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
   - Philipp Zabel <p.zabel@pengutronix.de>
 
-description: |
-  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
-  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
-  data path or MDP data path.
-  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
-  the shadow register.
+description:
+  MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals
+  like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC)
+  and others to each hardware sub-modules in the Display Controller IP or in
+  the Media Data Path (MDP) IP.
+  In some SoCs like MT2701, this hardware module may feature functionality
+  to, for example, protect shadow registers by blocking auto write triggers
+  upon operation (usually frame push) completion.
   MUTEX device node must be siblings to the central MMSYS_CONFIG node.
   For a description of the MMSYS_CONFIG binding, see
   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-- 
2.54.0

Re: [PATCH 1/6] dt-bindings: soc: mediatek: mutex: Improve title and description

[Krzysztof Kozlowski]

On Wed, Jul 01, 2026 at 02:20:38PM +0200, AngeloGioacchino Del Regno wrote:
> Improve both the title and the description of this hardware to
> disambiguate its functionality from a hardware mutex and/or from
> a hwspinlock.
> 
> Though in datasheets this is called "DISP_MUTEX", the meaning is
> is "Mute-X" (where "X" means "any hardware trigger signal") really
> as this is what this piece of hardware does: muting or unmuting of
> signals in each sub-IP of the display or other multimedia related
> controllers.
> 
> Based on that, also clarify the description text, as to make sure
> that the information is actually accurate.
> 
> While at it, also avoid forcing literal blocks in the description
> as there is nothing in there needing that (no ascii graph or other
> stuff that needs a literal block anyway), and add myself in the
> list of maintainers.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../bindings/soc/mediatek/mediatek,mutex.yaml   | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/6] dt-bindings: soc: mediatek: mutex: Allow #trigger-source-cells

[AngeloGioacchino Del Regno]

This hardware controls trigger sources, and there's even a generic
binding just for that: allow #trigger-source-cells in MuteX, so
that this is allowed to provide triggers to external HW.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml      | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 1ba086ad749d..429ea149068e 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -57,6 +57,9 @@ properties:
     items:
       - description: MUTEX Clock
 
+  '#trigger-source-cells':
+    const: 1
+
   mediatek,gce-events:
     description:
       The event id which is mapping to the specific hardware event signal
@@ -119,6 +122,7 @@ examples:
             interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_MUTEX_32K>;
+            #trigger-source-cells = <1>;
             mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
                                   <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
         };
-- 
2.54.0

Re: [PATCH 2/6] dt-bindings: soc: mediatek: mutex: Allow #trigger-source-cells

[AngeloGioacchino Del Regno]

On 7/1/26 14:20, AngeloGioacchino Del Regno wrote:
> This hardware controls trigger sources, and there's even a generic
> binding just for that: allow #trigger-source-cells in MuteX, so
> that this is allowed to provide triggers to external HW.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Hey Krzysztof, I noticed you gave your A-b/R-b on the other two bindings commits
but you skipped this.

Did you have any doubts on this one that I may clarify for you, or was it just
that this one slipped through while reviewing?

Cheers,
Angelo

> ---
>   .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml      | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> index 1ba086ad749d..429ea149068e 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> @@ -57,6 +57,9 @@ properties:
>       items:
>         - description: MUTEX Clock
>   
> +  '#trigger-source-cells':
> +    const: 1
> +
>     mediatek,gce-events:
>       description:
>         The event id which is mapping to the specific hardware event signal
> @@ -119,6 +122,7 @@ examples:
>               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
>               power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>               clocks = <&mmsys CLK_MM_MUTEX_32K>;
> +            #trigger-source-cells = <1>;
>               mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
>                                     <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
>           };

[PATCH 3/6] dt-bindings: display: mediatek: Allow trigger-sources on relevant HW

[AngeloGioacchino Del Regno]

Most of the MediaTek Display Controller hardware sub-IPs need a
specific (and reserved to them) MuteX trigger.

Since now MuteX is a trigger source, allow specifying trigger
sources in all of the display IPs that support one.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml     | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,color.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,dither.yaml  | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,dp.yaml      | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml     | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,dsc.yaml     | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml     | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,ethdr.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,od.yaml      | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml  | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml     | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,padding.yaml | 3 +++
 .../bindings/display/mediatek/mediatek,postmask.yaml           | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml    | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,split.yaml   | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,ufoe.yaml    | 3 +++
 .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml    | 3 +++
 20 files changed, 60 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 4bbea72b292a..41d60a3d8007 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -55,6 +55,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: AAL Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 5c5068128d0c..e148aa57b1b9 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -47,6 +47,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: CCORR Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 5564f4063317..7c0985d0f9ea 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -57,6 +57,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: COLOR Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 891c95be15b9..85a1746965b9 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -45,6 +45,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: DITHER Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
index 3a752a99949a..d8cfac0326ba 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -42,6 +42,9 @@ properties:
   power-domains:
     maxItems: 1
 
+  trigger-sources:
+    maxItems: 1
+
   interrupts:
     maxItems: 1
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index eb4f276e8dc4..f5be6c1e4b0e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -109,6 +109,9 @@ properties:
     items:
       - const: dpi
 
+  trigger-sources:
+    maxItems: 1
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
index c8b3e86943e4..4863db6aba6e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -43,6 +43,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     description:
       The register of client driver can be configured by gce with 4 arguments
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index b5cdfe0eaca4..a9793b274070 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -73,6 +73,9 @@ properties:
     items:
       - const: dphy
 
+  trigger-sources:
+    maxItems: 1
+
   port:
     $ref: /schemas/graph.yaml#/properties/port
     description:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 98db47894eeb..89370690ee71 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -100,6 +100,9 @@ properties:
       - const: gfx_fe1_async
       - const: vdo_be_async
 
+  trigger-sources:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     minItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index ec1054bb06d4..4d06085e6014 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -54,6 +54,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: GAMMA Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 3798a25402d3..656df51335b5 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -47,6 +47,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     minItems: 1
     maxItems: 2
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
index 930c088a722a..c912ae2493c3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
@@ -60,6 +60,9 @@ properties:
       - port@0
       - port@1
 
+  trigger-sources:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     description: describes how to locate the GCE client register
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
index ac0d924a451b..326223b36112 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -40,6 +40,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: OVL-2L Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 4df5c7b410c6..dc200068d617 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -61,6 +61,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: OVL Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
index 86787866ced0..9dac0319dd60 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -34,6 +34,9 @@ properties:
   power-domains:
     maxItems: 1
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: Padding's clocks
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
index fb6fe4742624..caef5194371f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
@@ -40,6 +40,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: POSTMASK Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index d914c06640df..13deb7c87ee6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -60,6 +60,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: RDMA Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
index 4b6ff546757e..7307a50fa30f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -40,6 +40,9 @@ properties:
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
     maxItems: 1
 
+  trigger-sources:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     description:
       The register of display function block to be set by gce. There are 4 arguments,
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
index 036a66ed42e7..31e0863dd815 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -39,6 +39,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: UFOe Clock
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index c3ed867d058d..3e6b346baa11 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -45,6 +45,9 @@ properties:
       the power controller specified by phandle. See
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
+  trigger-sources:
+    maxItems: 1
+
   clocks:
     items:
       - description: WDMA Clock
-- 
2.54.0

Re: [PATCH 3/6] dt-bindings: display: mediatek: Allow trigger-sources on relevant HW

[Krzysztof Kozlowski]

On Wed, Jul 01, 2026 at 02:20:40PM +0200, AngeloGioacchino Del Regno wrote:
> Most of the MediaTek Display Controller hardware sub-IPs need a
> specific (and reserved to them) MuteX trigger.
> 
> Since now MuteX is a trigger source, allow specifying trigger
> sources in all of the display IPs that support one.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 4/6] soc: mediatek: mtk-mutex: Add new functions to add/remove triggers

[AngeloGioacchino Del Regno]

Add new mtk_mutex_add_trigger() and mtk_mutex_remove_trigger() to
replace, in the near future, their older style equivalents such as
mtk_mutex_add_comp() and mtk_mutex_remove_comp() for the Display
Controller related MuteX triggers.

The same functions will be used to also replace the Media Data
Path 3 (MDP3) specific mtk_mutex_write_mod(), unifying the MuteX
handling across all of the currently supported multimedia-related
drivers for MediaTek SoCs.

While at it, this also takes into account the upcoming refactoring
of mtk_mmsys and mediatek-drm, which are about to migrate to a new
Component "Type -> Hardware ID" mapping, by adding a new function
parameter "hw_inst_id" to support that.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 60 ++++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mutex.h |  6 +++
 2 files changed, 66 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 6ffdcb673ae9..28715b07e668 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -960,6 +960,65 @@ void mtk_mutex_unprepare(struct mtk_mutex *mutex)
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
 
+static enum mtk_mutex_sof_id mtk_mutex_get_sof_trig(enum mtk_ddp_comp_type type,
+						    unsigned int hw_inst_id)
+{
+	switch (type) {
+	case MTK_DISP_DSI:
+		return MUTEX_SOF_DSI0 + hw_inst_id;
+	case MTK_DISP_DPI:
+		return MUTEX_SOF_DPI0 + hw_inst_id;
+	case MTK_DISP_DP_INTF:
+		return MUTEX_SOF_DP_INTF0 + hw_inst_id;
+	default:
+		break;
+	}
+
+	return DDP_MUTEX_SOF_MAX;
+}
+
+void mtk_mutex_add_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_type type,
+			   unsigned int hw_inst_id, unsigned int mtx_trig_id)
+{
+	struct mtk_mutex_ctx *ctx = container_of(mutex, struct mtk_mutex_ctx, mutex[mutex->id]);
+	enum mtk_mutex_sof_id sof_id = mtk_mutex_get_sof_trig(type, hw_inst_id);
+	const u32 offset = DISP_REG_MUTEX_MOD(ctx, mtx_trig_id, mutex->id);
+	u32 val;
+
+	if (sof_id < DDP_MUTEX_SOF_MAX) {
+		const u32 sof_offset = DISP_REG_MUTEX_SOF(ctx->data->mutex_sof_reg, mutex->id);
+
+		writel(ctx->data->mutex_sof[sof_id], ctx->regs + sof_offset);
+		return;
+	}
+
+	val = readl(ctx->regs + offset);
+	writel(val | BIT(mtx_trig_id % 32), ctx->regs + offset);
+}
+EXPORT_SYMBOL_NS_GPL(mtk_mutex_add_trigger, "MTK_MUTEX");
+
+void mtk_mutex_remove_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_type type,
+			      unsigned int hw_inst_id, unsigned int mtx_trig_id)
+{
+	struct mtk_mutex_ctx *ctx = container_of(mutex, struct mtk_mutex_ctx, mutex[mutex->id]);
+	enum mtk_mutex_sof_id sof_id = mtk_mutex_get_sof_trig(type, hw_inst_id);
+	const u32 offset = DISP_REG_MUTEX_MOD(ctx, mtx_trig_id, mutex->id);
+	u32 val;
+
+	if (sof_id < DDP_MUTEX_SOF_MAX) {
+		const u32 sof_offset = DISP_REG_MUTEX_SOF(ctx->data->mutex_sof_reg, mutex->id);
+
+		val = readl(ctx->regs + sof_offset);
+		writel(val & ~ctx->data->mutex_sof[sof_id], ctx->regs + sof_offset);
+		return;
+	}
+
+	val = readl(ctx->regs + offset);
+	writel(val & ~BIT(mtx_trig_id % 32), ctx->regs + offset);
+}
+EXPORT_SYMBOL_NS_GPL(mtk_mutex_remove_trigger, "MTK_MUTEX");
+
+/* TODO: Legacy - Scheduled for removal */
 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 			enum mtk_ddp_comp_id id)
 {
@@ -1011,6 +1070,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 }
 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
 
+/* TODO: Legacy - Scheduled for removal */
 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 			   enum mtk_ddp_comp_id id)
 {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 635218e3ac68..5368206dd62c 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -67,16 +67,22 @@ enum mtk_mutex_sof_index {
 	MUTEX_SOF_IDX_MAX		/* ALWAYS keep at the end */
 };
 
+enum mtk_ddp_comp_type;
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev);
 int mtk_mutex_prepare(struct mtk_mutex *mutex);
 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 			enum mtk_ddp_comp_id id);
+void mtk_mutex_add_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_type type,
+			   unsigned int hw_inst_id, unsigned int mtx_trig_id);
 void mtk_mutex_enable(struct mtk_mutex *mutex);
 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
 			     void *pkt);
 void mtk_mutex_disable(struct mtk_mutex *mutex);
 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 			   enum mtk_ddp_comp_id id);
+void mtk_mutex_remove_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_type type,
+			      unsigned int hw_inst_id, unsigned int mtx_trig_id);
 void mtk_mutex_unprepare(struct mtk_mutex *mutex);
 void mtk_mutex_put(struct mtk_mutex *mutex);
 void mtk_mutex_acquire(struct mtk_mutex *mutex);
-- 
2.54.0

[PATCH 5/6] soc: mediatek: mtk-mmsys: Rework routes to specify component ID

[AngeloGioacchino Del Regno]

In preparation for a refactoring of multimedia related MediaTek
drivers, including mmsys, mutex and mediatek-drm, rework all of
the MMSYS routes to specify a hardware component instance number
(or "SubID") alongside the hardware component type.

This also is one step of preparation towards the removal of the
catch-all mtk_ddp_comp_id enumeration and towards the migration
from a predefined-coupling static hardware component IDSubID
mapping (carrying around a very long enumeration and also some
multiple big arrays in mediatek-drm) to a more flexible map of
Component ID (Type) decoupled from Component SubID (HW Instance)
as then, anyway, techniques to handle components are always the
same on a type basis.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mt6893-mmsys.h |  34 +++---
 drivers/soc/mediatek/mt8167-mmsys.h |  21 ++--
 drivers/soc/mediatek/mt8173-mmsys.h |  28 ++---
 drivers/soc/mediatek/mt8183-mmsys.h |  14 +--
 drivers/soc/mediatek/mt8186-mmsys.h |  22 ++--
 drivers/soc/mediatek/mt8188-mmsys.h |  78 ++++++------
 drivers/soc/mediatek/mt8192-mmsys.h |  20 +--
 drivers/soc/mediatek/mt8195-mmsys.h | 181 ++++++++++++++--------------
 drivers/soc/mediatek/mt8365-mmsys.h |  20 +--
 drivers/soc/mediatek/mtk-mmsys.h    |  20 +--
 10 files changed, 220 insertions(+), 218 deletions(-)

diff --git a/drivers/soc/mediatek/mt6893-mmsys.h b/drivers/soc/mediatek/mt6893-mmsys.h
index c8654f591a83..2fd472b2b8c1 100644
--- a/drivers/soc/mediatek/mt6893-mmsys.h
+++ b/drivers/soc/mediatek/mt6893-mmsys.h
@@ -82,55 +82,55 @@
 #define DSI1_SEL_IN_DITHER1_MOUT			1
 
 static const struct mtk_mmsys_routes mmsys_mt6893_routing_table[] = {
-	MMSYS_ROUTE(OVL_2L0, OVL0,
+	MMSYS_ROUTE(OVL_2L, 0, OVL, 0,
 		    MT6893_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL, MT6893_DISP_SEL_IN_MASK,
 		    MT6893_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL_OVL0_2L),
-	MMSYS_ROUTE(COLOR0, CCORR,
+	MMSYS_ROUTE(COLOR, 0, CCORR, 0,
 		    MT6893_DISP_COLOR0_OUT_SEL_IN, MT6893_DISP_COLOR0_OUT_SIN_MASK,
 		    MT6893_DISP_COLOR0_OUT_SEL_IN_COLOR0),
-	MMSYS_ROUTE(CCORR, AAL0,
+	MMSYS_ROUTE(CCORR, 0, AAL, 0,
 		    MT6893_DISP_AAL0_SEL_IN, MT6893_DISP_AAL0_SEL_IN_CCORR0_SOUT,
 		    MT6893_DISP_AAL0_SEL_IN_CCORR0_SOUT),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT6893_DSI0_SEL_IN, MT6893_DSI0_SEL_IN_DITHER0_MOUT,
 		    MT6893_DSI0_SEL_IN_DITHER0_MOUT),
-	MMSYS_ROUTE(DITHER1, DSI1,
+	MMSYS_ROUTE(DITHER, 1, DSI, 1,
 		    MT6893_DSI1_SEL_IN, DSI1_SEL_IN_DITHER1_MOUT,
 		    DSI1_SEL_IN_DITHER1_MOUT),
-	MMSYS_ROUTE(RDMA4, DP_INTF0,
+	MMSYS_ROUTE(RDMA, 4, DP_INTF, 0,
 		    MT6893_DISP_DP_WRAP_SEL_IN, MT6893_DISP_DP_WRAP_MASK,
 		    MT6893_DISP_DISP_RDMA4_SOUT_DP_INTF0),
-	MMSYS_ROUTE(RDMA4, DSC0,
+	MMSYS_ROUTE(RDMA, 4, DSC, 0,
 		    MT6893_DISP_RDMA4_MERGE0_SEL_IN, MT6893_DISP_RDMA4_MERGE0_SEL_IN_MASK,
 		    MT6893_DISP_RDMA4_SOUT_RDMA4_MERGE0_SEL),
-	MMSYS_ROUTE(OVL_2L1, OVL1,
+	MMSYS_ROUTE(OVL_2L, 1, OVL, 1,
 		    MT6893_DISP_OVL1_2L_BGOUT_SOUT_SEL, MT6893_DISP_OVL1_2L_BGOUT_SOUT_MASK,
 		    MT6893_DISP_OVL1_2L_BGOUT_SOUT_OVL1),
-	MMSYS_ROUTE(CCORR, AAL0,
+	MMSYS_ROUTE(CCORR, 0, AAL, 0,
 		    MT6893_DISP_CCORR0_SOUT_SEL, MT6893_DISP_CCORR0_SOUT_AAL0_SEL,
 		    MT6893_DISP_CCORR0_SOUT_AAL0_SEL),
-	MMSYS_ROUTE(RDMA4, MERGE1,
+	MMSYS_ROUTE(RDMA, 4, MERGE, 1,
 		    MT6893_DISP_RDMA4_SOUT, MT6893_DISP_RDMA4_SOUT_MASK,
 		    MT6893_DISP_RDMA4_MERGE1_SEL),
-	MMSYS_ROUTE(RDMA4, DP_INTF0,
+	MMSYS_ROUTE(RDMA, 4, DP_INTF, 0,
 		    MT6893_DISP_RDMA4_SOUT, MT6893_DISP_RDMA4_DP_WRAP_SEL,
 		    MT6893_DISP_RDMA4_DP_WRAP_SEL),
-	MMSYS_ROUTE(DSC0, DP_INTF0,
+	MMSYS_ROUTE(DSC, 0, DP_INTF, 0,
 		    MT6893_DISP_DSC_WRAP_SOUT_SEL, MT6893_DISP_DSC_WRAP_SOUT_DP_WRAP_SEL,
 		    MT6893_DISP_DSC_WRAP_SOUT_DP_WRAP_SEL),
-	MMSYS_ROUTE(OVL_2L0, OVL0,
+	MMSYS_ROUTE(OVL_2L, 0, OVL, 0,
 		    MT6893_MMSYS_OVL_CON, MT6893_DISP_OVL0_2L_OVL0_2L_OVL1_OVL1_2L_BGOUT,
 		    MT6893_DISP_OVL0_2L_OVL0_2L_OVL1_OVL1_2L_BGOUT),
-	MMSYS_ROUTE(OVL_2L1, OVL1,
+	MMSYS_ROUTE(OVL_2L, 1, OVL, 1,
 		    MT6893_MMSYS_OVL_CON, MT6893_DISP_OVL0_2L_OVL1_2L_OVL1_OVL1_2L_BGOUT,
 		    MT6893_DISP_OVL0_2L_OVL1_2L_OVL1_OVL1_2L_BGOUT),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT6893_DISP_DITHER0_MOUT_EN, MT6893_DISP_DITHER0_MOUT_MASK,
 		    MT6893_DISP_DITHER0_MOUT_EN_DSI0_SEL),
-	MMSYS_ROUTE(DITHER1, DSI1,
+	MMSYS_ROUTE(DITHER, 1, DSI, 1,
 		    MT6893_DISP_DITHER1_MOUT_EN, MT6893_DISP_DITHER1_MOUT_MASK,
 		    MT6893_DISP_DITHER1_MOUT_EN_DSI1_SEL),
-	MMSYS_ROUTE(OVL_2L2, RDMA4,
+	MMSYS_ROUTE(OVL_2L, 2, RDMA, 4,
 		    MT6893_DISP_OVL2_2L_OUT0_MOUT, MT6893_DISP_OVL2_2L_OUT0_MOUT_MASK,
 		    MT6893_DISP_OVL2_2L_OUT0_MOUT_RDMA4),
 };
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index eef14083c47b..d579feee4212 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -10,29 +10,24 @@
 #define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x06c
 
 #define MT8167_DITHER_MOUT_EN_RDMA0			0x1
-#define MT8167_DITHER_MOUT_EN_MASK			0x7
-
 #define MT8167_RDMA0_SOUT_DSI0				0x2
-#define MT8167_RDMA0_SOUT_MASK				0x3
-
 #define MT8167_DSI0_SEL_IN_RDMA0			0x1
-#define MT8167_DSI0_SEL_IN_MASK				0x3
 
 static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
-	MMSYS_ROUTE(OVL0, COLOR0,
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
 		    MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
 		    OVL0_MOUT_EN_COLOR0),
-	MMSYS_ROUTE(DITHER0, RDMA0,
-		    MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
+	MMSYS_ROUTE(DITHER, 0, RDMA, 0,
+		    MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
 		    MT8167_DITHER_MOUT_EN_RDMA0),
-	MMSYS_ROUTE(OVL0, COLOR0,
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
 		    MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
 		    COLOR0_SEL_IN_OVL0),
-	MMSYS_ROUTE(RDMA0, DSI0,
-		    MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
+	MMSYS_ROUTE(RDMA, 0, DSI, 0,
+		    MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
 		    MT8167_DSI0_SEL_IN_RDMA0),
-	MMSYS_ROUTE(RDMA0, DSI0,
-		    MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
+	MMSYS_ROUTE(RDMA, 0, DSI, 0,
+		    MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
 		    MT8167_RDMA0_SOUT_DSI0),
 };
 
diff --git a/drivers/soc/mediatek/mt8173-mmsys.h b/drivers/soc/mediatek/mt8173-mmsys.h
index 957876d7c166..af67879ff8b4 100644
--- a/drivers/soc/mediatek/mt8173-mmsys.h
+++ b/drivers/soc/mediatek/mt8173-mmsys.h
@@ -33,46 +33,46 @@
 #define MT8173_RDMA0_SOUT_COLOR0			BIT(0)
 
 static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
-	MMSYS_ROUTE(OVL0, COLOR0,
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
 		    MT8173_OVL0_MOUT_EN_COLOR0),
-	MMSYS_ROUTE(OD0, RDMA0,
+	MMSYS_ROUTE(OD, 0, RDMA, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
 		    MT8173_OD0_MOUT_EN_RDMA0),
-	MMSYS_ROUTE(UFOE, DSI0,
+	MMSYS_ROUTE(UFOE, 0, DSI, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
 		    MT8173_UFOE_MOUT_EN_DSI0),
-	MMSYS_ROUTE(COLOR0, AAL0,
+	MMSYS_ROUTE(COLOR, 0, AAL, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
 		    0 /* SOUT to AAL */),
-	MMSYS_ROUTE(RDMA0, UFOE,
+	MMSYS_ROUTE(RDMA, 0, UFOE, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
 		    0 /* SOUT to UFOE */),
-	MMSYS_ROUTE(OVL0, COLOR0,
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
 		    MT8173_COLOR0_SEL_IN_OVL0),
-	MMSYS_ROUTE(AAL0, COLOR0,
+	MMSYS_ROUTE(AAL, 0, COLOR, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
 		    0 /* SEL_IN from COLOR0 */),
-	MMSYS_ROUTE(RDMA0, UFOE,
+	MMSYS_ROUTE(RDMA, 0, UFOE, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
 		    0 /* SEL_IN from RDMA0 */),
-	MMSYS_ROUTE(UFOE, DSI0,
+	MMSYS_ROUTE(UFOE, 0, DSI, 0,
 		    MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
 		    0 /* SEL_IN from UFOE */),
-	MMSYS_ROUTE(OVL1, COLOR1,
+	MMSYS_ROUTE(OVL, 1, COLOR, 1,
 		    MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
 		    MT8173_OVL1_MOUT_EN_COLOR1),
-	MMSYS_ROUTE(GAMMA, RDMA1,
+	MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
 		    MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
 		    MT8173_GAMMA_MOUT_EN_RDMA1),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
 		    RDMA1_SOUT_DPI0),
-	MMSYS_ROUTE(OVL1, COLOR1,
+	MMSYS_ROUTE(OVL, 1, COLOR, 1,
 		    MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
 		    COLOR1_SEL_IN_OVL1),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
 		    MT8173_DPI0_SEL_IN_RDMA1),
 };
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 123384958c4b..cf221ef203d2 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -28,25 +28,25 @@
 #define MT8183_MMSYS_SW0_RST_B			0x140
 
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
-	MMSYS_ROUTE(OVL0, OVL_2L0,
+	MMSYS_ROUTE(OVL, 0, OVL_2L, 0,
 		    MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
 		    MT8183_OVL0_MOUT_EN_OVL0_2L),
-	MMSYS_ROUTE(OVL_2L0, RDMA0,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
 		    MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
 		    MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
-	MMSYS_ROUTE(OVL_2L1, RDMA1,
+	MMSYS_ROUTE(OVL_2L, 1, RDMA, 1,
 		    MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
 		    MT8183_OVL1_2L_MOUT_EN_RDMA1),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
 		    MT8183_DITHER0_MOUT_IN_DSI0),
-	MMSYS_ROUTE(OVL_2L0, RDMA0,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
 		    MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
 		    MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
 		    MT8183_DPI0_SEL_IN_RDMA1),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
 		    MT8183_RDMA0_SOUT_COLOR0),
 };
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index 354664be72bd..0c6941be6fa5 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -63,37 +63,37 @@
 #define MT8186_MMSYS_SW0_RST_B				0x160
 
 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
 		    MT8186_OVL0_MOUT_TO_RDMA0),
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
 		    MT8186_RDMA0_FROM_OVL0),
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
 		    MT8186_OVL0_GO_BLEND),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
 		    MT8186_RDMA0_SOUT_TO_COLOR0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
 		    MT8186_DITHER0_MOUT_TO_DSI0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
 		    MT8186_DSI0_FROM_DITHER0),
-	MMSYS_ROUTE(OVL_2L0, RDMA1,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
 		    MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
 		    MT8186_OVL0_2L_MOUT_TO_RDMA1),
-	MMSYS_ROUTE(OVL_2L0, RDMA1,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
 		    MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
 		    MT8186_RDMA1_FROM_OVL0_2L),
-	MMSYS_ROUTE(OVL_2L0, RDMA1,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
 		    MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
 		    MT8186_OVL0_2L_GO_BLEND),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
 		    MT8186_RDMA1_MOUT_TO_DPI0_SEL),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
 		    MT8186_DPI0_FROM_RDMA1),
 };
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 99080afead7e..c70c4b462381 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -202,124 +202,124 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
 };
 
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
 		    MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0),
-	MMSYS_ROUTE(OVL0, WDMA0,
+	MMSYS_ROUTE(OVL, 0, WDMA, 0,
 		    MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
 		    MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0),
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
 		    MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
 		    MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(DITHER0, MERGE0,
+	MMSYS_ROUTE(DITHER, 0, MERGE, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
 		    MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(DITHER0, DSC0,
+	MMSYS_ROUTE(DITHER, 0, DSC, 0,
 		    MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
 		    MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(DITHER0, DP_INTF0,
+	MMSYS_ROUTE(DITHER, 0, DP_INTF, 0,
 		    MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
 		    MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(DSC0, MERGE0,
+	MMSYS_ROUTE(DSC, 0, MERGE, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
 		    MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(MERGE0, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
 		    MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
 		    MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
-	MMSYS_ROUTE(DSC0, DSI0,
+	MMSYS_ROUTE(DSC, 0, DSI, 0,
 		    MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
 		    MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0),
 		    MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0),
-	MMSYS_ROUTE(DITHER0, DSC0,
+	MMSYS_ROUTE(DITHER, 0, DSC, 0,
 		    MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8188_SOUT_DISP_DITHER0_TO_DSI0),
-	MMSYS_ROUTE(DITHER0, MERGE0,
+	MMSYS_ROUTE(DITHER, 0, MERGE, 0,
 		    MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0),
-	MMSYS_ROUTE(DITHER0, DP_INTF0,
+	MMSYS_ROUTE(DITHER, 0, DP_INTF, 0,
 		    MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0),
-	MMSYS_ROUTE(MERGE0, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
 		    MT8188_SOUT_VPP_MERGE_TO_DP_INTF0),
-	MMSYS_ROUTE(MERGE0, DPI0,
+	MMSYS_ROUTE(MERGE, 0, DPI, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
 		    MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(MERGE0, WDMA0,
+	MMSYS_ROUTE(MERGE, 0, WDMA, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
 		    MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0),
-	MMSYS_ROUTE(MERGE0, DSC0,
+	MMSYS_ROUTE(MERGE, 0, DSC, 0,
 		    MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
 		    MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
-	MMSYS_ROUTE(DSC0, DSI0,
+	MMSYS_ROUTE(DSC, 0, DSI, 0,
 		    MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0),
-	MMSYS_ROUTE(DSC0, MERGE0,
+	MMSYS_ROUTE(DSC, 0, MERGE, 0,
 		    MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
 };
 
 static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
-	MMSYS_ROUTE(MDP_RDMA0, MERGE1,
+	MMSYS_ROUTE(MDP_RDMA, 0, MERGE, 1,
 		    MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
 		    MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
-	MMSYS_ROUTE(MDP_RDMA1, MERGE1,
+	MMSYS_ROUTE(MDP_RDMA, 1, MERGE, 1,
 		    MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
 		    MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
-	MMSYS_ROUTE(MDP_RDMA2, MERGE2,
+	MMSYS_ROUTE(MDP_RDMA, 2, MERGE, 2,
 		    MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
 		    MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
-	MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8188_SOUT_TO_MIXER_IN1_SEL),
-	MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8188_SOUT_TO_MIXER_IN2_SEL),
-	MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8188_SOUT_TO_MIXER_IN3_SEL),
-	MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8188_SOUT_TO_MIXER_IN4_SEL),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
 		    MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
-	MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
 		    MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
 		    MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
 		    MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
 		    MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
 		    MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
 		    MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
 		    MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
-	MMSYS_ROUTE(MERGE5, DPI1,
+	MMSYS_ROUTE(MERGE, 5, DPI, 1,
 		    MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
 		    MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
-	MMSYS_ROUTE(MERGE5, DPI1,
+	MMSYS_ROUTE(MERGE, 5, DPI, 1,
 		    MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
 		    MT8188_MERGE4_SOUT_TO_DPI1_SEL),
-	MMSYS_ROUTE(MERGE5, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
 		    MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
 		    MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
-	MMSYS_ROUTE(MERGE5, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
 		    MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
 		    MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL),
 };
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 7cafa2455fd0..37ced5152ba7 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -31,34 +31,34 @@
 #define MT8192_DSI0_SEL_IN_DITHER0			0x1
 
 static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
-	MMSYS_ROUTE(OVL_2L0, RDMA0,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
 		    MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
 		    MT8192_OVL0_MOUT_EN_DISP_RDMA0),
-	MMSYS_ROUTE(OVL_2L2, RDMA4,
+	MMSYS_ROUTE(OVL_2L, 2, RDMA, 4,
 		    MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
 		    MT8192_OVL2_2L_MOUT_EN_RDMA4),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
 		    MT8192_DITHER0_MOUT_IN_DSI0),
-	MMSYS_ROUTE(OVL_2L0, RDMA0,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
 		    MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
 		    MT8192_RDMA0_SEL_IN_OVL0_2L),
-	MMSYS_ROUTE(CCORR, AAL0,
+	MMSYS_ROUTE(CCORR, 0, AAL, 0,
 		    MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
 		    MT8192_AAL0_SEL_IN_CCORR0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
 		    MT8192_DSI0_SEL_IN_DITHER0),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
 		    MT8192_RDMA0_SOUT_COLOR0),
-	MMSYS_ROUTE(CCORR, AAL0,
+	MMSYS_ROUTE(CCORR, 0, AAL, 0,
 		    MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
 		    MT8192_CCORR0_SOUT_AAL0),
-	MMSYS_ROUTE(OVL0, OVL_2L0,
+	MMSYS_ROUTE(OVL, 0, OVL_2L, 0,
 		    MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
 		    MT8192_DISP_OVL0_GO_BG),
-	MMSYS_ROUTE(OVL_2L0, RDMA0,
+	MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
 		    MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
 		    MT8192_DISP_OVL0_2L_GO_BLEND),
 };
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index f69929a2a4d4..3a58b9b74282 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -160,278 +160,279 @@
 #define MT8195_SVPP3_MDP_RSZ					BIT(5)
 
 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
 		    MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0),
-	MMSYS_ROUTE(OVL0, WDMA0,
+	MMSYS_ROUTE(OVL, 0, WDMA, 0,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
 		    MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0),
-	MMSYS_ROUTE(OVL0, OVL1,
+	MMSYS_ROUTE(OVL, 0, OVL, 1,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
 		    MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1),
-	MMSYS_ROUTE(OVL1, RDMA1,
+	MMSYS_ROUTE(OVL, 1, RDMA, 1,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
 		    MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1),
-	MMSYS_ROUTE(OVL1, WDMA1,
+	MMSYS_ROUTE(OVL, 1, WDMA, 1,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
 		    MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1),
-	MMSYS_ROUTE(OVL1, OVL0,
+	MMSYS_ROUTE(OVL, 1, OVL, 0,
 		    MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
 		    MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0),
-	MMSYS_ROUTE(DSC0, MERGE0,
+	MMSYS_ROUTE(DSC, 0, MERGE, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		    MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(DITHER1, MERGE0,
+	MMSYS_ROUTE(DITHER, 1, MERGE, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		    MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(MERGE5, MERGE0,
+	MMSYS_ROUTE(MERGE, 5, MERGE, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		    MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0),
-	MMSYS_ROUTE(DITHER0, DSC0,
+	MMSYS_ROUTE(DITHER, 0, DSC, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(MERGE0, DSC0,
+	MMSYS_ROUTE(MERGE, 0, DSC, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE),
-	MMSYS_ROUTE(DITHER1, DSC1,
+	MMSYS_ROUTE(DITHER, 1, DSC, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(MERGE0, DSC1,
+	MMSYS_ROUTE(MERGE, 0, DSC, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE),
-	MMSYS_ROUTE(MERGE0, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
-	MMSYS_ROUTE(MERGE0, DPI0,
+	MMSYS_ROUTE(MERGE, 0, DPI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
-	MMSYS_ROUTE(MERGE0, DPI1,
+	MMSYS_ROUTE(MERGE, 0, DPI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
-	MMSYS_ROUTE(DSC1, DP_INTF1,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DSC1, DPI0,
+	MMSYS_ROUTE(DSC, 1, DPI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DSC1, DPI1,
+	MMSYS_ROUTE(DSC, 1, DPI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DSC0, DP_INTF1,
+	MMSYS_ROUTE(DSC, 0, DP_INTF, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(DSC0, DPI0,
+	MMSYS_ROUTE(DSC, 0, DPI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(DSC0, DPI1,
+	MMSYS_ROUTE(DSC, 0, DPI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
 		    MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(DSC1, DP_INTF0,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
 		    MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(MERGE0, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
 		    MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
-	MMSYS_ROUTE(MERGE5, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
 		    MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0),
-	MMSYS_ROUTE(DSC0, DSI0,
+	MMSYS_ROUTE(DSC, 0, DSI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		    MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		    MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0),
-	MMSYS_ROUTE(DSC1, DSI1,
+	MMSYS_ROUTE(DSC, 1, DSI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
 		    MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(MERGE0, DSI1,
+	MMSYS_ROUTE(MERGE, 0, DSI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
 		    MT8195_SEL_IN_DSI1_FROM_VPP_MERGE),
-	MMSYS_ROUTE(OVL1, WDMA1,
+	MMSYS_ROUTE(OVL, 1, WDMA, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
 		    MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1),
-	MMSYS_ROUTE(MERGE0, WDMA1,
+	MMSYS_ROUTE(MERGE, 0, WDMA, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
 		    MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE),
-	MMSYS_ROUTE(DSC1, DSI1,
+	MMSYS_ROUTE(DSC, 1, DSI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC1, DP_INTF0,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC1, DP_INTF1,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC1, DPI0,
+	MMSYS_ROUTE(DSC, 1, DPI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC1, DPI1,
+	MMSYS_ROUTE(DSC, 1, DPI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC1, MERGE0,
+	MMSYS_ROUTE(DSC, 1, MERGE, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DITHER1, DSI1,
+	MMSYS_ROUTE(DITHER, 1, DSI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(DITHER1, DP_INTF0,
+	MMSYS_ROUTE(DITHER, 1, DP_INTF, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(DITHER1, DPI0,
+	MMSYS_ROUTE(DITHER, 1, DPI, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(DITHER1, DPI1,
+	MMSYS_ROUTE(DITHER, 1, DPI, 1,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
 		    MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
-	MMSYS_ROUTE(OVL0, WDMA0,
+	MMSYS_ROUTE(OVL, 0, WDMA, 0,
 		    MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
 		    MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0),
-	MMSYS_ROUTE(DITHER0, DSC0,
+	MMSYS_ROUTE(DITHER, 0, DSC, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER0_TO_DSI0),
-	MMSYS_ROUTE(DITHER1, DSC1,
+	MMSYS_ROUTE(DITHER, 1, DSC, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DITHER1, MERGE0,
+	MMSYS_ROUTE(DITHER, 1, MERGE, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE),
-	MMSYS_ROUTE(DITHER1, DSI1,
+	MMSYS_ROUTE(DITHER, 1, DSI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DITHER1, DP_INTF0,
+	MMSYS_ROUTE(DITHER, 1, DP_INTF, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DITHER1, DP_INTF1,
+	MMSYS_ROUTE(DITHER, 1, DP_INTF, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DITHER1, DPI0,
+	MMSYS_ROUTE(DITHER, 1, DPI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(DITHER1, DPI1,
+	MMSYS_ROUTE(DITHER, 1, DPI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
 		    MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
-	MMSYS_ROUTE(MERGE5, MERGE0,
+	MMSYS_ROUTE(MERGE, 5, MERGE, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
 		    MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE),
-	MMSYS_ROUTE(MERGE5, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
 		    MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0),
-	MMSYS_ROUTE(MERGE0, DSI1,
+	MMSYS_ROUTE(MERGE, 0, DSI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_DSI1),
-	MMSYS_ROUTE(MERGE0, DP_INTF0,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_DP_INTF0),
-	MMSYS_ROUTE(MERGE0, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 0, DP_INTF, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(MERGE0, DPI0,
+	MMSYS_ROUTE(MERGE, 0, DPI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(MERGE0, DPI1,
+	MMSYS_ROUTE(MERGE, 0, DPI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(MERGE0, WDMA1,
+	MMSYS_ROUTE(MERGE, 0, WDMA, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1),
-	MMSYS_ROUTE(MERGE0, DSC0,
+	MMSYS_ROUTE(MERGE, 0, DSC, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
-	MMSYS_ROUTE(MERGE0, DSC1,
+	MMSYS_ROUTE(MERGE, 0, DSC, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
 		    MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN),
-	MMSYS_ROUTE(DSC0, DSI0,
+	MMSYS_ROUTE(DSC, 0, DSI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0),
-	MMSYS_ROUTE(DSC0, DP_INTF1,
+	MMSYS_ROUTE(DSC, 0, DP_INTF, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
-	MMSYS_ROUTE(DSC0, DPI0,
+	MMSYS_ROUTE(DSC, 0, DPI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
-	MMSYS_ROUTE(DSC0, DPI1,
+	MMSYS_ROUTE(DSC, 0, DPI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
-	MMSYS_ROUTE(DSC0, MERGE0,
+	MMSYS_ROUTE(DSC, 0, MERGE, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
-	MMSYS_ROUTE(DSC1, DSI1,
+	MMSYS_ROUTE(DSC, 1, DSI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1),
-	MMSYS_ROUTE(DSC1, DP_INTF0,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0),
-	MMSYS_ROUTE(DSC1, DP_INTF1,
+	MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(DSC1, DPI0,
+	MMSYS_ROUTE(DSC, 1, DPI, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(DSC1, DPI1,
+	MMSYS_ROUTE(DSC, 1, DPI, 1,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
-	MMSYS_ROUTE(DSC1, MERGE0,
+	MMSYS_ROUTE(DSC, 1, MERGE, 0,
 		    MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
 		    MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE),
 };
 
 static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
-	MMSYS_ROUTE(MDP_RDMA0, MERGE1,
+	MMSYS_ROUTE(MDP_RDMA, 0, MERGE, 1,
 		    MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
 		    MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
-	MMSYS_ROUTE(MDP_RDMA1, MERGE1,
+	MMSYS_ROUTE(MDP_RDMA, 1, MERGE, 1,
 		    MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
 		    MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
-	MMSYS_ROUTE(MDP_RDMA2, MERGE2,
+	MMSYS_ROUTE(MDP_RDMA, 2, MERGE, 2,
 		    MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
 		    MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
-	MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_SOUT_TO_MIXER_IN1_SEL),
-	MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_SOUT_TO_MIXER_IN2_SEL),
-	MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_SOUT_TO_MIXER_IN3_SEL),
-	MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_SOUT_TO_MIXER_IN4_SEL),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
 		    MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
-	MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
 		    MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
 		    MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
 		    MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
-	MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
+	MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
 		    MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
 		    MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
 		    MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
-	MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
+	MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
 		    MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
 		    MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
-	MMSYS_ROUTE(MERGE5, DPI1,
+	MMSYS_ROUTE(MERGE, 5, DPI, 1,
 		    MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
 		    MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
-	MMSYS_ROUTE(MERGE5, DPI1,
+	MMSYS_ROUTE(MERGE, 5, DPI, 1,
 		    MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_MERGE4_SOUT_TO_DPI1_SEL),
-	MMSYS_ROUTE(MERGE5, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
 		    MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
 		    MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
-	MMSYS_ROUTE(MERGE5, DP_INTF1,
+	MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
 		    MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
 		    MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL),
 };
+
 #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 533a3fd0923b..b438ab7ae00b 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -28,35 +28,35 @@
 #define MT8365_DPI0_SEL_IN_RDMA1			0x0
 
 static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
-	MMSYS_ROUTE(OVL0, RDMA0,
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
-	MMSYS_ROUTE(COLOR0, CCORR,
+	MMSYS_ROUTE(COLOR, 0, CCORR, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
-	MMSYS_ROUTE(DITHER0, DSI0,
+	MMSYS_ROUTE(DITHER, 0, DSI, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
-	MMSYS_ROUTE(RDMA0, COLOR0,
+	MMSYS_ROUTE(RDMA, 0, COLOR, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
 		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
 		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
-	MMSYS_ROUTE(RDMA1, DPI0,
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
 		    MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index fe628d5f5198..b37d859b6c14 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -80,18 +80,24 @@
 
 #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
 
+/* Temporary compatibility definitions */
+#define DDP_COMPONENT_CCORR0		DDP_COMPONENT_CCORR
+#define DDP_COMPONENT_UFOE0		DDP_COMPONENT_UFOE
+#define DDP_COMPONENT_GAMMA0		DDP_COMPONENT_GAMMA
+#define DDP_COMPONENT_ETHDR_MIXER0	DDP_COMPONENT_ETHDR_MIXER
+
 /*
  * This macro adds a compile time check to make sure that the in/out
  * selection bit(s) fit in the register mask, similar to bitfield
  * macros, but this does not transform the value.
  */
-#define MMSYS_ROUTE(from, to, reg_addr, reg_mask, selection)		\
-	{ DDP_COMPONENT_##from, DDP_COMPONENT_##to, reg_addr, reg_mask,	\
-	  (__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") +	\
-	   __BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection),		\
-				   #selection " does not fit in "	\
-				   #reg_mask) +				\
-	   (selection))							\
+#define MMSYS_ROUTE(from, fsid, to, tsid, reg_addr, reg_mask, selection)	\
+	{ DDP_COMPONENT_##from##fsid, DDP_COMPONENT_##to##tsid, reg_addr, reg_mask,	\
+	  (__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") +		\
+	   __BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection),			\
+				   #selection " does not fit in "		\
+				   #reg_mask) +					\
+	   (selection))								\
 	}
 
 struct mtk_mmsys_routes {
-- 
2.54.0

[PATCH 6/6] soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table

[AngeloGioacchino Del Regno]

All of the mtk_mmsys_routes tables for all SoCs were converted to
use the MMSYS_ROUTE() macro but the default one used for MT2701,
MT2712 and SoCs from that generation was not: convert this one as
well.

This brings no functional change.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mtk-mmsys.h | 279 +++++++++++++------------------
 1 file changed, 114 insertions(+), 165 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index b37d859b6c14..d534d43aad6f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -157,171 +157,120 @@ struct mtk_mmsys_driver_data {
  * to an independent table.
  */
 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
-	{
-		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
-		BLS_TO_DSI_RDMA1_TO_DPI1
-	}, {
-		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
-		DSI_SEL_IN_BLS
-	}, {
-		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
-		BLS_TO_DPI_RDMA1_TO_DSI
-	}, {
-		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
-		DSI_SEL_IN_RDMA
-	}, {
-		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
-		DPI_SEL_IN_BLS
-	}, {
-		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
-		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
-		GAMMA_MOUT_EN_RDMA1
-	}, {
-		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
-		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
-		OD_MOUT_EN_RDMA0
-	}, {
-		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
-		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
-		OD1_MOUT_EN_RDMA1
-	}, {
-		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
-		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
-		OVL0_MOUT_EN_COLOR0
-	}, {
-		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
-		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
-		COLOR0_SEL_IN_OVL0
-	}, {
-		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
-		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
-		OVL_MOUT_EN_RDMA
-	}, {
-		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
-		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
-		OVL1_MOUT_EN_COLOR1
-	}, {
-		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
-		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
-		COLOR1_SEL_IN_OVL1
-	}, {
-		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
-		RDMA0_SOUT_DPI0
-	}, {
-		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
-		RDMA0_SOUT_DPI1
-	}, {
-		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
-		RDMA0_SOUT_DSI1
-	}, {
-		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
-		RDMA0_SOUT_DSI2
-	}, {
-		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
-		RDMA0_SOUT_DSI3
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
-		RDMA1_SOUT_DPI0
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
-		DPI0_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
-		RDMA1_SOUT_DPI1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
-		DPI1_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
-		DSI0_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
-		RDMA1_SOUT_DSI1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
-		DSI1_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
-		RDMA1_SOUT_DSI2
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
-		DSI2_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
-		RDMA1_SOUT_DSI3
-	}, {
-		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
-		DSI3_SEL_IN_RDMA1
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
-		RDMA2_SOUT_DPI0
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
-		DPI0_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
-		RDMA2_SOUT_DPI1
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
-		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
-		DPI1_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
-		DSI0_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
-		RDMA2_SOUT_DSI1
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
-		DSI1_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
-		RDMA2_SOUT_DSI2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
-		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
-		DSI2_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
-		RDMA2_SOUT_DSI3
-	}, {
-		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
-		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
-		DSI3_SEL_IN_RDMA2
-	}, {
-		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
-		DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
-		UFOE_MOUT_EN_DSI0
-	}
+	MMSYS_ROUTE(BLS, 0, DSI, 0,
+		    DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+		    BLS_TO_DSI_RDMA1_TO_DPI1),
+	MMSYS_ROUTE(BLS, 0, DSI, 0,
+		    DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+		    DSI_SEL_IN_BLS),
+	MMSYS_ROUTE(BLS, 0, DPI, 0,
+		    DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+		    BLS_TO_DPI_RDMA1_TO_DSI),
+	MMSYS_ROUTE(BLS, 0, DPI, 0,
+		    DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+		    DSI_SEL_IN_RDMA),
+	MMSYS_ROUTE(BLS, 0, DPI, 0,
+		    DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
+		    DPI_SEL_IN_BLS),
+	MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
+		    DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
+		    GAMMA_MOUT_EN_RDMA1),
+	MMSYS_ROUTE(OD, 0, RDMA, 0,
+		    DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
+		    OD_MOUT_EN_RDMA0),
+	MMSYS_ROUTE(OD, 1, RDMA, 1,
+		    DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
+		    OD1_MOUT_EN_RDMA1),
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
+		    DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
+		    OVL0_MOUT_EN_COLOR0),
+	MMSYS_ROUTE(OVL, 0, COLOR, 0,
+		    DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
+		    COLOR0_SEL_IN_OVL0),
+	MMSYS_ROUTE(OVL, 0, RDMA, 0,
+		    DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
+		    OVL_MOUT_EN_RDMA),
+	MMSYS_ROUTE(OVL, 1, COLOR, 1,
+		    DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
+		    OVL1_MOUT_EN_COLOR1),
+	MMSYS_ROUTE(OVL, 1, COLOR, 1,
+		    DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
+		    COLOR1_SEL_IN_OVL1),
+	MMSYS_ROUTE(RDMA, 0, DPI, 0,
+		    DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		    RDMA0_SOUT_DPI0),
+	MMSYS_ROUTE(RDMA, 0, DPI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		    RDMA0_SOUT_DPI1),
+	MMSYS_ROUTE(RDMA, 0, DSI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		    RDMA0_SOUT_DSI1),
+	MMSYS_ROUTE(RDMA, 0, DSI, 2,
+		    DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		    RDMA0_SOUT_DSI2),
+	MMSYS_ROUTE(RDMA, 0, DSI, 3,
+		    DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+		    RDMA0_SOUT_DSI3),
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
+		    DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		    RDMA1_SOUT_DPI0),
+	MMSYS_ROUTE(RDMA, 1, DPI, 0,
+		    DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+		    DPI0_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 1, DPI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		    RDMA1_SOUT_DPI1),
+	MMSYS_ROUTE(RDMA, 1, DPI, 1,
+		    DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+		    DPI1_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 1, DSI, 0,
+		    DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+		    DSI0_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 1, DSI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		    RDMA1_SOUT_DSI1),
+	MMSYS_ROUTE(RDMA, 1, DSI, 1,
+		    DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+		    DSI1_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 1, DSI, 2,
+		    DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		    RDMA1_SOUT_DSI2),
+	MMSYS_ROUTE(RDMA, 1, DSI, 2,
+		    DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+		    DSI2_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 1, DSI, 3,
+		    DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+		    RDMA1_SOUT_DSI3),
+	MMSYS_ROUTE(RDMA, 1, DSI, 3,
+		    DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
+		    DSI3_SEL_IN_RDMA1),
+	MMSYS_ROUTE(RDMA, 2, DPI, 0,
+		    DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		    RDMA2_SOUT_DPI0),
+	MMSYS_ROUTE(RDMA, 2, DPI, 0,
+		    DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+		    DPI0_SEL_IN_RDMA2),
+	MMSYS_ROUTE(RDMA, 2, DPI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		    RDMA2_SOUT_DPI1),
+	MMSYS_ROUTE(RDMA, 2, DPI, 1,
+		    DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+		    DPI1_SEL_IN_RDMA2),
+	MMSYS_ROUTE(RDMA, 2, DSI, 0,
+		    DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+		    DSI0_SEL_IN_RDMA2),
+	MMSYS_ROUTE(RDMA, 2, DSI, 1,
+		    DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		    RDMA2_SOUT_DSI1),
+	MMSYS_ROUTE(RDMA, 2, DSI, 1,
+		    DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+		    DSI1_SEL_IN_RDMA2),
+	MMSYS_ROUTE(RDMA, 2, DSI, 2,
+		    DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+		    RDMA2_SOUT_DSI2),
+	MMSYS_ROUTE(RDMA, 2, DSI, 2,
+		    DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+		    DSI2_SEL_IN_RDMA2),
 };
 
 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
-- 
2.54.0