From: Ben Horgan <ben.horgan@arm.com>
To: Gavin Shan <gshan@redhat.com>
Cc: james.morse@arm.com, reinette.chatre@intel.com,
fenghuay@nvidia.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, dave.martin@arm.com,
andre.przywara@arm.com
Subject: Re: [PATCH v1 02/11] arm_mpam: Restore the error interrupt enable from mpam_cpu_online()
Date: Thu, 16 Jul 2026 09:59:38 +0100 [thread overview]
Message-ID: <fdca99b6-3298-4959-a3a4-b4e552322731@arm.com> (raw)
In-Reply-To: <519cddd8-d67a-4aef-afdf-97c933b73f82@redhat.com>
Hi Gavin,
On 7/16/26 04:59, Gavin Shan wrote:
> Hi Ben,
>
> On 7/10/26 9:55 PM, Ben Horgan wrote:
>> When all CPUs affine to an MSC are offline the MSC may lose register state
>> which the driver then restores when an affine CPU comes back online. The
>> error interrupt enable, MPAMF_ECR.INTEN, is missed.
>>
>> Restore MPAMF_ECR at CPU online.
>>
>> Fixes: 49aa621c4dca ("arm_mpam: Register and enable IRQs")
>> Signed-off-by: Ben Horgan <ben.horgan@arm.com>
>> ---
>> drivers/resctrl/mpam_devices.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
>> index 82966ca2a631..acfa9a4dc2fc 100644
>> --- a/drivers/resctrl/mpam_devices.c
>> +++ b/drivers/resctrl/mpam_devices.c
>> @@ -1852,8 +1852,14 @@ static int mpam_cpu_online(unsigned int cpu)
>> if (msc->reenable_error_ppi)
>> _enable_percpu_irq(&msc->reenable_error_ppi);
>> - if (atomic_fetch_inc(&msc->online_refs) == 0)
>> + if (atomic_fetch_inc(&msc->online_refs) == 0) {
>> + mutex_lock(&msc->error_irq_lock);
>> + if (msc->error_irq_hw_enabled)
>> + mpam_touch_msc(msc, mpam_enable_msc_ecr, msc);
>> + mutex_unlock(&msc->error_irq_lock);
>> +
>> mpam_reprogram_msc(msc);
>> + }
>> }
>>
>
> I don't understand how this happened that MPAMF_ECR gets lost, but msc->error_irq_hw_enabled
> is kept as true. mpam_disable_msc_ecr() is triggered in __mpam_irq_handler() or mpam_unregister_irqs().
> Both are related to mpam_broken_work, which is invoked to disable the driver completely.
> I don't see how MPAMF_ECR is cleared at CPU offline time.
The reasoning is the same as to why mpam_reprogram_msc() is already run here. When all the CPUs
affine to an MSC at a cache are offline then the cache instance and so the MSC might be switched off
and lose register state. Hence, any registers we rely on need to set when the MSC comes back online.
For PSCI_CPU_SUSPEND this needs to be handled by the firmware and for PSCI_CPU_OFF the driver
handles it. Does that make any more sense?
Thanks,
Ben
>
>> if (mpam_resctrl_enabled)
>
> Thanks,
> Gavin
>
next prev parent reply other threads:[~2026-07-16 8:59 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 11:55 [PATCH v1 00/11] arm_mpam: minor fixes at v7.2 Ben Horgan
2026-07-10 11:55 ` [PATCH v1 01/11] arm_mpam: Move MPAMF_ECR write helpers to allow reuse Ben Horgan
2026-07-10 11:55 ` [PATCH v1 02/11] arm_mpam: Restore the error interrupt enable from mpam_cpu_online() Ben Horgan
2026-07-16 3:59 ` Gavin Shan
2026-07-16 8:59 ` Ben Horgan [this message]
2026-07-17 0:51 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 03/11] arm_mpam: Set mpam_feat_msmon_mbwu_31counter when there are bandwidth counters Ben Horgan
2026-07-15 6:34 ` Shaopeng Tan (Fujitsu)
2026-07-15 9:11 ` Ben Horgan
2026-07-16 4:18 ` Gavin Shan
2026-07-16 9:26 ` Ben Horgan
2026-07-17 0:52 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 04/11] arm_mpam: Add missing mon_sel locking in MBWU restore Ben Horgan
2026-07-16 4:29 ` Gavin Shan
2026-07-16 9:31 ` Ben Horgan
2026-07-17 0:53 ` Gavin Shan
2026-07-17 0:56 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 05/11] arm_mpam: Ensure MBWU counters are reset on restore Ben Horgan
2026-07-15 7:49 ` Shaopeng Tan (Fujitsu)
2026-07-15 8:45 ` Ben Horgan
2026-07-16 0:26 ` Shaopeng Tan (Fujitsu)
2026-07-16 9:34 ` Ben Horgan
2026-07-10 11:55 ` [PATCH v1 06/11] arm_mpam: Use __ris_msmon_read() for saving MBWU state Ben Horgan
2026-07-16 4:49 ` Gavin Shan
2026-07-17 0:55 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 07/11] arm_mpam: Initialize all of struct mon_read in mpam_restore_mbwu_state() Ben Horgan
2026-07-17 0:55 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 08/11] arm_mpam: resctrl: Correct check that existing class is L3 Ben Horgan
2026-07-16 4:51 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 09/11] arm_mpam: resctrl: Make read_mon_cdp_safe() self consistent Ben Horgan
2026-07-16 4:51 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 10/11] arm_mpam: Don't loop forever if there is the maximum possible amount of PARTIDs Ben Horgan
2026-07-16 4:52 ` Gavin Shan
2026-07-10 11:55 ` [PATCH v1 11/11] arm_mpam: Switch to kvzmalloc_objs() for allocation of component cfg Ben Horgan
2026-07-16 4:52 ` Gavin Shan
2026-07-16 4:58 ` [PATCH v1 00/11] arm_mpam: minor fixes at v7.2 Gavin Shan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fdca99b6-3298-4959-a3a4-b4e552322731@arm.com \
--to=ben.horgan@arm.com \
--cc=andre.przywara@arm.com \
--cc=dave.martin@arm.com \
--cc=fenghuay@nvidia.com \
--cc=gshan@redhat.com \
--cc=james.morse@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=reinette.chatre@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox