* zaurus bluetooth regression
From: Pavel Machek @ 2011-01-03 14:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTika7HAEc+BbqSnbo8viUt4nOqoeB69qWZs85-9s@mail.gmail.com>
Hi!
> >> It seems this commit
> >>
> >> commit 7a56aa45982bb87bfca98a2832b5ae782c03364a
> > ...
> >> ...is responsible for my bluetooth problems on zaurus -- at least
> >> bisect pointed to it, ?as I use 16C950-based bluetooth card, it seems
> >> very logical. I'll try 2.6.37-rc8 with that patch reverted...
> >>
> >
> > And yes, 37-rc8 with that reverted results in working bluetooth, so
> > yrs, that patch is responsible.
>
> could you tell, what kind of problem you're encountering and if you
> could tell, which flag UART_CAP_EFR or UART_CAP_SLEEP causes the
> problem?
Bluetooth will not work with 'tx command timeout', details should be
in bugzilla.
CAP_EFR seems to cause the problem.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply
* [patch 2/5] ulpi: handle ULPI_OTG_CTRL_CHRGVBUS
From: Arnaud Patard (Rtp) @ 2011-01-03 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D21D00C.3040601@compulab.co.il>
Igor Grinberg <grinberg@compulab.co.il> writes:
> On 01/03/11 13:41, Arnaud Patard (Rtp) wrote:
>> Igor Grinberg <grinberg@compulab.co.il> writes:
>> Hi,
>>> On 12/23/10 22:11, Arnaud Patard (Rtp) wrote:
>>>> Igor Grinberg <grinberg@compulab.co.il> writes:
>>>>> Hi Arnaud,
>>>>>
>>>>> On 12/20/10 17:48, Arnaud Patard (Rtp) wrote:
>>>>>> Current code doesn't handle setting CHRGVBUS when enabling vbus.
>>>>>> Add support for it
>>>>>>
>>>>>>
>>>>>>
>>>>>> Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
>>>>>> Index: tst-usb/drivers/usb/otg/ulpi.c
>>>>>> ===================================================================
>>>>>> --- tst-usb.orig/drivers/usb/otg/ulpi.c 2010-12-20 15:38:41.000000000 +0100
>>>>>> +++ tst-usb/drivers/usb/otg/ulpi.c 2010-12-20 15:38:57.000000000 +0100
>>>>>> @@ -234,7 +234,8 @@
>>>>>> {
>>>>>> unsigned int flags = otg_io_read(otg, ULPI_OTG_CTRL);
>>>>>>
>>>>>> - flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
>>>>>> + flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT |
>>>>>> + ULPI_OTG_CTRL_CHRGVBUS);
>>>>>>
>>>>>> if (on) {
>>>>>> if (otg->flags & ULPI_OTG_DRVVBUS)
>>>>>> @@ -242,6 +243,9 @@
>>>>>>
>>>>>> if (otg->flags & ULPI_OTG_DRVVBUS_EXT)
>>>>>> flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>>>>>> +
>>>>>> + if (otg->flags & ULPI_OTG_CHRGVBUS)
>>>>>> + flags |= ULPI_OTG_CTRL_CHRGVBUS;
>>>>>> }
>>>>>>
>>>>>> return otg_io_write(otg, flags, ULPI_OTG_CTRL);
>>>>> I think this is a wrong place to set the ChrgVbus bit.
>>>>> As for ULPI spec. 1.1:
>>>>> "3.8.7.1 Session Request Protocol (SRP)
>>>>> ULPI provides full SRP support. The Link uses the ChrgVbus and DischrgVbus bits
>>>>> in the OTG Control register to begin and end a session."
>>>>>
>>>>> So it is used for SRP.
>>>>> May be it is better to implement
>>>>> int (*start_srp)(struct otg_transceiver *otg);
>>>>> method for setting this bit?
>>>>>
>>>> I was not sure on where to put this so I took the same approach as the
>>>> fsl bsp which was to set it in this function and to call this function
>>>> _after_ usb_add_hcd() [ see my previous patch ]. Indeed, it fixed my
>>>> issue so I believe it not so bad given that there has already been some
>>>> troubles on the ehci-mxc init.
>>> Well, the problem is that this is supposed to be a generic driver and it should
>>> somehow follow the ULPI spec.
>>> This patch makes it more like mxc specific.
>>>
>>> As far as I understand, Session Request Protocol (SRP) allows a B-device (Peripheral)
>>> to nudge an A-device (Host) to turn on the USB's Vbus.
>>> This patch enables SRP along with Vbus, which seems incorrect completely.
>>> ulpi_set_vbus() should set the Vbus (as its name says) and that's it.
>> so, if I add a srp hook as you're suggesting, which part of the driver
>> should call it ?
>
> It should be called from outside the ulpi driver by the OTG logic
> (just like ulpi_set_vbus() is called).
> But, again, SRP should be set by the B-device (peripheral) and Vbus by the A-device (Host).
> Usually, the A-device and B-device are on the opposite sides of the USB cable.
>
>>> Have you tried without this patch or have you just applied it along with other
>>> patches from the fsl bsp?
>> I already tried without this patch and without it, things are not
>> working on my systems.
>>> Also, if this specific patch (2/5) makes your USB (Host as I understand) work,
>>> it makes me think that there could be some problem with your Vbus supply.
>>> Have you checked that?
>> I don't have any schematics and I've access only to the source code of
>> the kernel running on the efika nettop and smartbook [1]. I've not seen
>> anything (even remotely) related to vbus supply except in the ulpi code
>> and from what I've heard, it's unlikely that there's something to
>> control it on theses systems. Of course, I'll be happy to be proven
>> wrong. Without usb theses systems are useless so anything the can reduce
>> the number of patches needed to get the systems working with mainline is
>> welcome.
>
> Well, I was certain you are trying to use that port in Host mode (A-device), but
> now I'm confused...
> You say "things are not working" - what are those things?
> Can you, please, describe what are you trying to do?
> What are you trying to connect to this USB port? What cable do you
> use?
I thought it was clear that "things" was everything connected on the usb
ports. The problem is that this also means that the nettop/smartbook are
kind of not working too as ethernet/wifi/bt/hid devs are all connected
on usb [ they're all on the pcb ]. So, even if you boot on the mmc aka
the only storage available which doesn't need usb, you won't be able to
login.
> Also, what ulpi vendor/product id is reported in ulpi_init()?
ULPI transceiver vendor/product ID 0x0424/0x0006
Found SMSC USB3319 ULPI transceiver.
Arnaud
^ permalink raw reply
* [PATCH 02/04] ARM i.MX25 Add SIM driver
From: Russell King - ARM Linux @ 2011-01-03 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110103130551.GA24408@pengutronix.de>
On Mon, Jan 03, 2011 at 02:05:51PM +0100, Sascha Hauer wrote:
> The following comments are mostly coding style related, running Lindent
> and checkpatch.pl on this patch seems to be a good start for improving
> this driver.
Beware of Lindent - it can scrunch lines against the right hand side.
Always build the driver before you Lindent it, take a copy of the object
file, then Lindent it, and then re-build it and confirm that the resulting
code and data is indentical. A Lindent shouldn't ever change the produced
code, but unfortunately it has been known to do so.
Keep the Lindenting as a single commit - never combine it with other stuff.
Always go through the driver after running Lindent and fix up scrunches
on the right hand side by hand (maybe it needs the function splitting
into a few helper functions?) Commit these (and any other fixups) as a
follow-on commit.
^ permalink raw reply
* [patch 2/5] ulpi: handle ULPI_OTG_CTRL_CHRGVBUS
From: Igor Grinberg @ 2011-01-03 13:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87fwta8b99.fsf@lechat.rtp-net.org>
On 01/03/11 13:41, Arnaud Patard (Rtp) wrote:
> Igor Grinberg <grinberg@compulab.co.il> writes:
> Hi,
>> On 12/23/10 22:11, Arnaud Patard (Rtp) wrote:
>>> Igor Grinberg <grinberg@compulab.co.il> writes:
>>>> Hi Arnaud,
>>>>
>>>> On 12/20/10 17:48, Arnaud Patard (Rtp) wrote:
>>>>> Current code doesn't handle setting CHRGVBUS when enabling vbus.
>>>>> Add support for it
>>>>>
>>>>>
>>>>>
>>>>> Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
>>>>> Index: tst-usb/drivers/usb/otg/ulpi.c
>>>>> ===================================================================
>>>>> --- tst-usb.orig/drivers/usb/otg/ulpi.c 2010-12-20 15:38:41.000000000 +0100
>>>>> +++ tst-usb/drivers/usb/otg/ulpi.c 2010-12-20 15:38:57.000000000 +0100
>>>>> @@ -234,7 +234,8 @@
>>>>> {
>>>>> unsigned int flags = otg_io_read(otg, ULPI_OTG_CTRL);
>>>>>
>>>>> - flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
>>>>> + flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT |
>>>>> + ULPI_OTG_CTRL_CHRGVBUS);
>>>>>
>>>>> if (on) {
>>>>> if (otg->flags & ULPI_OTG_DRVVBUS)
>>>>> @@ -242,6 +243,9 @@
>>>>>
>>>>> if (otg->flags & ULPI_OTG_DRVVBUS_EXT)
>>>>> flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>>>>> +
>>>>> + if (otg->flags & ULPI_OTG_CHRGVBUS)
>>>>> + flags |= ULPI_OTG_CTRL_CHRGVBUS;
>>>>> }
>>>>>
>>>>> return otg_io_write(otg, flags, ULPI_OTG_CTRL);
>>>> I think this is a wrong place to set the ChrgVbus bit.
>>>> As for ULPI spec. 1.1:
>>>> "3.8.7.1 Session Request Protocol (SRP)
>>>> ULPI provides full SRP support. The Link uses the ChrgVbus and DischrgVbus bits
>>>> in the OTG Control register to begin and end a session."
>>>>
>>>> So it is used for SRP.
>>>> May be it is better to implement
>>>> int (*start_srp)(struct otg_transceiver *otg);
>>>> method for setting this bit?
>>>>
>>> I was not sure on where to put this so I took the same approach as the
>>> fsl bsp which was to set it in this function and to call this function
>>> _after_ usb_add_hcd() [ see my previous patch ]. Indeed, it fixed my
>>> issue so I believe it not so bad given that there has already been some
>>> troubles on the ehci-mxc init.
>> Well, the problem is that this is supposed to be a generic driver and it should
>> somehow follow the ULPI spec.
>> This patch makes it more like mxc specific.
>>
>> As far as I understand, Session Request Protocol (SRP) allows a B-device (Peripheral)
>> to nudge an A-device (Host) to turn on the USB's Vbus.
>> This patch enables SRP along with Vbus, which seems incorrect completely.
>> ulpi_set_vbus() should set the Vbus (as its name says) and that's it.
> so, if I add a srp hook as you're suggesting, which part of the driver
> should call it ?
It should be called from outside the ulpi driver by the OTG logic
(just like ulpi_set_vbus() is called).
But, again, SRP should be set by the B-device (peripheral) and Vbus by the A-device (Host).
Usually, the A-device and B-device are on the opposite sides of the USB cable.
>> Have you tried without this patch or have you just applied it along with other
>> patches from the fsl bsp?
> I already tried without this patch and without it, things are not
> working on my systems.
>> Also, if this specific patch (2/5) makes your USB (Host as I understand) work,
>> it makes me think that there could be some problem with your Vbus supply.
>> Have you checked that?
> I don't have any schematics and I've access only to the source code of
> the kernel running on the efika nettop and smartbook [1]. I've not seen
> anything (even remotely) related to vbus supply except in the ulpi code
> and from what I've heard, it's unlikely that there's something to
> control it on theses systems. Of course, I'll be happy to be proven
> wrong. Without usb theses systems are useless so anything the can reduce
> the number of patches needed to get the systems working with mainline is
> welcome.
Well, I was certain you are trying to use that port in Host mode (A-device), but
now I'm confused...
You say "things are not working" - what are those things?
Can you, please, describe what are you trying to do?
What are you trying to connect to this USB port? What cable do you use?
Also, what ulpi vendor/product id is reported in ulpi_init()?
> Arnaud
>
> [1] http://gitorious.org/efikamx/linux-kernel/
--
Regards,
Igor.
^ permalink raw reply
* [PATCH 1/2] davinci: Support disabling modem status interrupts on SOC UARTS
From: Michael Williamson @ 2011-01-03 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB593024816D2D7@dbde02.ent.ti.com>
On 1/3/2011 1:21 AM, Nori, Sekhar wrote:
> Hi Michael,
>
> On Sat, Jan 01, 2011 at 06:41:56, Michael Williamson wrote:
>> On the da850/omap-l138/am18x family of SoCs, up to three on chip UARTS may be
>> configured. These peripherals support the standard Tx/Rx signals as well as
>> CTS/RTS hardware flow control signals. The pins on these SOC's associated with
>> these signals are multiplexed; e.g., the pin providing UART0_TXD capability
>> also provides SPI0 chip select line 5 output capability. The configuration of
>> the pin multiplexing occurs during platform initialization (or by earlier
>> bootloader operations).
>>
>> There is a problem with the multiplexing implementation on these SOCs. Only
>> the output and output enable portions of the I/O section of the pin are
>> multiplexed. All peripheral input functions remain connected to a given pin
>> regardless of configuration.
>>
>> In many configurations of these parts, providing a UART with Tx/Rx capability
>> is needed, but the HW flow control capability is not. Furthermore, the pins
>> associated with the CTS inputs on these UARTS are often configured to support
>> a different peripheral, and they may be active/toggling during runtime. This
>> can result in false modem status (CTS) interrupts being asserted to the 8250
>> driver controlling the associated Tx/Rx pins, and can impact system
>> performance. This is especially true if the CTS pin is shared with something
>> like a clock line as is the case with UART1 CTS and the McASP AHCLKX.
>>
>> The 8250 serial driver platform data does not provide a direct mechanism to
>> tell the driver to disable modem status (i.e., CTS) interrupts for a given
>> port. As a work-around, allow davinci platforms to override set_termios for
>> configured UARTS that do not provide a true CTS input and ensure any request
>> does not enable HW flow control.
>>
>> This patch was tested using a MityDSP-L138 SOM having UART1 enabled with the
>> associated CTS pin connected to a clock (configured for the AHCLKX function).
>>
>> Background / problem reports related to this issue are captured in the links
>> below:
>> http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/36701.aspx
>> http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg19524.html
>>
>> Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
>> Tested-by: Michael Williamson <michael.williamson@criticallink.com>
>> ---
>> This patch is against davinci-linux.
>>
>> I'm open to suggestions for reducing the patch description.
>>
>> I'm open to alternatives to the solution below, outside of disabling the
>> UARTs in question as is done on the DA850 evm and the hawkboard (both
>> of which might be able to use this patch?).
>
> Can you please CC linux-serial on this patch? Folks on that list
> will have ideas on how best to work around this issue.
>
> I think setting the UART_BUG_NOMSR in up->bugs for these ports
> (as you previously implemented on your tree) is a better patch
> since it utilizes an existing established mechanism.
>
> I understand there is no existing way to pass the bugs through
> platform data, but may be that needs to be created (or may be
> have a new port type for "DaVinci UART with no flow control" and
> then setup up->bugs after checking for this port type).
>
I will post to linux-serial and see what their take is on this issue.
Thanks for the comments.
-Mike
^ permalink raw reply
* [PATCH v4] davinci: Support various speedgrades for MityDSP-L138 and MityARM-1808 SoMs
From: Michael Williamson @ 2011-01-03 13:21 UTC (permalink / raw)
To: linux-arm-kernel
For the MityDSP-L138/MityARM-1808 SoMs, the speed grade can be determined
from the part number string read from the factory configuration block on
the on-board I2C PROM. Configure the maximum CPU speed based on this
information.
This patch was tested using a MityDSP-L138 and MityARM-1808 at various
speedgrades. Also, for code coverage, a bogus configuration was tested
as well as a configuration having an unknown part number.
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Tested-by: Michael Williamson <michael.williamson@criticallink.com>
---
Built against linux-davinci.
Changes since v2 (v3 was sent in error, wrong file, sorry for the churn):
- reworked logic to use fall-through logic for mityomapl138_cpugreq_init call
per comments.
arch/arm/mach-davinci/board-mityomapl138.c | 83 +++++++++++++++++++++++++---
1 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0bb5f0c..86d6229 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -44,38 +44,109 @@ struct factory_config {
static struct factory_config factory_config;
+struct part_no_info {
+ const char *part_no; /* part number string of interest */
+ int max_freq; /* khz */
+};
+
+static struct part_no_info mityomapl138_pn_info[] = {
+ {
+ .part_no = "L138-C",
+ .max_freq = 300000,
+ },
+ {
+ .part_no = "L138-D",
+ .max_freq = 375000,
+ },
+ {
+ .part_no = "L138-F",
+ .max_freq = 456000,
+ },
+ {
+ .part_no = "1808-C",
+ .max_freq = 300000,
+ },
+ {
+ .part_no = "1808-D",
+ .max_freq = 375000,
+ },
+ {
+ .part_no = "1808-F",
+ .max_freq = 456000,
+ },
+ {
+ .part_no = "1810-D",
+ .max_freq = 375000,
+ },
+};
+
+#ifdef CONFIG_CPU_FREQ
+static void mityomapl138_cpufreq_init(const char *partnum)
+{
+ int i, ret;
+
+ for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
+ /*
+ * the part number has additional characters beyond what is
+ * stored in the table. This information is not needed for
+ * determining the speed grade, and would require several
+ * more table entries. Only check the first N characters
+ * for a match.
+ */
+ if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
+ strlen(mityomapl138_pn_info[i].part_no))) {
+ da850_max_speed = mityomapl138_pn_info[i].max_freq;
+ break;
+ }
+ }
+
+ ret = da850_register_cpufreq("pll0_sysclk3");
+ if (ret)
+ pr_warning("cpufreq registration failed: %d\n", ret);
+}
+#else
+static void mityomapl138_cpufreq_init(const char *partnum) { }
+#endif
+
static void read_factory_config(struct memory_accessor *a, void *context)
{
int ret;
+ const char *partnum = NULL;
struct davinci_soc_info *soc_info = &davinci_soc_info;
ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
if (ret != sizeof(struct factory_config)) {
pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
ret);
- return;
+ goto bad_config;
}
if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
factory_config.magic);
- return;
+ goto bad_config;
}
if (factory_config.version != FACTORY_CONFIG_VERSION) {
pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
factory_config.version);
- return;
+ goto bad_config;
}
pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
- pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
if (is_valid_ether_addr(factory_config.mac))
memcpy(soc_info->emac_pdata->mac_addr,
factory_config.mac, ETH_ALEN);
else
pr_warning("MityOMAPL138: Invalid MAC found "
"in factory config block\n");
+
+ partnum = factory_config.partnum;
+ pr_info("MityOMAPL138: Part Number = %s\n", partnum);
+
+bad_config:
+ /* default maximum speed is valid for all platforms */
+ mityomapl138_cpufreq_init(partnum);
}
static struct at24_platform_data mityomapl138_fd_chip = {
@@ -383,10 +454,6 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warning("rtc setup failed: %d\n", ret);
- ret = da850_register_cpufreq("pll0_sysclk3");
- if (ret)
- pr_warning("cpufreq registration failed: %d\n", ret);
-
ret = da8xx_register_cpuidle();
if (ret)
pr_warning("cpuidle registration failed: %d\n", ret);
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/7 v2] OMAP2430: hwmod data: Add McSPI
From: Govindraj @ 2011-01-03 13:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20101230190320.GA2713@angua.secretlab.ca>
On Fri, Dec 31, 2010 at 12:33 AM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> On Wed, Dec 01, 2010 at 07:31:22PM +0530, Govindraj.R wrote:
>> From: Charulatha V <charu@ti.com>
>>
>> Update the 2430 hwmod data file with McSPI info.
>>
>> Signed-off-by: Charulatha V <charu@ti.com>
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>
> Hmmm; this patch is virtually identical to the first patch in this
> series which adds 2420 hwmod support. ?I see a large block of
> identical data with minor differences. ?Surely support for these two
> chips can share the common blocks of data.
>
> Is this going to be a common situation for HWMOD data?
Grant,
Thanks for your Review comments.
Currently we have four hwmod data files:
2420, 2430 , 3xxx, 44xx
We need to fill these four files with hw info data to be passed
to driver there could be small info that might be duplicated.
Currently we are updating all the four files.
As Paul said there might be some changes done going forward.
To handle the hwmod files.
Hope this clarifies.
--
Thanks,
Govindraj.R
>
> g.
>
>> ---
>> ?arch/arm/mach-omap2/omap_hwmod_2430_data.c | ?219 ++++++++++++++++++++++++++++
>> ?1 files changed, 219 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
>> index 7cf0d3a..bcdfb2b 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
>> @@ -17,6 +17,7 @@
>> ?#include <plat/dma.h>
>> ?#include <plat/serial.h>
>> ?#include <plat/i2c.h>
>> +#include <plat/mcspi.h>
>> ?#include <plat/omap24xx.h>
>>
>> ?#include "omap_hwmod_common_data.h"
>> @@ -38,6 +39,9 @@ static struct omap_hwmod omap2430_iva_hwmod;
>> ?static struct omap_hwmod omap2430_l3_main_hwmod;
>> ?static struct omap_hwmod omap2430_l4_core_hwmod;
>> ?static struct omap_hwmod omap2430_wd_timer2_hwmod;
>> +static struct omap_hwmod omap2430_mcspi1_hwmod;
>> +static struct omap_hwmod omap2430_mcspi2_hwmod;
>> +static struct omap_hwmod omap2430_mcspi3_hwmod;
>>
>> ?/* L3 -> L4_CORE interface */
>> ?static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
>> @@ -216,6 +220,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
>> ?static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
>> ?};
>>
>> +/* l4 core -> mcspi1 interface */
>> +static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
>> + ? ? {
>> + ? ? ? ? ? ? .pa_start ? ? ? = 0x48098000,
>> + ? ? ? ? ? ? .pa_end ? ? ? ? = 0x480980ff,
>> + ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT,
>> + ? ? },
>> +};
>> +
>> +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
>> + ? ? .master ? ? ? ? = &omap2430_l4_core_hwmod,
>> + ? ? .slave ? ? ? ? ?= &omap2430_mcspi1_hwmod,
>> + ? ? .clk ? ? ? ? ? ?= "mcspi1_ick",
>> + ? ? .addr ? ? ? ? ? = omap2430_mcspi1_addr_space,
>> + ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap2430_mcspi1_addr_space),
>> + ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4 core -> mcspi2 interface */
>> +static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
>> + ? ? {
>> + ? ? ? ? ? ? .pa_start ? ? ? = 0x4809a000,
>> + ? ? ? ? ? ? .pa_end ? ? ? ? = 0x4809a0ff,
>> + ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT,
>> + ? ? },
>> +};
>> +
>> +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
>> + ? ? .master ? ? ? ? = &omap2430_l4_core_hwmod,
>> + ? ? .slave ? ? ? ? ?= &omap2430_mcspi2_hwmod,
>> + ? ? .clk ? ? ? ? ? ?= "mcspi2_ick",
>> + ? ? .addr ? ? ? ? ? = omap2430_mcspi2_addr_space,
>> + ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap2430_mcspi2_addr_space),
>> + ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4 core -> mcspi3 interface */
>> +static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
>> + ? ? {
>> + ? ? ? ? ? ? .pa_start ? ? ? = 0x480b8000,
>> + ? ? ? ? ? ? .pa_end ? ? ? ? = 0x480b80ff,
>> + ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT,
>> + ? ? },
>> +};
>> +
>> +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
>> + ? ? .master ? ? ? ? = &omap2430_l4_core_hwmod,
>> + ? ? .slave ? ? ? ? ?= &omap2430_mcspi3_hwmod,
>> + ? ? .clk ? ? ? ? ? ?= "mcspi3_ick",
>> + ? ? .addr ? ? ? ? ? = omap2430_mcspi3_addr_space,
>> + ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap2430_mcspi3_addr_space),
>> + ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> ?/* L4 WKUP */
>> ?static struct omap_hwmod omap2430_l4_wkup_hwmod = {
>> ? ? ? .name ? ? ? ? ? = "l4_wkup",
>> @@ -569,6 +627,162 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
>> ? ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
>> ?};
>>
>> +/*
>> + * 'mcspi' class
>> + * multichannel serial port interface (mcspi) / master/slave synchronous serial
>> + * bus
>> + */
>> +
>> +static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
>> + ? ? .rev_offs ? ? ? = 0x0000,
>> + ? ? .sysc_offs ? ? ?= 0x0010,
>> + ? ? .syss_offs ? ? ?= 0x0014,
>> + ? ? .sysc_flags ? ? = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? SYSC_HAS_AUTOIDLE),
>> + ? ? .idlemodes ? ? ?= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
>> + ? ? .sysc_fields ? ?= &omap_hwmod_sysc_type1,
>> +};
>> +
>> +static struct omap_hwmod_class omap2430_mcspi_class = {
>> + ? ? .name = "mcspi",
>> + ? ? .sysc = &omap2430_mcspi_sysc,
>> + ? ? .rev = OMAP2_MCSPI_REV,
>> +};
>> +
>> +/* mcspi1 */
>> +static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
>> + ? ? { .irq = 65 },
>> +};
>> +
>> +static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
>> + ? ? { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
>> + ? ? { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
>> + ? ? { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
>> + ? ? { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
>> + ? ? { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
>> + ? ? { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
>> + ? ? { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
>> + ? ? { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
>> +};
>> +
>> +static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
>> + ? ? &omap2430_l4_core__mcspi1,
>> +};
>> +
>> +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
>> + ? ? .num_chipselect = 4,
>> +};
>> +
>> +static struct omap_hwmod omap2430_mcspi1_hwmod = {
>> + ? ? .name ? ? ? ? ? = "mcspi1_hwmod",
>> + ? ? .mpu_irqs ? ? ? = omap2430_mcspi1_mpu_irqs,
>> + ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
>> + ? ? .sdma_reqs ? ? ?= omap2430_mcspi1_sdma_reqs,
>> + ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
>> + ? ? .main_clk ? ? ? = "mcspi1_fck",
>> + ? ? .prcm ? ? ? ? ? = {
>> + ? ? ? ? ? ? .omap2 = {
>> + ? ? ? ? ? ? ? ? ? ? .module_offs = CORE_MOD,
>> + ? ? ? ? ? ? ? ? ? ? .prcm_reg_id = 1,
>> + ? ? ? ? ? ? ? ? ? ? .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_reg_id = 1,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
>> + ? ? ? ? ? ? },
>> + ? ? },
>> + ? ? .slaves ? ? ? ? = omap2430_mcspi1_slaves,
>> + ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap2430_mcspi1_slaves),
>> + ? ? .class ? ? ? ? ?= &omap2430_mcspi_class,
>> + ? ? .dev_attr ? ? ? = &omap_mcspi1_dev_attr,
>> + ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
>> +};
>> +
>> +/* mcspi2 */
>> +static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
>> + ? ? { .irq = 66 },
>> +};
>> +
>> +static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
>> + ? ? { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
>> + ? ? { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
>> + ? ? { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
>> + ? ? { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
>> +};
>> +
>> +static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
>> + ? ? &omap2430_l4_core__mcspi2,
>> +};
>> +
>> +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
>> + ? ? .num_chipselect = 2,
>> +};
>> +
>> +static struct omap_hwmod omap2430_mcspi2_hwmod = {
>> + ? ? .name ? ? ? ? ? = "mcspi2_hwmod",
>> + ? ? .mpu_irqs ? ? ? = omap2430_mcspi2_mpu_irqs,
>> + ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
>> + ? ? .sdma_reqs ? ? ?= omap2430_mcspi2_sdma_reqs,
>> + ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
>> + ? ? .main_clk ? ? ? = "mcspi2_fck",
>> + ? ? .prcm ? ? ? ? ? = {
>> + ? ? ? ? ? ? .omap2 = {
>> + ? ? ? ? ? ? ? ? ? ? .module_offs = CORE_MOD,
>> + ? ? ? ? ? ? ? ? ? ? .prcm_reg_id = 1,
>> + ? ? ? ? ? ? ? ? ? ? .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_reg_id = 1,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
>> + ? ? ? ? ? ? },
>> + ? ? },
>> + ? ? .slaves ? ? ? ? = omap2430_mcspi2_slaves,
>> + ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap2430_mcspi2_slaves),
>> + ? ? .class ? ? ? ? ?= &omap2430_mcspi_class,
>> + ? ? .dev_attr ? ? ? = &omap_mcspi2_dev_attr,
>> + ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
>> +};
>> +
>> +/* mcspi3 */
>> +static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
>> + ? ? { .irq = 91 },
>> +};
>> +
>> +static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
>> + ? ? { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
>> + ? ? { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
>> + ? ? { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
>> + ? ? { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
>> +};
>> +
>> +static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
>> + ? ? &omap2430_l4_core__mcspi3,
>> +};
>> +
>> +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
>> + ? ? .num_chipselect = 2,
>> +};
>> +
>> +static struct omap_hwmod omap2430_mcspi3_hwmod = {
>> + ? ? .name ? ? ? ? ? = "mcspi3_hwmod",
>> + ? ? .mpu_irqs ? ? ? = omap2430_mcspi3_mpu_irqs,
>> + ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
>> + ? ? .sdma_reqs ? ? ?= omap2430_mcspi3_sdma_reqs,
>> + ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
>> + ? ? .main_clk ? ? ? = "mcspi3_fck",
>> + ? ? .prcm ? ? ? ? ? = {
>> + ? ? ? ? ? ? .omap2 = {
>> + ? ? ? ? ? ? ? ? ? ? .module_offs = CORE_MOD,
>> + ? ? ? ? ? ? ? ? ? ? .prcm_reg_id = 2,
>> + ? ? ? ? ? ? ? ? ? ? .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_reg_id = 2,
>> + ? ? ? ? ? ? ? ? ? ? .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
>> + ? ? ? ? ? ? },
>> + ? ? },
>> + ? ? .slaves ? ? ? ? = omap2430_mcspi3_slaves,
>> + ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap2430_mcspi3_slaves),
>> + ? ? .class ? ? ? ? ?= &omap2430_mcspi_class,
>> + ? ? .dev_attr ? ? ? = &omap_mcspi3_dev_attr,
>> + ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
>> +};
>> +
>> ?static __initdata struct omap_hwmod *omap2430_hwmods[] = {
>> ? ? ? &omap2430_l3_main_hwmod,
>> ? ? ? &omap2430_l4_core_hwmod,
>> @@ -581,6 +795,11 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
>> ? ? ? &omap2430_uart3_hwmod,
>> ? ? ? &omap2430_i2c1_hwmod,
>> ? ? ? &omap2430_i2c2_hwmod,
>> +
>> + ? ? /* mcspi class */
>> + ? ? &omap2430_mcspi1_hwmod,
>> + ? ? &omap2430_mcspi2_hwmod,
>> + ? ? &omap2430_mcspi3_hwmod,
>> ? ? ? NULL,
>> ?};
>>
>> --
>> 1.7.1
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Increase Visibility of Your 3D Game App & Earn a Chance To Win $500!
>> Tap into the largest installed PC base & get more eyes on your game by
>> optimizing for Intel(R) Graphics Technology. Get started today with the
>> Intel(R) Software Partner Program. Five $500 cash prizes are up for grabs.
>> http://p.sf.net/sfu/intelisp-dev2dev
>> _______________________________________________
>> spi-devel-general mailing list
>> spi-devel-general at lists.sourceforge.net
>> https://lists.sourceforge.net/lists/listinfo/spi-devel-general
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
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^ permalink raw reply
* [PATCH] ARM: imx/mx27_3ds: Add PMIC support
From: Fabio Estevam @ 2011-01-03 13:16 UTC (permalink / raw)
To: linux-arm-kernel
MX27_3DS board has a MC13783 PMIC connected to the CSPI2 port.
Add support for the PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/mach-mx27_3ds.c | 77 +++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0449b80..17d2e60 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -242,6 +242,7 @@ config MACH_MX27_3DS
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX27PDK platform. This includes specific
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 0ee7a73..6fd0f8f 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -26,6 +26,9 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/delay.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -39,6 +42,7 @@
#define SD1_EN_GPIO (GPIO_PORTB + 25)
#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
+#define SPI2_SS0 (GPIO_PORTD + 21)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
@@ -87,6 +91,10 @@ static const int mx27pdk_pins[] __initconst = {
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
+ /* CSPI2 */
+ PD22_PF_CSPI2_SCLK,
+ PD23_PF_CSPI2_MISO,
+ PD24_PF_CSPI2_MOSI,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -176,6 +184,72 @@ static int __init mx27_3ds_otg_mode(char *options)
}
__setup("otg_mode=", mx27_3ds_otg_mode);
+/* Regulators */
+static struct regulator_consumer_supply vmmc1_consumers[] = {
+ REGULATOR_SUPPLY("lcd_2v8", NULL),
+};
+
+static struct regulator_init_data vmmc1_init = {
+ .constraints = {
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
+ .consumer_supplies = vmmc1_consumers,
+};
+
+static struct regulator_consumer_supply vgen_consumers[] = {
+ REGULATOR_SUPPLY("vdd_lcdio", NULL),
+};
+
+static struct regulator_init_data vgen_init = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
+ .consumer_supplies = vgen_consumers,
+};
+
+static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
+ {
+ .id = MC13783_REGU_VMMC1,
+ .init_data = &vmmc1_init,
+ }, {
+ .id = MC13783_REGU_VGEN,
+ .init_data = &vgen_init,
+ },
+};
+
+/* MC13783 */
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+ .regulators = mx27_3ds_regulators,
+ .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
+ .flags = MC13783_USE_REGULATOR,
+};
+
+/* SPI */
+static int spi2_internal_chipselect[] = {SPI2_SS0};
+
+static const struct spi_imx_master spi2_pdata __initconst = {
+ .chipselect = spi2_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
+};
+
+static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
+ {
+ .modalias = "mc13783",
+ .max_speed_hz = 1000000,
+ .bus_num = 1,
+ .chip_select = 0, /* SS0 */
+ .platform_data = &mc13783_pdata,
+ .irq = IRQ_GPIOC(14),
+ .mode = SPI_CS_HIGH,
+ },
+};
+
static void __init mx27pdk_init(void)
{
@@ -199,6 +273,9 @@ static void __init mx27pdk_init(void)
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
+ imx27_add_spi_imx1(&spi2_pdata);
+ spi_register_board_info(mx27_3ds_spi_devs,
+ ARRAY_SIZE(mx27_3ds_spi_devs));
}
static void __init mx27pdk_timer_init(void)
--
1.6.0.4
^ permalink raw reply related
* [PATCH v3] davinci: Support various speedgrades for MityDSP-L138 and MityARM-1808 SoMs
From: Michael Williamson @ 2011-01-03 13:07 UTC (permalink / raw)
To: linux-arm-kernel
For the MityDSP-L138/MityARM-1808 SoMs, the speed grade can be determined
from the part number string read from the factory configuration block on
the on-board I2C PROM. Configure the maximum CPU speed based on this
information.
This patch was tested using a MityDSP-L138 at various speedgrades. Also,
for code coverage, a bogus configuration was tested as well as a
configuration having an unknown part number.
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Tested-by: Michael Williamson <michael.williamson@criticallink.com>
---
Built against linux-davinci tree.
Changes since v2.
- reworked logic to use fall-through logic for mityomapl138_cpugreq_init call
per comments.
arch/arm/mach-davinci/board-mityomapl138.c | 83 +++++++++++++++++++++++++---
1 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0bb5f0c..8ba1937 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -44,38 +44,109 @@ struct factory_config {
static struct factory_config factory_config;
+struct part_no_info {
+ const char *part_no; /* part number string of interest */
+ int max_freq; /* khz */
+};
+
+static struct part_no_info mityomapl138_pn_info[] = {
+ {
+ .part_no = "L138-C",
+ .max_freq = 300000,
+ },
+ {
+ .part_no = "L138-D",
+ .max_freq = 375000,
+ },
+ {
+ .part_no = "L138-F",
+ .max_freq = 456000,
+ },
+ {
+ .part_no = "1808-C",
+ .max_freq = 300000,
+ },
+ {
+ .part_no = "1808-D",
+ .max_freq = 375000,
+ },
+ {
+ .part_no = "1808-F",
+ .max_freq = 456000,
+ },
+ {
+ .part_no = "1810-D",
+ .max_freq = 375000,
+ },
+};
+
+#ifdef CONFIG_CPU_FREQ
+static void mityomapl138_cpufreq_init(const char *partnum)
+{
+ int i, ret;
+
+ for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
+ /*
+ * the part number has additional characters beyond what is
+ * stored in the table. This information is not needed for
+ * determining the speed grade, and would require several
+ * more table entries. Only check the first N characters
+ * for a match.
+ */
+ if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
+ strlen(mityomapl138_pn_info[i].part_no))) {
+ da850_max_speed = mityomapl138_pn_info[i].max_freq;
+ break;
+ }
+ }
+
+ ret = da850_register_cpufreq("pll0_sysclk3");
+ if (ret)
+ pr_warning("cpufreq registration failed: %d\n", ret);
+}
+#else
+static void mityomapl138_cpufreq_init(const char *partnum) { }
+#endif
+
static void read_factory_config(struct memory_accessor *a, void *context)
{
int ret;
+ const char *partnum = NULL;
struct davinci_soc_info *soc_info = &davinci_soc_info;
ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
if (ret != sizeof(struct factory_config)) {
pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
ret);
- return;
+ goto bad_config;
}
if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
factory_config.magic);
- return;
+ goto bad_config;
}
if (factory_config.version != FACTORY_CONFIG_VERSION) {
pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
factory_config.version);
- return;
+ goto bad_config;
}
pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
- pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
if (is_valid_ether_addr(factory_config.mac))
memcpy(soc_info->emac_pdata->mac_addr,
factory_config.mac, ETH_ALEN);
else
pr_warning("MityOMAPL138: Invalid MAC found "
"in factory config block\n");
+
+ partnum = factory_config.partnum;
+ pr_info("MityOMAPL138: Part Number = %s\n", partnum);
+
+bad_config:
+ /* default maximum speed is valid for all platforms */
+ mityomapl138_cpufreq_init(NULL);
}
static struct at24_platform_data mityomapl138_fd_chip = {
@@ -383,10 +454,6 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warning("rtc setup failed: %d\n", ret);
- ret = da850_register_cpufreq("pll0_sysclk3");
- if (ret)
- pr_warning("cpufreq registration failed: %d\n", ret);
-
ret = da8xx_register_cpuidle();
if (ret)
pr_warning("cpuidle registration failed: %d\n", ret);
--
1.7.0.4
^ permalink raw reply related
* [PATCH v3] davinci: Support various speedgrades for MityDSP-L138 and MityARM-1808 SoMs
From: Michael Williamson @ 2011-01-03 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294060053-2761-1-git-send-email-michael.williamson@criticallink.com>
Please IGNORE this patch. I sent the wrong file. Sorry for the noise.
-Mike
On 1/3/2011 8:07 AM, Michael Williamson wrote:
> For the MityDSP-L138/MityARM-1808 SoMs, the speed grade can be determined
> from the part number string read from the factory configuration block on
> the on-board I2C PROM. Configure the maximum CPU speed based on this
> information.
>
> This patch was tested using a MityDSP-L138 at various speedgrades. Also,
> for code coverage, a bogus configuration was tested as well as a
> configuration having an unknown part number.
>
> Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
> Tested-by: Michael Williamson <michael.williamson@criticallink.com>
> ---
> Built against linux-davinci tree.
>
> Changes since v2.
>
> - reworked logic to use fall-through logic for mityomapl138_cpugreq_init call
> per comments.
>
> arch/arm/mach-davinci/board-mityomapl138.c | 83 +++++++++++++++++++++++++---
> 1 files changed, 75 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
> index 0bb5f0c..8ba1937 100644
> --- a/arch/arm/mach-davinci/board-mityomapl138.c
> +++ b/arch/arm/mach-davinci/board-mityomapl138.c
> @@ -44,38 +44,109 @@ struct factory_config {
>
> static struct factory_config factory_config;
>
> +struct part_no_info {
> + const char *part_no; /* part number string of interest */
> + int max_freq; /* khz */
> +};
> +
> +static struct part_no_info mityomapl138_pn_info[] = {
> + {
> + .part_no = "L138-C",
> + .max_freq = 300000,
> + },
> + {
> + .part_no = "L138-D",
> + .max_freq = 375000,
> + },
> + {
> + .part_no = "L138-F",
> + .max_freq = 456000,
> + },
> + {
> + .part_no = "1808-C",
> + .max_freq = 300000,
> + },
> + {
> + .part_no = "1808-D",
> + .max_freq = 375000,
> + },
> + {
> + .part_no = "1808-F",
> + .max_freq = 456000,
> + },
> + {
> + .part_no = "1810-D",
> + .max_freq = 375000,
> + },
> +};
> +
> +#ifdef CONFIG_CPU_FREQ
> +static void mityomapl138_cpufreq_init(const char *partnum)
> +{
> + int i, ret;
> +
> + for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
> + /*
> + * the part number has additional characters beyond what is
> + * stored in the table. This information is not needed for
> + * determining the speed grade, and would require several
> + * more table entries. Only check the first N characters
> + * for a match.
> + */
> + if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
> + strlen(mityomapl138_pn_info[i].part_no))) {
> + da850_max_speed = mityomapl138_pn_info[i].max_freq;
> + break;
> + }
> + }
> +
> + ret = da850_register_cpufreq("pll0_sysclk3");
> + if (ret)
> + pr_warning("cpufreq registration failed: %d\n", ret);
> +}
> +#else
> +static void mityomapl138_cpufreq_init(const char *partnum) { }
> +#endif
> +
> static void read_factory_config(struct memory_accessor *a, void *context)
> {
> int ret;
> + const char *partnum = NULL;
> struct davinci_soc_info *soc_info = &davinci_soc_info;
>
> ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
> if (ret != sizeof(struct factory_config)) {
> pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
> ret);
> - return;
> + goto bad_config;
> }
>
> if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
> pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
> factory_config.magic);
> - return;
> + goto bad_config;
> }
>
> if (factory_config.version != FACTORY_CONFIG_VERSION) {
> pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
> factory_config.version);
> - return;
> + goto bad_config;
> }
>
> pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
> - pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
> if (is_valid_ether_addr(factory_config.mac))
> memcpy(soc_info->emac_pdata->mac_addr,
> factory_config.mac, ETH_ALEN);
> else
> pr_warning("MityOMAPL138: Invalid MAC found "
> "in factory config block\n");
> +
> + partnum = factory_config.partnum;
> + pr_info("MityOMAPL138: Part Number = %s\n", partnum);
> +
> +bad_config:
> + /* default maximum speed is valid for all platforms */
> + mityomapl138_cpufreq_init(NULL);
> }
>
> static struct at24_platform_data mityomapl138_fd_chip = {
> @@ -383,10 +454,6 @@ static void __init mityomapl138_init(void)
> if (ret)
> pr_warning("rtc setup failed: %d\n", ret);
>
> - ret = da850_register_cpufreq("pll0_sysclk3");
> - if (ret)
> - pr_warning("cpufreq registration failed: %d\n", ret);
> -
> ret = da8xx_register_cpuidle();
> if (ret)
> pr_warning("cpuidle registration failed: %d\n", ret);
^ permalink raw reply
* [PATCH 02/04] ARM i.MX25 Add SIM driver
From: Sascha Hauer @ 2011-01-03 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20736.212.121.242.58.1294045639.squirrel@mail.fqingenieria.es>
Hello Iban,
On Mon, Jan 03, 2011 at 10:07:19AM +0100, FQ | Iban Cerro wrote:
>
> This driver is slightly based on the Freescale original one, with several
> code simplifications. We made specially emphasis in avoiding any ISO7816
> code into the driver, which is not the right place to be. Driver mainly
> works via ioctl to configure and then using read/write functions to
> read/write smart cards.
>
> One important consideration (not clear in the User Manual from our point
> of view) is that there exist two SIM modules into the MX25 core, both of
> them in different memory position. This causes all accesses to SIM modules
> must be done via SIM0. This differs from the way the User Manual explains
> how to access the two different SIM modules, which seems is inherited from
> the MX51 core.
The following comments are mostly coding style related, running Lindent
and checkpatch.pl on this patch seems to be a good start for improving
this driver.
The main problem for pushing this driver to mainline is that you invent
a i.MX specific smartcard API. This is not a good idea and probably not
acceptable in mainline.
>
> Signed-off-by: Iban Cerro Galvez <iban@fqingenieria.es>
> ---
> arch/arm/plat-mxc/Kconfig | 7 +
> arch/arm/plat-mxc/Makefile | 1 +
> arch/arm/plat-mxc/include/mach/mxc_sim.h | 319 +++++++++++
> arch/arm/plat-mxc/sim.c | 874
> ++++++++++++++++++++++++++++++
Your mailer breaks lines which means that other people can't apply this
patch.
> 4 files changed, 1201 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/plat-mxc/include/mach/mxc_sim.h
> create mode 100644 arch/arm/plat-mxc/sim.c
>
> diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
> index 389f217..7b16d0d 100644
> --- a/arch/arm/plat-mxc/Kconfig
> +++ b/arch/arm/plat-mxc/Kconfig
> @@ -74,6 +74,13 @@ config MXC_PWM
> help
> Enable support for the i.MX PWM controller(s).
>
> +config MXC_SIM
> + tristate "Enable SIM driver"
> + select HAVE_SIM
> + help
> + Enable support for the i.MX SIM controller(s).
> +
> +
> config MXC_DEBUG_BOARD
> bool "Enable MXC debug board(for 3-stack)"
> help
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> index 5fd20e9..73073fb 100644
> --- a/arch/arm/plat-mxc/Makefile
> +++ b/arch/arm/plat-mxc/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
> obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
> obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
> obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
> +obj-$(CONFIG_MXC_SIM) += sim.o
> obj-$(CONFIG_MXC_PWM) += pwm.o
> obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
> obj-$(CONFIG_MXC_ULPI) += ulpi.o
> diff --git a/arch/arm/plat-mxc/include/mach/mxc_sim.h
> b/arch/arm/plat-mxc/include/mach/mxc_sim.h
> new file mode 100644
> index 0000000..74ff008
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/mxc_sim.h
> @@ -0,0 +1,319 @@
> +/*
> + * Copyright 2010-2011 FQ Ingenieria Electronica S.A.
> + *
> + * Adapted and simplify this driver to kernel mainline code style using
> + * other drivers from Freescale
> + * Jaume Ribot (jaume at fqingenieria.es)
> + * Iban Cerro Galvez (iban at fqingenieria.es)
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/*!
> + * @file mxc_sim.h
> + *
> + * @brief Driver for Freescale IMX SIM interface
> + *
> + */
> +
> +#ifndef MXC_SIM_INTERFACE_H
> +#define MXC_SIM_INTERFACE_H
> +
> +#define SIM_DRIVER_VERSION 0x01
> +
> +/* Transmit and receive buffer sizes */
> +#define SIM_XMT_BUFFER_SIZE 256
> +#define SIM_RCV_BUFFER_SIZE 256
> +
> +/*BAUD_DIVISOR */
> +#define SIM_DEFAULT_BAUD_DIV 372
> +
> +#define WRITE_TIMEOUT 1000
> +#define READ_TIMEOUT 1000
> +
> +
> +struct mxc_sim_platform_data {
> + unsigned int clk_rate;
> + char *clock_sim;
Please do not pass clock names to drivers. Use clk_get(dev, id) instead.
> + char *power_sim;
This seems to be unused.
> + int (*init)(struct platform_device *pdev);
> + void (*exit)(void);
> + unsigned int detect; /* 1 have detect pin, 0 not */
> + unsigned int sim_number; /* 0 or 1 */
> +};
> +
> +typedef struct {
> + unsigned long addr;
> + unsigned long data;
> +} sim_reg;
Do not typedef struct types, see Documentation/CodingStyle.
> +
> +/* Main SIM driver structure */
> +typedef struct {
> + /*SIM number 0, 1 */
> + int sim_number;
> + /* card inserted = 1, ATR received = 2, card removed = 0 */
> + int present;
> + /* current ATR or OPS state */
> + int state;
> + /* current power state */
> + int power;
> + /* error code occured during transfer */
> + int errval;
> + /* Clock id */
> + struct clk *clk;
> + /* on off clk*/
> + uint8_t clk_flag;
> + /* frequency of clk sim */
> + uint32_t clk_sim;
> + /* value of clk divisor*/
> + int uart_div;
> + /* IO map memory */
> + struct resource *res;
> + /* Mapped address */
> + void __iomem *ioaddr; /* Mapped address */
> + int ipb_irq; /* sim ipb IRQ num */
> + int dat_irq; /* sim dat IRQ num */
> + /* async notifier for card and ATR detection */
> + struct fasync_struct *fasync;
> + /* Platform specific data */
> + struct mxc_sim_platform_data *plat_data;
> +} sim_t;
ditto
> +
> +/* ISO7816-3 protocols */
> +#define SIM_PROTOCOL_T0 0
> +#define SIM_PROTOCOL_T1 1
> +
> +/* Transfer types for SIM_IOCTL_XFER */
> +#define SIM_XFER_TYPE_TPDU 0
> +#define SIM_XFER_TYPE_PTS 1
> +
> +/* Interface power states */
> +#define SIM_POWER_OFF 0
> +#define SIM_POWER_ON 1
> +
> +/* Return values for SIM_IOCTL_GET_PRESENSE */
> +#define SIM_PRESENT_REMOVED 0
> +#define SIM_PRESENT_DETECTED 1
> +#define SIM_PRESENT_OPERATIONAL 2
> +
> +/* Return values for SIM_IOCTL_GET_ERROR */
> +#define SIM_OK 0
> +#define SIM_E_ACCESS 1
> +#define SIM_E_TPDUSHORT 2
> +#define SIM_E_PTSEMPTY 3
> +#define SIM_E_INVALIDXFERTYPE 4
> +#define SIM_E_INVALIDXMTLENGTH 5
> +#define SIM_E_INVALIDRCVLENGTH 6
> +#define SIM_E_NACK 7
> +#define SIM_E_TIMEOUT 8
> +#define SIM_E_NOCARD 9
> +#define SIM_E_PARAM_FI_INVALID 10
> +#define SIM_E_PARAM_DI_INVALID 11
> +#define SIM_E_PARAM_FBYD_WITHFRACTION 12
> +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 13
> +#define SIM_E_PARAM_DIVISOR_RANGE 14
> +#define SIM_E_MALLOC 15
> +#define SIM_E_IRQ 16
> +#define SIM_E_POWERED_ON 17
> +#define SIM_E_POWERED_OFF 18
> +
> +/* ioctl encodings */
> +#define SIM_IOCTL_BASE 0xc0
> +#define SIM_IOCTL_VERSION _IOR(SIM_IOCTL_BASE, 1,unsigned char)
> +#define SIM_IOCTL_POWER_ON _IO(SIM_IOCTL_BASE, 2)
> +#define SIM_IOCTL_POWER_OFF _IO(SIM_IOCTL_BASE, 3)
> +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 4)
> +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 5)
> +#define SIM_IOCTL_CLK_PORT _IOW(SIM_IOCTL_BASE, 6, int)
> +#define SIM_IOCTL_RST_PORT _IOW(SIM_IOCTL_BASE, 7, int)
> +#define SIM_IOCTL_VCC_PORT _IOW(SIM_IOCTL_BASE, 8, int)
> +#define SIM_IOCTL_SET_CLK_SIM _IOW(SIM_IOCTL_BASE, 9, unsigned long)
> +#define SIM_IOCTL_SET_CLK_DIV _IOW(SIM_IOCTL_BASE, 10, int)
> +#define SIM_IOCTL_GET_REG _IOW(SIM_IOCTL_BASE, 11, sim_reg)
> +#define SIM_IOCTL_SET_REG _IOW(SIM_IOCTL_BASE, 12, sim_reg)
> +
> +/* Interface character references */
> +#define SIM_IFC_TXI(letter, number) (letter + number * 4)
> +#define SIM_IFC_TA1 SIM_IFC_TXI(0, 0)
> +#define SIM_IFC_TB1 SIM_IFC_TXI(0, 1)
> +#define SIM_IFC_TC1 SIM_IFC_TXI(0, 2)
> +#define SIM_IFC_TD1 SIM_IFC_TXI(0, 3)
> +#define SIM_IFC_TA2 SIM_IFC_TXI(1, 0)
> +#define SIM_IFC_TB2 SIM_IFC_TXI(1, 1)
> +#define SIM_IFC_TC2 SIM_IFC_TXI(1, 2)
> +#define SIM_IFC_TD2 SIM_IFC_TXI(1, 3)
> +#define SIM_IFC_TA3 SIM_IFC_TXI(2, 0)
> +#define SIM_IFC_TB3 SIM_IFC_TXI(2, 1)
> +#define SIM_IFC_TC3 SIM_IFC_TXI(2, 2)
> +#define SIM_IFC_TD3 SIM_IFC_TXI(2, 3)
> +#define SIM_IFC_TA4 SIM_IFC_TXI(3, 0)
> +#define SIM_IFC_TB4 SIM_IFC_TXI(3, 1)
> +#define SIM_IFC_TC4 SIM_IFC_TXI(3, 2)
> +#define SIM_IFC_TD4 SIM_IFC_TXI(3, 3)
> +
> +/* ATR and OPS states */
> +#define SIM_STATE_REMOVED 0
> +#define SIM_STATE_OPERATIONAL_IDLE 1
> +#define SIM_STATE_OPERATIONAL_COMMAND 2
> +#define SIM_STATE_OPERATIONAL_RESPONSE 3
> +#define SIM_STATE_OPERATIONAL_STATUS1 4
> +#define SIM_STATE_OPERATIONAL_STATUS2 5
> +#define SIM_STATE_OPERATIONAL_PTS 6
> +#define SIM_STATE_DETECTED_ATR_T0 7
> +#define SIM_STATE_DETECTED_ATR_TS 8
> +#define SIM_STATE_DETECTED_ATR_TXI 9
> +#define SIM_STATE_DETECTED_ATR_THB 10
> +#define SIM_STATE_DETECTED_ATR_TCK 11
> +
> +/* Definitions of the offset of the SIM hardware registers */
> +#define PORT1_CNTL 0x00 /* 00 */
> +#define SETUP 0x04 /* 04 */
> +#define PORT1_DETECT 0x08 /* 08 */
> +#define PORT1_XMT_BUF 0x0C /* 0c */
> +#define PORT1_RCV_BUF 0x10 /* 10 */
> +#define PORT0_CNTL 0x14 /* 14 */
> +#define CNTL 0x18 /* 18 */
> +#define CLK_PRESCALER 0x1C /* 1c */
> +#define RCV_THRESHOLD 0x20 /* 20 */
> +#define ENABLE 0x24 /* 24 */
> +#define XMT_STATUS 0x28 /* 28 */
> +#define RCV_STATUS 0x2C /* 2c */
> +#define INT_MASK 0x30 /* 30 */
> +#define PORTO_XMT_BUF 0x34 /* 34 */
> +#define PORT0_RCV_BUF 0x38 /* 38 */
> +#define PORT0_DETECT 0x3C /* 3c */
> +#define DATA_FORMAT 0x40 /* 40 */
> +#define XMT_THRESHOLD 0x44 /* 44 */
> +#define GUARD_CNTL 0x48 /* 48 */
> +#define OD_CONFIG 0x4C /* 4c */
> +#define RESET_CNTL 0x50 /* 50 */
> +#define CHAR_WAIT 0x54 /* 54 */
> +#define GPCNT 0x58 /* 58 */
> +#define DIVISOR 0x5C /* 5c */
> +#define BWT 0x60 /* 60 */
> +#define BGT 0x64 /* 64 */
> +#define BWT_H 0x68 /* 68 */
> +#define XMT_FIFO_STAT 0x6C /* 6c */
> +#define RCV_FIFO_CNT 0x70 /* 70 */
> +#define RCV_FIFO_WPTR 0x74 /* 74 */
> +#define RCV_FIFO_RPTR 0x78 /* 78 */
so 0x78 means 78, who would have guessed that? Please remove the comments.
> +
> +/* SIM port[0|1]_cntl register bits */
> +#define SIM_PORT_CNTL_SFPD (1<<7)
> +#define SIM_PORT_CNTL_3VOLT (1<<6)
> +#define SIM_PORT_CNTL_SCSP (1<<5)
> +#define SIM_PORT_CNTL_SCEN (1<<4)
> +#define SIM_PORT_CNTL_SRST (1<<3)
> +#define SIM_PORT_CNTL_STEN (1<<2)
> +#define SIM_PORT_CNTL_SVEN (1<<1)
> +#define SIM_PORT_CNTL_SAPD (1<<0)
> +
> +#define MX25_SIM_SETUP_P1_EN (1<<1) // Port 1 enabled
> +#define MX25_SIM_SETUP_AMODE_EN (1<<0) // Alternate port enabled
Please do not use C99 style comments.
> +
> +/* SIM od_config register bits */
> +#define SIM_OD_CONFIG_OD_P1 (1<<1)
> +#define SIM_OD_CONFIG_OD_P0 (1<<0)
> +
> +/* SIM enable register bits */
> +#define SIM_ENABLE_XMTEN (1<<1)
> +#define SIM_ENABLE_RCVEN (1<<0)
> +
> +/* SIM int_mask register bits */
> +#define SIM_INT_MASK_RFEM (1<<13)
> +#define SIM_INT_MASK_BGTM (1<<12)
> +#define SIM_INT_MASK_BWTM (1<<11)
> +#define SIM_INT_MASK_RTM (1<<10)
> +#define SIM_INT_MASK_CWTM (1<<9)
> +#define SIM_INT_MASK_GPCM (1<<8)
> +#define SIM_INT_MASK_TDTFM (1<<7)
> +#define SIM_INT_MASK_TFOM (1<<6)
> +#define SIM_INT_MASK_XTM (1<<5)
> +#define SIM_INT_MASK_TFEIM (1<<4)
> +#define SIM_INT_MASK_ETCIM (1<<3)
> +#define SIM_INT_MASK_OIM (1<<2)
> +#define SIM_INT_MASK_TCIM (1<<1)
> +#define SIM_INT_MASK_RIM (1<<0)
> +
> +/* SIM xmt_status register bits */
> +#define SIM_XMT_STATUS_GPCNT (1<<8)
> +#define SIM_XMT_STATUS_TDTF (1<<7)
> +#define SIM_XMT_STATUS_TFO (1<<6)
> +#define SIM_XMT_STATUS_TC (1<<5)
> +#define SIM_XMT_STATUS_ETC (1<<4)
> +#define SIM_XMT_STATUS_TFE (1<<3)
> +#define SIM_XMT_STATUS_XTE (1<<0)
> +
> +/* SIM rcv_status register bits */
> +#define SIM_RCV_STATUS_BGT (1<<11)
> +#define SIM_RCV_STATUS_BWT (1<<10)
> +#define SIM_RCV_STATUS_RTE (1<<9)
> +#define SIM_RCV_STATUS_CWT (1<<8)
> +#define SIM_RCV_STATUS_CRCOK (1<<7)
> +#define SIM_RCV_STATUS_LRCOK (1<<6)
> +#define SIM_RCV_STATUS_RDRF (1<<5)
> +#define SIM_RCV_STATUS_RFD (1<<4)
> +#define SIM_RCV_STATUS_RFE (1<<1)
> +#define SIM_RCV_STATUS_OEF (1<<0)
> +
> +/* SIM cntl register bits */
> +#define SIM_CNTL_BWTEN (1<<15)
> +#define SIM_CNTL_XMT_CRC_LRC (1<<14)
> +#define SIM_CNTL_CRCEN (1<<13)
> +#define SIM_CNTL_LRCEN (1<<12)
> +#define SIM_CNTL_CWTEN (1<<11)
> +#define SIM_CNTL_SAMPLE12 (1<<4)
> +#define SIM_CNTL_ONACK (1<<3)
> +#define SIM_CNTL_ANACK (1<<2)
> +#define SIM_CNTL_ICM (1<<1)
> +#define SIM_CNTL_GPCNT_CLK_SEL(x) ((x&0x03)<<9)
Please add some spacing here, like this: ((x & 0x3) << 9)
See Documentation/CodingStyle for more information.
Also, there are braces missing around x, it should be:
(((x) & 0x3) << 9)
> +#define SIM_CNTL_GPCNT_CLK_SEL_MASK (0x03<<9)
> +#define SIM_CNTL_BAUD_SEL(x) ((x&0x07)<<6)
> +#define SIM_CNTL_BAUD_SEL_MASK (0x07<<6)
> +
> +/* SIM rcv_threshold register bits */
> +#define SIM_RCV_THRESHOLD_RTH(x) ((x&0x0f)<<9)
> +#define SIM_RCV_THRESHOLD_RTH_MASK (0x0f<<9)
> +#define SIM_RCV_THRESHOLD_RDT(x) ((x&0x1ff)<<0)
> +#define SIM_RCV_THRESHOLD_RDT_MASK (0x1ff<<0)
> +
> +/* SIM xmt_threshold register bits */
> +#define SIM_XMT_THRESHOLD_XTH(x) ((x&0x0f)<<4)
> +#define SIM_XMT_THRESHOLD_XTH_MASK (0x0f<<4)
> +#define SIM_XMT_THRESHOLD_TDT(x) ((x&0x0f)<<0)
> +#define SIM_XMT_THRESHOLD_TDT_MASK (0x0f<<0)
> +
> +/* SIM guard_cntl register bits */
> +#define SIM_GUARD_CNTL_RCVR11 (1<<8)
> +#define SIM_GIARD_CNTL_GETU(x) (x&0xff)
> +#define SIM_GIARD_CNTL_GETU_MASK (0xff)
> +
> +/* SIM port[0|]_detect register bits */
> +#define SIM_PORT_DETECT_SPDS (1<<3)
> +#define SIM_PORT_DETECT_SPDP (1<<2)
> +#define SIM_PORT_DETECT_SDI (1<<1)
> +#define SIM_PORT_DETECT_SDIM (1<<0)
> +
> +/* SIM XMT_FIFO_STAT*/
> +#define SIM_XMT_FIFO_XMT_CNT_MASK (0x0f<<8)
> +#define SIM_XMT_FIFO_XMT_WPTR_MASK (0x0f<<4)
> +#define SIM_XMT_FIFO_XMT_RPTR_MASK (0x0f<<0)
> +
> +/* SIM PORT_RCV_BUF */
> +#define PORT_RCV_BUF_PE (1<<8)
> +#define PORT_RCV_BUF_FE (1<<9)
> +#define PORT_RCV_BUF_CWT (1<<10)
> +/* SIM RESET_CNTL */
> +#define SIM_RESET_CNTL_DBUG (1<<6)
> +#define SIM_RESET_CNTL_STOP (1<<5)
> +#define SIM_RESET_CNTL_DOZE (1<<4)
> +#define SIM_RESET_CNTL_KILL_CLOCK (1<<3)
> +#define SIM_RESET_CNTL_SOFT_RST (1<<2)
> +#define SIM_RESET_CNTL_FLUSH_XMT (1<<1)
> +#define SIM_RESET_CNTL_FLUSH_RCV (1<<0)
> +/* END of REGS definitions */
> +#endif
> diff --git a/arch/arm/plat-mxc/sim.c b/arch/arm/plat-mxc/sim.c
> new file mode 100644
> index 0000000..7af073c
> --- /dev/null
> +++ b/arch/arm/plat-mxc/sim.c
> @@ -0,0 +1,874 @@
> +/*
> + * Copyright 2010-2011 FQ Ingenieria Electronica S.A.
> + *
> + * Adapted and simplify this driver to kernel mainline code style using
> + * other drivers from Freescale
> + * Jaume Ribot (jaume at fqingenieria.es)
> + * Iban Cerro Galvez (iban at fqingenieria.es)
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/*!
> + * @file mxc_sim.c
> + *
> + * @brief Driver for Freescale IMX SIM interface
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/ioport.h>
> +#include <linux/kernel.h>
> +#include <linux/delay.h>
> +
> +#include <linux/sched.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/poll.h>
> +#include <linux/miscdevice.h>
> +#include <linux/clk.h>
> +#include <linux/types.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <asm/io.h>
> +#include <mach/hardware.h>
> +#include <mach/mxc_sim.h>
> +
> +#define DRIVER_NAME "mxc_sim"
> +#define SIM1_DEV_NAME "mxc_sim_0"
> +#define SIM2_DEV_NAME "mxc_sim_1"
> +
> +static struct miscdevice sim_dev;
> +
> +#define sim_debug(fmt, ...) \
> + printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
Please do not define your own debug functions. dev_dbg is the weapon of
choice here.
> +
> +
> +/* Function: sim_clear_ports
> + *
> + * Description: function to unset reset, Vcc_enable or Clk_enable
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + * uint32_t value value to set port
> + */
> +static void sim_clear_ports(sim_t *sim, uint32_t value)
> +{
> + uint32_t reg_data;
> + void __iomem *addr;
> +
> +#if defined(CONFIG_SOC_IMX25)
> + if (cpu_is_mx25()) {
> + addr = sim->ioaddr + PORT0_CNTL;
> + }
broken indention.
> +#else
> + if (sim->sim_number ==0)
> + addr = sim->ioaddr + PORT0_CNTL;
> + else
> + addr = sim->ioaddr + PORT1_CNTL;
> +#endif
This #ifdef looks wrong here. The idea is to make the driver independent
of compile time options. Now with this ifdef, if i.MX25 is enabled, it
won't be working on any other SoC.
> +
> + reg_data = __raw_readl(addr);
> + reg_data &= ~value;
> + __raw_writel(reg_data, addr);
> +}
> +
> +
> +/* Function: sim_set_ports
> + *
> + * Description: function to set Reset, Vcc enable or Clk_enabble
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + * uint32_t value value to set port
> + */
> +static void sim_set_ports(sim_t *sim, uint32_t value)
> +{
> + uint32_t reg_data;
> + void __iomem *addr;
> +
> +#if defined(CONFIG_SOC_IMX25)
> + if (cpu_is_mx25()) {
> + addr = sim->ioaddr + PORT0_CNTL;
> + }
> +#else
> + if (sim->sim_number ==0)
> + addr = sim->ioaddr + PORT0_CNTL;
> + else
> + addr = sim->ioaddr + PORT1_CNTL;
> +#endif
> +
> + reg_data = __raw_readl(addr);
> + reg_data |= value;
> + __raw_writel(reg_data, addr);
> +
> +}
> +
> +
> +/* Function: sim_power_on
> + *
> + * Description: run the power on sequence. Follow sequence explained in
> RM 39.5
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_power_on(sim_t *sim)
> +{
> + uint32_t reg_data;
> +
> + // Power on sequence
This comment is not very useful.
> + sim_debug("%s Powering on the sim port.\n", __func__);
> +
> + // Enable Vcc enable port
> + sim_set_ports(sim, SIM_PORT_CNTL_SVEN);
> + msleep(10);//TODO: adjust this delay
> +
> + // Enable CLK enable Port
> + sim_set_ports(sim, SIM_PORT_CNTL_SCEN);
> + msleep(10);//TODO: adjust this delay
> +
> + // Configure RCV parameters
> + reg_data = SIM_RCV_THRESHOLD_RTH(0) | SIM_RCV_THRESHOLD_RDT(1);
> + __raw_writel(reg_data, sim->ioaddr + RCV_THRESHOLD);
> + __raw_writel(SIM_RCV_STATUS_RDRF, sim->ioaddr + RCV_STATUS);
> +
> + //Configure int
> + reg_data = __raw_readl(sim->ioaddr + INT_MASK);
> + reg_data &= ~SIM_INT_MASK_RIM;
> + __raw_writel(reg_data, sim->ioaddr + INT_MASK);
> +
> + //Duplicate in function sim_start
> + __raw_writel(31, sim->ioaddr + DIVISOR);
> + reg_data = __raw_readl(sim->ioaddr + CNTL);
> + reg_data |= SIM_CNTL_SAMPLE12;
> + __raw_writel(reg_data, sim->ioaddr + CNTL);
> +
> + // Enable RCV
> + reg_data = __raw_readl(sim->ioaddr + ENABLE);
> + reg_data |= SIM_ENABLE_RCVEN;
> + __raw_writel(reg_data, sim->ioaddr + ENABLE);
> +
> + // Enable RST
> + sim_set_ports(sim, SIM_PORT_CNTL_SRST);
> + msleep(10);//TODO: adjust this delay
> +
> + sim->power = SIM_POWER_ON;
> +
> +};
> +
> +/* Function: sim_power_off
> + *
> + * Description: run the power off sequence
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_power_off(sim_t *sim)
> +{
> + uint32_t reg_data;
> +
> + sim_debug("%s entering.\n", __func__);
> + /* sim_power_off sequence */
> +
> + //disable clk
> + sim_clear_ports(sim, SIM_PORT_CNTL_SCEN);
> +
> + reg_data = __raw_readl(sim->ioaddr + ENABLE);
> + reg_data &= ~SIM_ENABLE_RCVEN;
> + __raw_writel(reg_data, sim->ioaddr + ENABLE);
> +
> + reg_data = __raw_readl(sim->ioaddr + INT_MASK);
> + reg_data |= SIM_INT_MASK_RIM;
> + __raw_writel(reg_data, sim->ioaddr + INT_MASK);
> +
> + __raw_writel(0, sim->ioaddr + RCV_THRESHOLD);
> +
> + //Disable RST
> + sim_clear_ports(sim, SIM_PORT_CNTL_SRST);
> + //Disable Vcc enable port
> + sim_clear_ports(sim, SIM_PORT_CNTL_SVEN);
> +
> + sim->power = SIM_POWER_OFF;
> +};
> +
> +/* Function: sim_set_clk_sim
> + *
> + * Description: Set CLK SIM frequency
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +uint32_t sim_set_clk_sim(sim_t *sim)
> +{
> + uint32_t clk_rate, clk_div = 0;
> + // get ipg_clk
> + clk_rate = clk_get_rate(sim->clk);
> + // calcule divisor
> + clk_div = clk_rate / sim->clk_sim;
> + if (clk_rate % sim->clk_sim)
> + clk_div++;
> + //write divisor
> + __raw_writel(clk_div, sim->ioaddr + CLK_PRESCALER);
> + //calculate real Value
> + clk_rate =clk_rate/clk_div;
> +
> + sim_debug("%s prescaler is 0x%x.\n", __func__, clk_div);
> + sim_debug("Clk = %d Hz\n", clk_rate);
> +
> + return clk_rate;
> +}
> +
> +/* Function: sim_set_clk_uart_divisor
> + *
> + * Description: Set SIM Uart divisor frequency
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +int sim_set_clk_uart_divisor(sim_t *sim)
> +{
> + uint32_t reg, divisor;
> +
> + //ajust baud_sel -> divisor register
s/ajust/adjust/
> + reg = __raw_readl(sim->ioaddr + CNTL);
> + //ajust sample 12
> + if ((sim->uart_div % 12) == 0)
> + {
See Documentaion/CodingStyle for placing braces.
> + reg |= SIM_CNTL_SAMPLE12;
> + divisor=sim->uart_div/12;
> + }
> + else if ((sim->uart_div % 8) == 0)
> + {
> + reg &= ~SIM_CNTL_SAMPLE12;
> + divisor=sim->uart_div/8;
> + }
> + else
> + {
> + sim_debug("%s no valid divisor \n", __func__);
> + return -1;
> + }
> + // put 111 in baud_sel for use Divisor register
> + reg |= SIM_CNTL_BAUD_SEL(7);
> + __raw_writel(reg, sim->ioaddr + CNTL);
> + //ajust Divisor register
> + __raw_writel(divisor, sim->ioaddr + DIVISOR );
> + sim_debug("%s divisor is %d.\n", __func__, sim->uart_div);
> +
> + return 0;
> +}
> +
> +
> +
> +/* Function: sim_start
> + *
> + * Description: ramp up the SIM interface.
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +static void sim_start(sim_t *sim)
> +{
> + uint32_t reg_data = 0;
> +
> + sim_debug("%s entering.\n", __func__);
> + // Configuring SIM for Operation
> + // Adjust XMT thresholds (no NACK and 4 bytes or less to activate TDTF bit
> + reg_data = SIM_XMT_THRESHOLD_XTH(0) | SIM_XMT_THRESHOLD_TDT(4);
> + __raw_writel(reg_data, sim->ioaddr + XMT_THRESHOLD);
> + // Enable SIM port N and alternate port disabled -> Only applies to MX51
> + // Always eanble port 0,
> +
> + // Always enable port 0 -> Duplicated SIM core
> + __raw_writel(0x00, sim->ioaddr + SETUP);
> +
> + // Adjust clock divider in function of platform definitions
> + // 66.5 / 5 -> 13.5 -> 14 (4.75MHZ initial frequency)
> + sim->clk_sim = sim->plat_data->clk_rate;
> + sim_set_clk_sim(sim);
> +
> + // Adjust Control register
> + reg_data = __raw_readl(sim->ioaddr + CNTL);
> + reg_data |= SIM_CNTL_ANACK | SIM_CNTL_ICM;
> + __raw_writel(reg_data, sim->ioaddr + CNTL);
> +
> + // Adjust BAUD divider
> + sim->uart_div=SIM_DEFAULT_BAUD_DIV;
> + sim_set_clk_uart_divisor(sim);
> +
> + // Adjust Open Drain in Port 0 XMT configuration register
> + reg_data = __raw_readl(sim->ioaddr + OD_CONFIG);
> + reg_data |= SIM_OD_CONFIG_OD_P0 | SIM_OD_CONFIG_OD_P1;
> + __raw_writel(reg_data, sim->ioaddr + OD_CONFIG);
> +
> + // Adjust Port 0
> + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
> + reg_data |= SIM_PORT_CNTL_3VOLT | SIM_PORT_CNTL_STEN;
> + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
> +
> + // Since there is no PD0 layout on MX51, assume that there is a SIM card
> in slot defaulty.
> + if (0 == (sim->plat_data->detect)) {
> + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
> + reg_data |= SIM_PORT_DETECT_SPDS;
> + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
> + sim->present = SIM_PRESENT_DETECTED;
> + }
> +
> + // FQ enable SIM present on the future
> + if (sim->present == SIM_PRESENT_DETECTED)
> + sim_power_on(sim);
> +
> +};
> +
> +/* Function: sim_stop
> + *
> + * Description: shut down the SIM interface
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_stop(sim_t *sim)
> +{
> + sim_debug("%s entering.\n", __func__);
> + __raw_writel(0, sim->ioaddr + SETUP);
> + __raw_writel(0, sim->ioaddr + ENABLE);
> + __raw_writel(0, sim->ioaddr + PORT0_CNTL);
> + __raw_writel(SIM_CNTL_ANACK | SIM_CNTL_ICM, sim->ioaddr + CNTL);
> + __raw_writel(0, sim->ioaddr + CLK_PRESCALER);
> + __raw_writel(0, sim->ioaddr + SETUP);
> + __raw_writel(0, sim->ioaddr + OD_CONFIG);
> + __raw_writel(0, sim->ioaddr + XMT_THRESHOLD);
> + //Clear XMT_STATUS
> + __raw_writel( SIM_XMT_STATUS_TDTF | SIM_XMT_STATUS_TC |
> + SIM_XMT_STATUS_ETC | SIM_XMT_STATUS_TFE , sim->ioaddr +
> XMT_STATUS);
> + //Enable SOFT_RESET
> + __raw_writel(SIM_RESET_CNTL_SOFT_RST , sim->ioaddr + RESET_CNTL);
> + mdelay(1);//TODO: adjust this delay
> +};
> +
> +/* Function: sim_data_reset
> + *
> + * Description: reset a SIM structure to default values
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_data_reset(sim_t *sim)
> +{
> + sim->present = SIM_PRESENT_REMOVED;
> + sim->state = SIM_STATE_REMOVED;
> + sim->power = SIM_POWER_OFF;
> + sim->errval = SIM_OK;
> +};
> +
> +/* Function: sim_cold_reset
> + *
> + * Description: cold reset the SIM interface, including card
> + * power down and interface hardware reset.
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_cold_reset(sim_t *sim)
> +{
> + sim_debug("%s entering.\n", __func__);
> + if (sim->present != SIM_PRESENT_REMOVED) {
> + sim_power_off(sim);
> + sim_stop(sim);
> + sim_data_reset(sim);
> + sim->state = SIM_STATE_DETECTED_ATR_T0;
> + sim->present = SIM_PRESENT_DETECTED;
> + msleep(50);//TODO: adjust this delay
> + sim_start(sim);
> + sim_power_on(sim);
> + };
> +};
> +
> +/* Function: sim_warm_reset
> + *
> + * Description: warm reset the SIM interface: just invoke the
> + * reset signal and reset the SIM structure for the interface.
> + *
> + * Parameters:
> + * sim_t* sim pointer to SIM device handler
> + */
> +
> +static void sim_warm_reset(sim_t *sim)
> +{
> + sim_debug("%s entering.\n", __func__);
> + if (sim->present != SIM_PRESENT_REMOVED) {
> + sim_set_ports(sim,SIM_PORT_CNTL_SRST);
> + sim_data_reset(sim);
> + msleep(50);//TODO: adjust this delay
> + sim_clear_ports(sim,SIM_PORT_CNTL_SRST);
> +
> + };
> +};
> +
> +/* Function: sim_ioctl
> + *
> + * Description: handle ioctl calls
> + *
> + * Parameters: OS specific
> + */
> +
> +static long sim_ioctl(struct file *file, unsigned int cmd, unsigned long
> arg)
> +{
> + int ret=0, value=-1;
> + unsigned long real_freq;
> + unsigned char version = SIM_DRIVER_VERSION;
> + sim_t *sim = (sim_t *) file->private_data;
> + sim_reg s_reg = {0,0};
> +
> + sim_debug("%s cmd %d \n", __func__, cmd);
> + switch (cmd) {
> + sim_debug("ioctl cmd %d is issued...\n", cmd);
> +
> + case SIM_IOCTL_VERSION:
> + sim_debug("ioctl cmd SIM_IOCTL_VERSION\n");
> + ret = copy_to_user((unsigned char *) arg, &version,
> + sizeof(unsigned char));
> + break;
> +
> + case SIM_IOCTL_POWER_ON:
> + sim_debug("ioctl cmd SIM_IOCTL_POWER_ON\n");
> + if (sim->power == SIM_POWER_ON) {
> + ret = -SIM_E_POWERED_ON;
> + break;
> + };
> + sim_power_on(sim);
> + break;
> +
> + case SIM_IOCTL_POWER_OFF:
> + sim_debug("ioctl cmd SIM_IOCTL_POWER_OFF\n");
> + if (sim->power == SIM_POWER_OFF) {
> + ret = -SIM_E_POWERED_OFF;
> + break;
> + };
> + sim_power_off(sim);
> + break;
> +
> + case SIM_IOCTL_COLD_RESET:
> + sim_debug("ioctl cmd SIM_IOCTL_COLD_RESET\n");
> + if (sim->power == SIM_POWER_OFF) {
> + ret = -SIM_E_POWERED_OFF;
> + break;
> + };
> + sim_cold_reset(sim);
> + break;
> +
> + case SIM_IOCTL_WARM_RESET:
> + sim_debug("ioctl cmd SIM_IOCTL_WARM_RESET\n");
> + sim_warm_reset(sim);
> + if (sim->power == SIM_POWER_OFF) {
> + ret = -SIM_E_POWERED_OFF;
> + break;
> + };
> + break;
> +
> + case SIM_IOCTL_CLK_PORT:
> + sim_debug("ioctl cmd SIM_IOCTL_CLK_PORT\n");
> + ret = copy_from_user(&value, (int *) arg,
> + sizeof(int));
> + if (value == 0)
> + sim_set_ports(sim, SIM_PORT_CNTL_SCEN);
> + else
> + sim_clear_ports(sim, SIM_PORT_CNTL_SCEN);
> + break;
> +
> + case SIM_IOCTL_RST_PORT:
> + sim_debug("ioctl cmd SIM_IOCTL_RST_PORT\n");
> + ret = copy_from_user(&value, (int *) arg,
> + sizeof(int));
> + if (value == 0)
> + sim_set_ports(sim, SIM_PORT_CNTL_SRST);
> + else
> + sim_clear_ports(sim, SIM_PORT_CNTL_SRST);
> + break;
> +
> + case SIM_IOCTL_VCC_PORT:
> + sim_debug("ioctl cmd SIM_IOCTL_VCC_PORT\n");
> + ret = copy_from_user(&value, (int *) arg,
> + sizeof(int));
> + if (value == 0)
> + sim_set_ports(sim, SIM_PORT_CNTL_SVEN);
> + else
> + sim_clear_ports(sim, SIM_PORT_CNTL_SVEN);
> + break;
> +
> + case SIM_IOCTL_SET_CLK_SIM:
> + sim_debug("ioctl cmd SIM_IOCTL_SET_CLK_SIM\n");
> + ret = copy_from_user(&real_freq, (unsigned long *) arg,
> + sizeof(unsigned long));
> + if (sim->clk_sim > 0)
> + {
> + sim->clk_sim = real_freq;
> + real_freq = sim_set_clk_sim(sim);
> + }
> + else
> + {
> + sim_debug("Invalid Freq. %lu Hz\n",real_freq );
> + real_freq = -1;
> + }
> + ret = copy_to_user((unsigned long *) arg, &real_freq,
> + sizeof(unsigned long));
> + break;
> +
> + case SIM_IOCTL_SET_CLK_DIV:
> + sim_debug("ioctl cmd SIM_IOCTL_SET_CLK_DIV\n");
> + ret = copy_from_user(&value, (int *) arg,
> + sizeof(int));
> + if (sim->uart_div > 0)
> + {
> + sim->uart_div = value;
> + ret = sim_set_clk_uart_divisor(sim);
> + }
> + else
> + {
> + sim_debug("Invalid DIV. %d\n",value);
> + }
> + break;
> +
> + /*debug register*/
> + case SIM_IOCTL_GET_REG:
> + sim_debug("ioctl cmd SIM_IOCTL_GET_REG\n");
> + ret = copy_from_user(&s_reg, (sim_reg *) arg, sizeof(sim_reg));
> + s_reg.data =(unsigned long) __raw_readl(s_reg.addr);
> + ret = copy_to_user((sim_reg *) arg, &s_reg, sizeof(sim_reg));
> + break;
> +
> + case SIM_IOCTL_SET_REG:
> + sim_debug("ioctl cmd SIM_IOCTL_SET_REG\n");
> + ret = copy_from_user(&s_reg, (sim_reg *) arg, sizeof(sim_reg));
> + __raw_writel( (uint32_t) s_reg.data, sim->ioaddr + s_reg.addr);
> + break;
> + };
> +
> + return ret;
> +};
> +
> +/* Function: sim_write
> + *
> + * Description: handle write calls
> + *
> + * Parameters: OS specific
> + */
> +static ssize_t sim_write(struct file *file, const char *user_buf,
> + size_t count, loff_t *ppos)
> +{
> + int ret=0, i;
> + uint32_t reg_data=0;
> + sim_t *sim = (sim_t *) file->private_data;
> + char write_buffer[SIM_XMT_BUFFER_SIZE];
> + int timeout;
> +
> + sim_debug("%s entering.\n", __func__);
> +
> + ret = copy_from_user(write_buffer, user_buf,count);
broken indention.
> + if (ret)
> + return -EFAULT;
> +
> + //start XMT
> + reg_data = __raw_readl(sim->ioaddr + ENABLE);
> + reg_data |= SIM_ENABLE_XMTEN;
> + __raw_writel(reg_data, sim->ioaddr + ENABLE);
> +
> + for (i=0; i < count; i++)
> + {
> + //transmit 1 Byte
> + __raw_writel( write_buffer[i],sim->ioaddr + PORT1_XMT_BUF );
> + sim_debug( "TX = %02x\n", write_buffer[i] );
> +
> + // wait write 1 Byte TODO: interupts
> + timeout= WRITE_TIMEOUT;
> + do {
> + reg_data = __raw_readl( sim->ioaddr + XMT_FIFO_STAT );
> + reg_data = ( reg_data && SIM_XMT_FIFO_XMT_CNT_MASK ) >> 8;
> + sim_debug("wait write, timeout = %d", timeout );
> + timeout--;
> + }while ( reg_data > 0 && timeout != 0 );
broken indention.
> + }
> +
> + //disable write
> + reg_data = __raw_readl( sim->ioaddr + ENABLE );
> + reg_data &= ~SIM_ENABLE_XMTEN;
> + __raw_writel( reg_data, sim->ioaddr + ENABLE );
> +
> + return i;
> +};
> +
> +/* Function: sim_read
> + *
> + * Description: handle read calls
> + *
> + * Parameters: OS specific
> + */
> +static ssize_t sim_read(struct file *file, char *user_buf,
> + size_t count, loff_t *ppos)
> +{
> + int ret=0;
> + char read_buffer[SIM_RCV_BUFFER_SIZE];
> + sim_t *sim = (sim_t *) file->private_data;
> + int i=0;
> + int timeout = READ_TIMEOUT;
> +
> + sim_debug("%s entering.\n", __func__);
> +
> + while (__raw_readl(sim->ioaddr + RCV_FIFO_CNT) != 0 && i < count &&
> timeout > 0 ) {
> + uint32_t data;
> + data = __raw_readl(sim->ioaddr + PORT1_RCV_BUF);
> + sim_debug("RX = %02x\n", data);
> + //detect parity ERROR or FRAME ERROR or CWT ERROR
> + if ( data & (PORT_RCV_BUF_PE | PORT_RCV_BUF_FE | PORT_RCV_BUF_CWT ) )
> + {
> + printk(KERN_ERR "ERROR READ !\n");
> + return IRQ_HANDLED;
> + }
> + else{
> + read_buffer[i] = (char) data;
> + i++;
> + }
> + timeout--;
> + };
> + ret = copy_to_user(user_buf, read_buffer,i);
> + if (ret)
> + return -EFAULT;
> +
> + return i;
> +}
> +
> +
> +/* Function: sim_open
> + *
> + * Description: ramp up interface when being opened
> + *
> + * Parameters: OS specific
> + */
> +
> +static int sim_open(struct inode *inode, struct file *file)
> +{
> + int errval = SIM_OK;
> +
> + sim_t *sim = dev_get_drvdata(sim_dev.parent);
> + file->private_data = sim;
> +
> + sim_debug("%s entering.\n", __func__);
> + if (!sim->ioaddr) {
> + errval = -ENOMEM;
> + return errval;
> + }
> +
> + if (!(sim->clk_flag)) {
> + sim_debug("\n%s enable the clock ret = %d\n", __func__,
> clk_enable(sim->clk) );
> + sim->clk_flag = 1;
> + }
> +
> + sim_start(sim);
> +
> + return errval;
> +};
> +/* Function: sim_fasync
> + *
> + * Description: async handler
> + *
> + * Parameters: OS specific
> + */
> +
> +static int sim_fasync(int fd, struct file *file, int mode)
> +{
> + sim_t *sim = (sim_t *) file->private_data;
> + pr_debug("%s entering.\n", __func__);
> + return fasync_helper(fd, file, mode, &sim->fasync);
> +}
> +/* Function: sim_release
> + *
> + * Description: shut down interface when being closed
> + *
> + * Parameters: OS specific
> + */
> +
> +static int sim_release(struct inode *inode, struct file *file)
> +{
> + uint32_t reg_data;
> +
> + sim_t *sim = (sim_t *) file->private_data;
> +
> + sim_debug("%s entering.\n", __func__);
> + if (sim->clk_flag) {
> + sim_debug("\n%s disable the clock\n", __func__);
> + clk_disable(sim->clk);
> + sim->clk_flag = 0;
> + }
> +
> + /* disable presense detection */
> + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
> + __raw_writel(reg_data | SIM_PORT_DETECT_SDIM, sim->ioaddr + PORT0_DETECT);
> +
> + if (sim->present != SIM_PRESENT_REMOVED) {
> + sim_power_off(sim);
> + if (sim->fasync)
> + kill_fasync(&sim->fasync, SIGIO, POLL_IN);
> + };
> +
> + sim_stop(sim);
> +
> + sim_fasync(-1, file, 0);
> +
> + sim_debug("exit\n");
> + return 0;
> +};
> +
> +static const struct file_operations sim_fops = {
> + .owner = THIS_MODULE,
> + .read = sim_read,
> + .write = sim_write,
> + .open = sim_open,
> + .unlocked_ioctl = sim_ioctl,
> + .fasync = sim_fasync, // FQ commented
> + .release = sim_release
> +};
> +
> +// TODO -> Dev name must be dynamic or include all SIM ports
> +/*
> +static struct miscdevice sim_dev = {
> + MISC_DYNAMIC_MINOR,
> + NULL,
> + &sim_fops,
> +};
> +*/
> +
> +/*****************************************************************************\
> + *
> *
> + * Driver init/exit
> *
> + *
> *
> +\*****************************************************************************/
Trailing whitespaces here.
> +
> +static int sim_probe(struct platform_device *pdev)
> +{
> + int ret = 0;
> + struct mxc_sim_platform_data *sim_plat = pdev->dev.platform_data;
> +
> + sim_t *sim = kzalloc(sizeof(sim_t), GFP_KERNEL);
> +
> + if (sim == 0) {
> + ret = -ENOMEM;
> + printk(KERN_ERR "Can't get the MEMORY\n");
> + return ret;
> + };
> +
> + BUG_ON(pdev == NULL);
> +
> + sim->plat_data = sim_plat;
> + sim->clk_flag = 0;
> + sim->sim_number = sim->plat_data->sim_number;
> +
> + printk(KERN_INFO "Trying initialize port %d...\n", sim->sim_number);
> +
> + sim->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!sim->res) {
> + ret = -ENOMEM;
> + printk(KERN_ERR "Can't get the MEMORY\n");
Use dev_err here. Also it is useful to print the error value here.
> + goto out;
> + }
> +
> + // request the sim clk and sim_serial_clk
> + sim_debug("CLK rate:%d\n", sim->plat_data->clk_rate);
> + sim->clk = clk_get_sys(sim->plat_data->clock_sim, NULL);
> + if (IS_ERR(sim->clk)) {
> + ret = PTR_ERR(sim->clk);
> + printk(KERN_ERR "Get CLK ERROR !\n");
> + goto out;
> + }
> + sim_debug("sim clock:%lu\n", clk_get_rate(sim->clk));
> +
> + if (!request_mem_region(sim->res->start,
> + sim->res->end -
> + sim->res->start + 1, pdev->name)) {
> + printk(KERN_ERR "request_mem_region failed\n");
> + ret = -ENOMEM;
> + goto out1;
> + }
> +
> + sim->ioaddr = (void *)ioremap(sim->res->start, sim->res->end -
> + sim->res->start + 1);
ioremap can fail.
> +
> + platform_set_drvdata(pdev, sim);
> + sim_dev.minor = MISC_DYNAMIC_MINOR;
> + if (sim->sim_number == 0)
> + sim_dev.name = SIM1_DEV_NAME;
> + else if (sim->sim_number == 1)
> + sim_dev.name = SIM2_DEV_NAME;
> + sim_dev.fops = &sim_fops,
> + sim_dev.parent = &(pdev->dev);
> +
> + misc_register(&sim_dev);
I suppose this function can fail?
> +
> + return ret;
> +
> +out1:
> + clk_put(sim->clk);
> +out:
> + kfree(sim);
> + return ret;
> +}
> +
> +static int sim_remove(struct platform_device *pdev)
> +{
> + sim_t *sim = platform_get_drvdata(pdev);
> +
> + clk_put(sim->clk);
> +
> + if (sim->ipb_irq)
> + free_irq(sim->ipb_irq, sim);
> + if (sim->dat_irq)
> + free_irq(sim->dat_irq, sim);
I see no request_irq anywhere in this patch.
> +
> + iounmap(sim->ioaddr);
> +
> + kfree(sim);
> + release_mem_region(sim->res->start,
> + sim->res->end - sim->res->start + 1);
> +
> +
> + misc_deregister(&sim_dev);
> + return 0;
> +}
> +
> +static struct platform_driver sim_driver = {
> + .driver = {
> + .name = DRIVER_NAME,
> + .owner = THIS_MODULE,
> + },
> + .probe = sim_probe,
> + .remove = sim_remove,
> + .suspend = NULL,
> + .resume = NULL,
> +};
> +
> +static int __init sim_drv_init(void)
> +{
> + printk(KERN_INFO "IMX : SIM driver\n");
> +
> + return platform_driver_register(&sim_driver);
> +}
> +
> +static void __exit sim_drv_exit(void)
> +{
> + platform_driver_unregister(&sim_driver);
> +}
> +
> +module_init(sim_drv_init);
> +module_exit(sim_drv_exit);
> +
> +MODULE_AUTHOR("FQ Ingenieria Electronica S.A.");
> +MODULE_DESCRIPTION("MXC SIM Driver");
> +MODULE_LICENSE("GPL");
> --
> 1.5.4.3
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v5] davinci: Add additional JTAG code for AM-1808 and OMAP-L138 Rev 2.0 SoCs From: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
From: Michael Williamson @ 2011-01-03 13:03 UTC (permalink / raw)
To: linux-arm-kernel
The JTAG variant code for Rev-2.0 silicon of the OMAP-L138 has changed.
In addition, the variant code for the AM-1808 SoC appears to match
the Rev-2.0 code for the OMAP-L138. Add an additional entry to support
these chips.
This patch is originally from a patch on the arago project, here:
http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=6157618435e313a444cdf059702bd34036a6e2b7
Further information related to the need for this patch can be located at
http://e2e.ti.com/support/embedded/f/354/p/67290/248486.aspx
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-November/021224.html
This patch was tested using an AM-1808 SoC on a MityARM-1808 SoM card. It
was also tested using a Rev 1.0 silicon OMAP-L138 on a MityDSP-L138F card.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Tested-by: Michael Williamson <michael.williamson@criticallink.com>
Reported-by: Nicolas Luna <luna.id@gmail.com>
---
Built against linux-davinci tree.
Changes since v4.
- removed am18x code from 0 variant per Sekhar's request.
arch/arm/mach-davinci/da850.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 78b5ae2..1550ac3 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -764,6 +764,13 @@ static struct davinci_id da850_ids[] = {
.cpu_id = DAVINCI_CPU_ID_DA850,
.name = "da850/omap-l138",
},
+ {
+ .variant = 0x1,
+ .part_no = 0xb7d1,
+ .manufacturer = 0x017, /* 0x02f >> 1 */
+ .cpu_id = DAVINCI_CPU_ID_DA850,
+ .name = "da850/omap-l138/am18x",
+ },
};
static struct davinci_timer_instance da850_timer_instance[4] = {
--
1.7.0.4
^ permalink raw reply related
* [PATCH v7 5/7] omap3: nand: configurable fifo threshold to gain the throughput
From: Nori, Sekhar @ 2011-01-03 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1293629546-18831-6-git-send-email-s-ghorai@ti.com>
Hi Sukumar,
On Wed, Dec 29, 2010 at 19:02:24, Ghorai, Sukumar wrote:
> Configure the FIFO THREASHOLD value different for read and write to keep busy
> both filling and to drain out of FIFO at reading and writing.
>
> Signed-off-by: Vimal Singh <vimalsingh@ti.com>
> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
> ---
> arch/arm/mach-omap2/gpmc.c | 11 +++++++----
> arch/arm/plat-omap/include/plat/gpmc.h | 5 ++++-
> drivers/mtd/nand/omap2.c | 22 ++++++++++++++--------
> 3 files changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index cfaf357..b26b1a5 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -59,7 +59,6 @@
> #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
> #define GPMC_SECTION_SHIFT 28 /* 128 MB */
>
> -#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
> #define CS_NUM_SHIFT 24
> #define ENABLE_PREFETCH (0x1 << 7)
> #define DMA_MPU_MODE 2
> @@ -595,15 +594,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
> /**
> * gpmc_prefetch_enable - configures and starts prefetch transfer
> * @cs: cs (chip select) number
> + * @fifo_th: fifo threshold to be used for read/ write
> * @dma_mode: dma mode enable (1) or disable (0)
> * @u32_count: number of bytes to be transferred
> * @is_write: prefetch read(0) or write post(1) mode
> */
> -int gpmc_prefetch_enable(int cs, int dma_mode,
> +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> unsigned int u32_count, int is_write)
> {
>
> - if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
> + printk(KERN_ERR "PREFETCH Fifo Threshold is not supported\n");
> + return -1;
Please consider using pr_err(). Also, adding function/device name
prefix helps locate which module caused the error from logs.
Also, is "operation not permitted" the best error we can give back
here?
> + } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> /* Set the amount of bytes to be prefetched */
> gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
>
> @@ -611,7 +614,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
> * enable the engine. Set which cs is has requested for.
> */
> gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
> - PREFETCH_FIFOTHRESHOLD |
> + PREFETCH_FIFOTHRESHOLD(fifo_th) |
> ENABLE_PREFETCH |
> (dma_mode << DMA_MPU_MODE) |
> (0x1 & is_write)));
> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
> index 054e704..fb82335 100644
> --- a/arch/arm/plat-omap/include/plat/gpmc.h
> +++ b/arch/arm/plat-omap/include/plat/gpmc.h
> @@ -83,6 +83,9 @@
> #define GPMC_IRQ_FIFOEVENTENABLE 0x01
> #define GPMC_IRQ_COUNT_EVENT 0x02
>
> +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
> +#define PREFETCH_FIFOTHRESHOLD(val) (val << 8)
Parenthesize val please.
> +
> /*
> * Note that all values in this struct are in nanoseconds, while
> * the register values are in gpmc_fck cycles.
> @@ -133,7 +136,7 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
> extern void gpmc_cs_free(int cs);
> extern int gpmc_cs_set_reserved(int cs, int reserved);
> extern int gpmc_cs_reserved(int cs);
> -extern int gpmc_prefetch_enable(int cs, int dma_mode,
> +extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> unsigned int u32_count, int is_write);
> extern int gpmc_prefetch_reset(int cs);
> extern void omap3_gpmc_save_context(void);
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index 007862e..384d89b 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -243,7 +243,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
> }
>
> /* configure and start prefetch transfer */
> - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
> + ret = gpmc_prefetch_enable(info->gpmc_cs,
> + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
> if (ret) {
> /* PFPW engine is busy, use cpu copy method */
> if (info->nand.options & NAND_BUSWIDTH_16)
> @@ -287,7 +288,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
> }
>
> /* configure and start prefetch transfer */
> - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
> + ret = gpmc_prefetch_enable(info->gpmc_cs,
> + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
> if (ret) {
> /* PFPW engine is busy, use cpu copy method */
> if (info->nand.options & NAND_BUSWIDTH_16)
> @@ -340,8 +342,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
> dma_addr_t dma_addr;
> int ret;
>
> - /* The fifo depth is 64 bytes. We have a sync at each frame and frame
> - * length is 64 bytes.
> + /* The fifo depth is 64 bytes max.
> + * But configure the FIFO-threahold to 32 to get a sync at each frame
> + * and frame length is 32 bytes.
> */
> int buf_len = len >> 6;
>
> @@ -382,7 +385,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
> OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
> }
> /* configure and start prefetch transfer */
> - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
> + ret = gpmc_prefetch_enable(info->gpmc_cs,
> + PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
> if (ret)
> /* PFPW engine is busy, use cpu copy methode */
> goto out_copy;
> @@ -518,7 +522,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
> init_completion(&info->comp);
>
> /* configure and start prefetch transfer */
> - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
> + ret = gpmc_prefetch_enable(info->gpmc_cs,
> + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
> if (ret)
> /* PFPW engine is busy, use cpu copy methode */
> goto out_copy;
> @@ -563,8 +568,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
> info->buf = (u_char *) buf;
> init_completion(&info->comp);
>
> - /* configure and start prefetch transfer */
> - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
> + /* configure and start prefetch transfer : size=24 */
> + ret = gpmc_prefetch_enable(info->gpmc_cs,
> + (PREFETCH_FIFOTHRESHOLD_MAX*3)/8, 0x0, len, 0x1);
Spaces around binary '*'
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v7 4/7] omap3: nand: prefetch in irq mode support
From: Nori, Sekhar @ 2011-01-03 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1293629546-18831-5-git-send-email-s-ghorai@ti.com>
Hi Sukumar,
On Wed, Dec 29, 2010 at 19:02:23, Ghorai, Sukumar wrote:
> This patch enable prefetch-irq mode for nand transfer(read, write)
>
> Signed-off-by: Vimal Singh <vimalsingh@ti.com>
> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
> ---
> arch/arm/mach-omap2/board-flash.c | 2 +
> arch/arm/plat-omap/include/plat/nand.h | 4 +-
> drivers/mtd/nand/omap2.c | 169 ++++++++++++++++++++++++++++++++
> 3 files changed, 174 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
> index f6b7253..1964509 100644
> --- a/arch/arm/mach-omap2/board-flash.c
> +++ b/arch/arm/mach-omap2/board-flash.c
> @@ -16,6 +16,7 @@
> #include <linux/platform_device.h>
> #include <linux/mtd/physmap.h>
> #include <linux/io.h>
> +#include <plat/irqs.h>
>
> #include <plat/gpmc.h>
> #include <plat/nand.h>
> @@ -147,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
> board_nand_data.nr_parts = nr_parts;
> board_nand_data.devsize = nand_type;
>
> + board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
> gpmc_nand_init(&board_nand_data);
> }
> #else
> diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
> index 78c0bdb..ae5e053 100644
> --- a/arch/arm/plat-omap/include/plat/nand.h
> +++ b/arch/arm/plat-omap/include/plat/nand.h
> @@ -13,7 +13,8 @@
> enum nand_io {
> NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
> NAND_OMAP_POLLED, /* polled mode, without prefetch */
> - NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */
> + NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
> + NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
> };
>
> struct omap_nand_platform_data {
> @@ -26,6 +27,7 @@ struct omap_nand_platform_data {
> int (*nand_setup)(void);
> int (*dev_ready)(struct omap_nand_platform_data *);
> int dma_channel;
> + int gpmc_irq;
> enum nand_io xfer_type;
> unsigned long phys_base;
> int devsize;
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index 66b7428..007862e 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -11,6 +11,7 @@
> #include <linux/platform_device.h>
> #include <linux/dma-mapping.h>
> #include <linux/delay.h>
> +#include <linux/interrupt.h>
> #include <linux/jiffies.h>
> #include <linux/sched.h>
> #include <linux/mtd/mtd.h>
> @@ -108,6 +109,13 @@ struct omap_nand_info {
> unsigned long phys_base;
> struct completion comp;
> int dma_ch;
> + int gpmc_irq;
> + enum {
> + OMAP_NAND_IO_READ = 0, /* read */
> + OMAP_NAND_IO_WRITE, /* write */
> + } iomode;
> + u_char *buf;
> + int buf_len;
> };
>
> /**
> @@ -436,6 +444,153 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd,
> omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
> }
>
> +/*
> + * omap_nand_irq - GMPC irq handler
> + * @this_irq: gpmc irq number
> + * @dev: omap_nand_info structure pointer is passed here
> + */
> +static irqreturn_t omap_nand_irq(int this_irq, void *dev)
> +{
> + struct omap_nand_info *info = (struct omap_nand_info *) dev;
> + u32 bytes;
> + u32 irq_stat;
> +
> + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
> + bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
> + bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
> + if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
> + if (irq_stat & 0x2)
> + goto done;
> +
> + if (info->buf_len & (info->buf_len < bytes))
Meant to use logical AND here?
> + bytes = info->buf_len;
> + else if (!info->buf_len)
> + bytes = 0;
> + iowrite32_rep(info->nand.IO_ADDR_W,
> + (u32 *)info->buf, bytes >> 2);
> + info->buf = info->buf + bytes;
> + info->buf_len -= bytes;
> +
> + } else {
> + ioread32_rep(info->nand.IO_ADDR_R,
> + (u32 *)info->buf, bytes >> 2);
> + info->buf = info->buf + bytes;
> +
> + if (irq_stat & 0x2)
> + goto done;
> + }
> + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
> + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
irq_stat update remains unused.
> +
> + return IRQ_HANDLED;
> +
> +done:
> + complete(&info->comp);
> + /* disable irq */
> + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
> +
> + /* clear status */
> + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
> + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/*
> + * omap_read_buf_irq_pref - read data from NAND controller into buffer
> + * @mtd: MTD device structure
> + * @buf: buffer to store date
> + * @len: number of bytes to read
> + */
> +static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
> +{
> + struct omap_nand_info *info = container_of(mtd,
> + struct omap_nand_info, mtd);
> + int ret = 0;
> +
> + if (len <= mtd->oobsize) {
> + omap_read_buf_pref(mtd, buf, len);
> + return;
> + }
> +
> + info->iomode = OMAP_NAND_IO_READ;
> + info->buf = buf;
> + init_completion(&info->comp);
You can use INIT_COMPLETION to reset the completion variable.
Same change can be done in write below.
> +
> + /* configure and start prefetch transfer */
> + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
> + if (ret)
> + /* PFPW engine is busy, use cpu copy methode */
s/methode/method
> + goto out_copy;
> +
> + info->buf_len = len;
> + /* enable irq */
> + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
> + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
> +
> + /* waiting for read to complete */
> + wait_for_completion(&info->comp);
> +
> + /* disable and stop the PFPW engine */
> + gpmc_prefetch_reset(info->gpmc_cs);
> + return;
> +
> +out_copy:
> + if (info->nand.options & NAND_BUSWIDTH_16)
> + omap_read_buf16(mtd, buf, len);
> + else
> + omap_read_buf8(mtd, buf, len);
> +}
> +
> +/*
> + * omap_write_buf_irq_pref - write buffer to NAND controller
> + * @mtd: MTD device structure
> + * @buf: data buffer
> + * @len: number of bytes to write
> + */
> +static void omap_write_buf_irq_pref(struct mtd_info *mtd,
> + const u_char *buf, int len)
> +{
> + struct omap_nand_info *info = container_of(mtd,
> + struct omap_nand_info, mtd);
> + int ret = 0;
> + if (len <= mtd->oobsize) {
> + omap_write_buf_pref(mtd, buf, len);
> + return;
> + }
> +
> + info->iomode = OMAP_NAND_IO_WRITE;
> + info->buf = (u_char *) buf;
> + init_completion(&info->comp);
> +
> + /* configure and start prefetch transfer */
> + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
> + if (ret)
> + /* PFPW engine is busy, use cpu copy methode */
> + goto out_copy;
> +
> + info->buf_len = len;
> + /* enable irq */
> + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
> + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
> +
> + /* waiting for write to complete */
> + wait_for_completion(&info->comp);
> + /* wait for data to flushed-out before reset the prefetch */
> + do {
> + ret = gpmc_read_status(GPMC_PREFETCH_COUNT);
> + } while (ret);
Please have a timeout for this while loop in case hardware does
not become ready. Also, consider using cpu_relax() inside the
tight loop.
> + /* disable and stop the PFPW engine */
> + gpmc_prefetch_reset(info->gpmc_cs);
> + return;
> +
> +out_copy:
> + if (info->nand.options & NAND_BUSWIDTH_16)
> + omap_write_buf16(mtd, buf, len);
> + else
> + omap_write_buf8(mtd, buf, len);
> +}
> +
> /**
> * omap_verify_buf - Verify chip data against buffer
> * @mtd: MTD device structure
> @@ -769,6 +924,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
>
> info->gpmc_cs = pdata->cs;
> info->phys_base = pdata->phys_base;
> + info->gpmc_irq = pdata->gpmc_irq;
>
> info->mtd.priv = &info->nand;
> info->mtd.name = dev_name(&pdev->dev);
> @@ -846,6 +1002,19 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
> }
> break;
>
> + case NAND_OMAP_PREFETCH_IRQ:
> + err = request_irq(info->gpmc_irq,
> + omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
I was expecting to see a free_irq() in the remove.
Thanks,
Sekhar
> + if (err) {
> + dev_err(&pdev->dev, "requesting irq(%d) error:%d",
> + info->gpmc_irq, err);
> + goto out_release_mem_region;
> + } else {
> + info->nand.read_buf = omap_read_buf_irq_pref;
> + info->nand.write_buf = omap_write_buf_irq_pref;
> + }
> + break;
> +
> default:
> dev_err(&pdev->dev,
> "xfer_type(%d) not supported!\n", pdata->xfer_type);
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [patch 2/5] ulpi: handle ULPI_OTG_CTRL_CHRGVBUS
From: Arnaud Patard (Rtp) @ 2011-01-03 11:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D14B69D.4030506@compulab.co.il>
Igor Grinberg <grinberg@compulab.co.il> writes:
Hi,
> On 12/23/10 22:11, Arnaud Patard (Rtp) wrote:
>> Igor Grinberg <grinberg@compulab.co.il> writes:
>>
>>> Hi Arnaud,
>>>
>>> On 12/20/10 17:48, Arnaud Patard (Rtp) wrote:
>>>> Current code doesn't handle setting CHRGVBUS when enabling vbus.
>>>> Add support for it
>>>>
>>>>
>>>>
>>>> Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
>>>> Index: tst-usb/drivers/usb/otg/ulpi.c
>>>> ===================================================================
>>>> --- tst-usb.orig/drivers/usb/otg/ulpi.c 2010-12-20 15:38:41.000000000 +0100
>>>> +++ tst-usb/drivers/usb/otg/ulpi.c 2010-12-20 15:38:57.000000000 +0100
>>>> @@ -234,7 +234,8 @@
>>>> {
>>>> unsigned int flags = otg_io_read(otg, ULPI_OTG_CTRL);
>>>>
>>>> - flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
>>>> + flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT |
>>>> + ULPI_OTG_CTRL_CHRGVBUS);
>>>>
>>>> if (on) {
>>>> if (otg->flags & ULPI_OTG_DRVVBUS)
>>>> @@ -242,6 +243,9 @@
>>>>
>>>> if (otg->flags & ULPI_OTG_DRVVBUS_EXT)
>>>> flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>>>> +
>>>> + if (otg->flags & ULPI_OTG_CHRGVBUS)
>>>> + flags |= ULPI_OTG_CTRL_CHRGVBUS;
>>>> }
>>>>
>>>> return otg_io_write(otg, flags, ULPI_OTG_CTRL);
>>> I think this is a wrong place to set the ChrgVbus bit.
>>> As for ULPI spec. 1.1:
>>> "3.8.7.1 Session Request Protocol (SRP)
>>> ULPI provides full SRP support. The Link uses the ChrgVbus and DischrgVbus bits
>>> in the OTG Control register to begin and end a session."
>>>
>>> So it is used for SRP.
>>> May be it is better to implement
>>> int (*start_srp)(struct otg_transceiver *otg);
>>> method for setting this bit?
>>>
>> I was not sure on where to put this so I took the same approach as the
>> fsl bsp which was to set it in this function and to call this function
>> _after_ usb_add_hcd() [ see my previous patch ]. Indeed, it fixed my
>> issue so I believe it not so bad given that there has already been some
>> troubles on the ehci-mxc init.
>
> Well, the problem is that this is supposed to be a generic driver and it should
> somehow follow the ULPI spec.
> This patch makes it more like mxc specific.
>
> As far as I understand, Session Request Protocol (SRP) allows a B-device (Peripheral)
> to nudge an A-device (Host) to turn on the USB's Vbus.
> This patch enables SRP along with Vbus, which seems incorrect completely.
> ulpi_set_vbus() should set the Vbus (as its name says) and that's it.
so, if I add a srp hook as you're suggesting, which part of the driver
should call it ?
>
> Have you tried without this patch or have you just applied it along with other
> patches from the fsl bsp?
I already tried without this patch and without it, things are not
working on my systems.
>
> Also, if this specific patch (2/5) makes your USB (Host as I understand) work,
> it makes me think that there could be some problem with your Vbus supply.
> Have you checked that?
I don't have any schematics and I've access only to the source code of
the kernel running on the efika nettop and smartbook [1]. I've not seen
anything (even remotely) related to vbus supply except in the ulpi code
and from what I've heard, it's unlikely that there's something to
control it on theses systems. Of course, I'll be happy to be proven
wrong. Without usb theses systems are useless so anything the can reduce
the number of patches needed to get the systems working with mainline is
welcome.
Arnaud
[1] http://gitorious.org/efikamx/linux-kernel/
^ permalink raw reply
* [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
From: Russell King - ARM Linux @ 2011-01-03 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTiktQbR5cm6qKzrhCBEMqmxOq4WhryoZnQ-kge0g@mail.gmail.com>
On Sun, Jan 02, 2011 at 09:33:34PM +0100, Linus Walleij wrote:
> As for the in-tree PL08x driver I'd say it's doing pretty well for
> memcpy() so we could add platform data for that on supported
> platforms, then for device transfers we need more elaborative
> work.
It has the issue that it's not unmapping the buffers after the memcpy()
operation has completed, so on ARMv6+ we have the possibility for
speculative prefetches to corrupt the destination buffer.
Neither are a number of the other DMA engine drivers. This is why I'd
like to see some common infrastructure in the DMA engine core for saying
"this tx descriptor is now complete" so that DMA engine driver authors
don't have to even think about whether they should be unmapping buffers.
I'd also like to see DMA_COMPL_SKIP_*_UNMAP always set by prep_slave_sg()
in tx->flags so we don't have to end up with "is this a slave operation"
tests in the completion handler.
^ permalink raw reply
* [PATCH 6/7] ARM: PL011: Add support for transmit DMA
From: Rabin Vincent @ 2011-01-03 11:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1PZhMW-0007pl-6b@rmk-PC.arm.linux.org.uk>
On Mon, Jan 3, 2011 at 15:40, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> + ? ? ? if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
> + ? ? ? ? ? ? ? uap->dmatx.queued = false;
> + ? ? ? ? ? ? ? dev_dbg(uap->port.dev, "unable to map TX DMA\n");
> + ? ? ? ? ? ? ? return -EBUSY;
> + ? ? ? }
> +
> + ? ? ? desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> + ? ? ? if (!desc) {
> + ? ? ? ? ? ? ? uap->dmatx.queued = false;
Doesn't dma_unmap_sg need to be called here?
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* If DMA cannot be used right now, we complete this
> + ? ? ? ? ? ? ? ?* transaction via IRQ and let the TTY layer retry.
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? dev_dbg(uap->port.dev, "TX DMA busy\n");
> + ? ? ? ? ? ? ? return -EBUSY;
> + ? ? ? }
^ permalink raw reply
* [PATCH 0/7] PL011 DMA support
From: Russell King - ARM Linux @ 2011-01-03 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110103100753.GB26785@n2100.arm.linux.org.uk>
On Mon, Jan 03, 2011 at 10:07:54AM +0000, Russell King - ARM Linux wrote:
> This is another posting of the PL011 DMA patch set, with a new patch
> to include the PL011 revision in the boot time messages, and fixups
> to the DMA patch as a result of discussions with Dan.
>
> Acks for patches 1 and 6 would be appreciated.
I'd like to have an ack from Linus for patches 1 and 6, and an ack from
Dan for just patch 6. Once I have those acks, I think PL011 TX DMA
support is good to go for this merge window.
^ permalink raw reply
* [PATCH] ARM: S3C64xx: Clear DMA_HALT upon start
From: Kukjin Kim @ 2011-01-03 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294019615-18532-1-git-send-email-jassisinghbrar@gmail.com>
Jassi Brar wrote:
>
> From: Jassi Brar <jassi.brar@samsung.com>
>
> The stop function sets the DMA_HALT bit, which prevents
> the DMA transfer to resume after stop, for example during
> audio PAUSE/PLAY cycle. Clear the HALT bit during start.
>
> Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
> ---
> arch/arm/mach-s3c64xx/dma.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
> index e7d03ab..d9aa072 100644
> --- a/arch/arm/mach-s3c64xx/dma.c
> +++ b/arch/arm/mach-s3c64xx/dma.c
> @@ -212,6 +212,7 @@ static int s3c64xx_dma_start(struct s3c2410_dma_chan
> *chan)
>
> config = readl(chan->regs + PL080S_CH_CONFIG);
> config |= PL080_CONFIG_ENABLE;
> + config &= ~PL080_CONFIG_HALT;
>
> pr_debug("%s: writing config %08x\n", __func__, config);
> writel(config, chan->regs + PL080S_CH_CONFIG);
> --
Ok...will apply.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH] sa1100: Update platform device registration
From: Russell King - ARM Linux @ 2011-01-03 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1293474105-14300-1-git-send-email-jochen@scram.de>
On Mon, Dec 27, 2010 at 07:21:45PM +0100, Jochen Friedrich wrote:
> Replace some magic numbers with constants and add interrupt definitions.
Please send to the patch system, thanks.
^ permalink raw reply
* [PATCH 2.6.37 RESEND] sa1100: Fix platform device registration
From: Russell King - ARM Linux @ 2011-01-03 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1293472170-14130-1-git-send-email-jochen@scram.de>
On Mon, Dec 27, 2010 at 06:49:30PM +0100, Jochen Friedrich wrote:
> Since commit 7a5b4e16c880f8350d255dc188f81622905618c1, simpad devices don't
> boot anymore, since platform devices are registered too early. Fix by moving
> the registration from map_io to arch_initcall as done on other sa1100 boards.
Please send to the patch system, thanks.
^ permalink raw reply
* [RFC] Fixing CPU Hotplug for RealView Platforms
From: Russell King - ARM Linux @ 2011-01-03 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinMobeQBz_ruGAeOSoTWP_9-0Aw4-=8Sk3JxEjX@mail.gmail.com>
On Mon, Dec 20, 2010 at 09:16:15AM +0100, Vincent Guittot wrote:
> I'm also interested in hotplug latency measurement and have done some
> on my CA9 platform u8500. I have the same kind of result for plugging
> a secondary cpu:
> total duration = 295ms
> 166 us for the low level cpu wake up
> 228ms between the return from platform_cpu_die and the cpu becomes online
>
> I have added some trace events for doing these measurements and I'd
> like to add some generic traces point in the cpu hotplug code like we
> already have in power management code (cpuidle, suspend, cpufreq ...)
> These traces could be used with power events for studying the impact
> of cpu hotplug in the complete power management scheme.
Note that if you pass lpj=<number> to the kernel, you'll bypass the
calibration and have a faster response to CPU onlining.
^ permalink raw reply
* [PATCH] ARM: mxs: Change duart device to use amba-pl011
From: Russell King - ARM Linux @ 2011-01-03 10:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20101227114938.GA13154@freescale.com>
On Mon, Dec 27, 2010 at 07:49:40PM +0800, Shawn Guo wrote:
> I did not see this problem. It's true that the clock is turned off
> in amba_device_register. But later, the clock will be turned on
> again by amba_probe -> amba_get_enable_pclk very soon.
>
> But we should add something like below in mx28_clocks_init to reflect
> the clock status and get usecount updated.
>
> clk_enable(&uart_clk)
>
> I ran into similar problem with fec driver, and would cover that in
> fec patch set.
This sounds like entirely the wrong approach. Please take some time to
understand that there are different clocks which do different things.
The PCLK is the name ARM Ltd give to the APB bus clock. This we name
apb_pclk, and we expect platforms to provide it where possible. This
name will be looked up for every primecell device on the system.
If you don't provide an apb_pclk, it will find the device specific
function clock. This in itself is no bad thing, unless you use the
device outside of the AMBA driver (iow, before probe or after remove)
and helps identify when you've forgotten to provide an apb_pclk.
^ permalink raw reply
* [PATCH] ARM: mxs: Change duart device to use amba-pl011
From: Russell King - ARM Linux @ 2011-01-03 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20101222202542.GT14221@pengutronix.de>
On Wed, Dec 22, 2010 at 09:25:42PM +0100, Uwe Kleine-K?nig wrote:
> Hello Shawn,
>
> On Tue, Dec 21, 2010 at 09:12:10PM +0800, Shawn Guo wrote:
> > The mxs duart is actually an amba-pl011 device. This commit changes
> > the duart device code to dynamically allocate amba-pl011 device,
> > so that drivers/serial/amba-pl011.c can be used on mxs.
> I have problems using this. The problem I found up to now is that
> during probe of the device (triggered by mxs_add_duart ->
> amba_device_register -> amba_put_disable_pclk) the uart clock is
> disabled.
Which uart clock is disabled? The PCLK or the UARTCLK (names as defined
in the ARM PL011 TRM).
If the pclk code is disabling the UARTCLK, then add a dummy apb_pclk to
your clock lookups, which is what everyone else who can't control the
APB PCLK does.
^ permalink raw reply
* [PATCH 02/04] ARM i.MX25 Add SIM driver
From: Russell King - ARM Linux @ 2011-01-03 10:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20736.212.121.242.58.1294045639.squirrel@mail.fqingenieria.es>
On Mon, Jan 03, 2011 at 10:07:19AM +0100, FQ | Iban Cerro wrote:
> arch/arm/plat-mxc/Kconfig | 7 +
> arch/arm/plat-mxc/Makefile | 1 +
> arch/arm/plat-mxc/include/mach/mxc_sim.h | 319 +++++++++++
> arch/arm/plat-mxc/sim.c | 874
> ++++++++++++++++++++++++++++++
Please find somewhere under drivers/ to put... drivers. Not in arch/
thanks.
^ permalink raw reply
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