* [PATCH RESEND v6 2/4] TI816X: Update common OMAP machine specific sources
From: Hemant Pedanekar @ 2011-02-14 15:03 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the common machine specific source files with support for
TI816X.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/clock3xxx_data.c | 5 +++-
arch/arm/mach-omap2/common.c | 21 +++++++++++++++
arch/arm/mach-omap2/control.h | 6 ++++
arch/arm/mach-omap2/id.c | 33 ++++++++++++++++++++++-
arch/arm/mach-omap2/include/mach/entry-macro.S | 13 +++++++++
arch/arm/mach-omap2/io.c | 22 +++++++++++++++-
arch/arm/mach-omap2/irq.c | 5 +++-
arch/arm/mach-omap2/serial.c | 8 +++---
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/io.h | 8 ++++++
arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++++++++++
arch/arm/plat-omap/io.c | 5 +++-
12 files changed, 144 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1..f14d986 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
+ } else if (cpu_is_ti816x()) {
+ cpu_mask = RATE_IN_TI816X;
+ cpu_clkflg = CK_TI816X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void)
/*
* Lock DPLL5 and put it in autoidle.
*/
- if (omap_rev() >= OMAP3430_REV_ES2_0)
+ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index d5eaee3..48de451 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -108,6 +108,27 @@ void __init omap3_map_io(void)
omap2_set_globals_3xxx();
omap34xx_map_common_io();
}
+
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI816X DEVICE ID register is at offset 0x600 from control base).
+ */
+#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
+ TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals ti816x_globals = {
+ .class = OMAP343X_CLASS,
+ .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+ .ctrl = TI816X_CTRL_BASE,
+ .prm = TI816X_PRCM_BASE,
+ .cm = TI816X_PRCM_BASE,
+};
+
+void __init omap2_set_globals_ti816x(void)
+{
+ __omap2_set_globals(&ti816x_globals);
+}
#endif
#if defined(CONFIG_ARCH_OMAP4)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f0629ae..c2804c1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,6 +52,9 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
+/* TI816X spefic control submodules */
+#define TI816X_CONTROL_DEVCONF 0x600
+
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
@@ -241,6 +244,9 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
+/* TI816X CONTROL_DEVCONF register offsets */
+#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
+
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5f9086c..5c25f1b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -191,12 +191,19 @@ static void __init omap3_check_features(void)
if (!cpu_is_omap3505() && !cpu_is_omap3517())
omap3_features |= OMAP3_HAS_IO_WAKEUP;
+ omap3_features |= OMAP3_HAS_SDRC;
+
/*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
}
+static void __init ti816x_check_features(void)
+{
+ omap3_features = OMAP3_HAS_NEON;
+}
+
static void __init omap3_check_revision(void)
{
u32 cpuid, idcode;
@@ -287,6 +294,20 @@ static void __init omap3_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
}
break;
+ case 0xb81e:
+ omap_chip.oc = CHIP_IS_TI816X;
+
+ switch (rev) {
+ case 0:
+ omap_revision = TI8168_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = TI8168_REV_ES1_1;
+ break;
+ default:
+ omap_revision = TI8168_REV_ES1_1;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
@@ -372,6 +393,8 @@ static void __init omap3_cpuinfo(void)
/* Already set in omap3_check_revision() */
strcpy(cpu_name, "AM3505");
}
+ } else if (cpu_is_ti816x()) {
+ strcpy(cpu_name, "TI816X");
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
@@ -386,7 +409,7 @@ static void __init omap3_cpuinfo(void)
strcpy(cpu_name, "OMAP3503");
}
- if (cpu_is_omap3630()) {
+ if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
@@ -462,7 +485,13 @@ void __init omap2_check_revision(void)
omap24xx_check_revision();
} else if (cpu_is_omap34xx()) {
omap3_check_revision();
- omap3_check_features();
+
+ /* TI816X doesn't have feature register */
+ if (!cpu_is_ti816x())
+ omap3_check_features();
+ else
+ ti816x_check_features();
+
omap3_cpuinfo();
return;
} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 81985a6..a48690b 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -61,6 +61,14 @@
bne 9998f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
+ bne 9998f
+
+ /*
+ * ti816x has additional IRQ pending register. Checking this
+ * register on omap2 & omap3 has no effect (read as 0).
+ */
+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+ cmp \irqnr, #0x0
9998:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@@ -133,6 +141,11 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
+#ifdef CONFIG_SOC_OMAPTI816X
+ bne 9999f
+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+ cmp \irqnr, #0x0
+#endif
9999:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 11decd8..87b13ab 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
#endif
};
#endif
+
+#ifdef CONFIG_SOC_OMAPTI816X
+static struct map_desc omapti816x_io_desc[] __initdata = {
+ {
+ .virtual = L4_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_34XX_PHYS),
+ .length = L4_34XX_SIZE,
+ .type = MT_DEVICE
+ },
+};
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
@@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_SOC_OMAPTI816X
+void __init omapti816x_map_common_io(void)
+{
+ iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+ _omap2_map_common_io();
+}
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
@@ -402,7 +422,7 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
omap_hwmod_late_init();
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ if (omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index d151aac..bc524b9 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -108,7 +108,7 @@ static void omap_mask_irq(struct irq_data *d)
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
int spurious = 0;
/*
@@ -203,6 +203,9 @@ void __init omap_init_irq(void)
BUG_ON(!base);
+ if (cpu_is_ti816x())
+ bank->nr_irqs = 128;
+
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 32e91a9..36a2828 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
@@ -759,13 +759,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
p->private_data = uart;
/*
- * omap44xx: Never read empty UART fifo
+ * omap44xx, ti816x: Never read empty UART fifo
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
- if (cpu_is_omap44xx())
+ if (cpu_is_omap44xx() || cpu_is_ti816x())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -847,7 +847,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
- if (cpu_is_omap34xx())
+ if (cpu_is_omap34xx() && !cpu_is_ti816x())
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26ad..e87efe1 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
+#include <plat/ti816x.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 478c5d9..d72ec85 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_SOC_OMAPTI816X
+extern void omapti816x_map_common_io(void);
+#else
+static inline void omapti816x_map_common_io(void)
+{
+}
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
extern void omap44xx_map_common_io(void);
#else
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 0000000..50510f5
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI816X modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI816X_H
+
+#define L4_SLOW_TI816X_BASE 0x48000000
+
+#define TI816X_SCM_BASE 0x48140000
+#define TI816X_CTRL_BASE TI816X_SCM_BASE
+#define TI816X_PRCM_BASE 0x48180000
+
+#define TI816X_ARM_INTC_BASE 0x48200000
+
+#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1295fa..f1ecfa9 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP3
- if (cpu_is_omap34xx()) {
+ if (cpu_is_ti816x()) {
+ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+ return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+ } else if (cpu_is_omap34xx()) {
if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
--
1.7.3.5
^ permalink raw reply related
* [PATCH RESEND v6 3/4] TI816X: Create board support and enable build for TI816X EVM
From: Hemant Pedanekar @ 2011-02-14 15:03 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds minimal support and build configuration for TI816X EVM.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/Kconfig | 5 +++
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-ti8168evm.c | 57 +++++++++++++++++++++++++++++++++
3 files changed, 63 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6a4cfc2..9b4e78f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -299,6 +299,11 @@ config MACH_OMAP_3630SDP
default y
select OMAP_PACKAGE_CBP
+config MACH_TI8168EVM
+ bool "TI8168 Evaluation Module"
+ depends on SOC_OMAPTI816X
+ default y
+
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 742ca67..ec24999 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -224,6 +224,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
hsmmc.o
+obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
# Platform specific device init code
usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
obj-y += $(usbfs-m) $(usbfs-y)
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
new file mode 100644
index 0000000..6282cc4
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -0,0 +1,57 @@
+/*
+ * Code for TI8168 EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+
+static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+};
+
+static void __init ti8168_evm_init_irq(void)
+{
+ omap_board_config = ti8168_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ omap_init_irq();
+}
+
+static void __init ti8168_evm_init(void)
+{
+ omap_serial_init();
+}
+
+static void __init ti8168_evm_map_io(void)
+{
+ omap2_set_globals_ti816x();
+ omapti816x_map_common_io();
+}
+
+MACHINE_START(TI8168EVM, "ti8168evm")
+ /* Maintainer: Texas Instruments */
+ .boot_params = 0x80000100,
+ .map_io = ti8168_evm_map_io,
+ .init_irq = ti8168_evm_init_irq,
+ .timer = &omap_timer,
+ .init_machine = ti8168_evm_init,
+MACHINE_END
--
1.7.3.5
^ permalink raw reply related
* [PATCH RESEND v6 4/4] TI816X: Add low level debug support
From: Hemant Pedanekar @ 2011-02-14 15:04 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for low level debugging on TI816X boards. Currently the
support for UART3 console on TI816X EVM is added.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++++++++++
arch/arm/plat-omap/include/plat/serial.h | 8 ++++++++
arch/arm/plat-omap/include/plat/uncompress.h | 7 +++++++
3 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 6a4d413..e1b0f17 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -69,6 +69,12 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
+ cmp \rp, #TI816XUART1 @ ti816x UART offsets different
+ beq 81f @ configure UART1
+ cmp \rp, #TI816XUART2 @ ti816x UART offsets different
+ beq 82f @ configure UART2
+ cmp \rp, #TI816XUART3 @ ti816x UART offsets different
+ beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@@ -91,6 +97,12 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
+81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
+ b 98f
+82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
+ b 98f
+83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
+ b 98f
95: ldr \rp, =ZOOM_UART_BASE
mrc p15, 0, \rv, c1, c0
tst \rv, #1 @ MMU enabled?
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index cec5d56..4102bf4 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,6 +51,11 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
+/* TI816X serial ports */
+#define TI816X_UART1_BASE 0x48020000
+#define TI816X_UART2_BASE 0x48022000
+#define TI816X_UART3_BASE 0x48024000
+
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@@ -81,6 +86,9 @@
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
+#define TI816XUART1 81
+#define TI816XUART2 82
+#define TI816XUART3 83
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ad98b85..30b891c 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,6 +93,10 @@ static inline void flush(void)
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+#define DEBUG_LL_TI816X(p, mach) \
+ _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ TI816XUART##p)
+
static inline void __arch_decomp_setup(unsigned long arch_id)
{
int port = 0;
@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_ZOOM(omap_zoom2);
DEBUG_LL_ZOOM(omap_zoom3);
+ /* TI8168 base boards using UART3 */
+ DEBUG_LL_TI816X(3, ti8168evm);
+
} while (0);
}
--
1.7.3.5
^ permalink raw reply related
* Machine ID question
From: Alexander Stein @ 2011-02-14 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110210082915.GV27982@pengutronix.de>
On Thursday 10 February 2011, 09:29:15 Uwe Kleine-K?nig wrote:
> On Wed, Feb 09, 2011 at 02:23:07PM -0700, John Linn wrote:
> > I used the form to create a new machine ID for the new Xilinx platform
> > in anticipation of
> > the code making it into the mainline sometime in the future.
> >
> > The proposed patches are using ARCH_XILINX in the Kconfig.
>
> You should use MACH_XILINX in the patches. There are some ARCH_... in
> the machine db, but I think nowadays you cannot (and should not) create
> them there.
Uhm, the last entry in the db was created today (14th Feb). Is there a reason
why there no new entries should be created?
Alexander
^ permalink raw reply
* [git pull] Revert arm/dt documentation change that shouldn't have been merged yet
From: Grant Likely @ 2011-02-14 15:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
I included a patch I shouldn't have in my last pull req. This pull
req reverts it. Thanks to Russell for pointing it out to me.
g.
The following changes since commit 795abaf1e4e188c4171e3cd3dbb11a9fcacaf505:
klist: Fix object alignment on 64-bit. (2011-02-13 16:54:24 -0800)
are available in the git repository at:
git://git.secretlab.ca/git/linux-2.6 devicetree/merge
Grant Likely (1):
Revert "dt: add documentation of ARM dt boot interface"
Documentation/arm/Booting | 33 ++----------------
Documentation/devicetree/booting-without-of.txt | 40 -----------------------
2 files changed, 4 insertions(+), 69 deletions(-)
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Will Deacon @ 2011-02-14 15:26 UTC (permalink / raw)
To: linux-arm-kernel
Currently, the gic uses handle_level_irq for handling SPIs (Shared
Peripheral Interrupts), requiring active interrupts to be masked at
the distributor level during IRQ handling.
On a virtualised system, only the CPU interfaces are virtualised in
hardware. Accesses to the distributor must be trapped by the hypervisor,
adding latency to the critical interrupt path in Linux.
This patch modifies the GIC code to use handle_fasteoi_irq for handling
interrupts, which only requires us to signal EOI to the CPU interface
when handling is complete. Cascaded IRQ handling is also updated so that
EOI is signalled after handling.
Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke
cascading interrupts by forgetting to add IRQ masking. This is no longer
an issue because the unmask call is now unnecessary.
Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).
Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
Reposting because I forgot the CCs the first time round...
arch/arm/common/gic.c | 23 +++++++++--------------
1 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 2243772..9def30b 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -71,13 +71,6 @@ static inline unsigned int gic_irq(struct irq_data *d)
/*
* Routines to acknowledge, disable and enable interrupts
*/
-static void gic_ack_irq(struct irq_data *d)
-{
- spin_lock(&irq_controller_lock);
- writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
- spin_unlock(&irq_controller_lock);
-}
-
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (d->irq % 32);
@@ -96,6 +89,11 @@ static void gic_unmask_irq(struct irq_data *d)
spin_unlock(&irq_controller_lock);
}
+static void gic_eoi_irq(struct irq_data *d)
+{
+ writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(d);
@@ -174,9 +172,6 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned int cascade_irq, gic_irq;
unsigned long status;
- /* primary controller ack'ing */
- chip->irq_ack(&desc->irq_data);
-
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
@@ -192,15 +187,15 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(cascade_irq);
out:
- /* primary controller unmasking */
- chip->irq_unmask(&desc->irq_data);
+ /* primary controller EOI */
+ chip->irq_eoi(&desc->irq_data);
}
static struct irq_chip gic_chip = {
.name = "GIC",
- .irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
+ .irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_cpu,
@@ -275,7 +270,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
for (i = irq_start; i < irq_limit; i++) {
set_irq_chip(i, &gic_chip);
set_irq_chip_data(i, gic);
- set_irq_handler(i, handle_level_irq);
+ set_irq_handler(i, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH v4 0/5] ARM: omap[34]: Thumb-2 compatibility fixes
From: Dave Martin @ 2011-02-14 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102140950580.14920@xanadu.home>
On Mon, Feb 14, 2011 at 10:00:23AM -0500, Nicolas Pitre wrote:
> On Mon, 14 Feb 2011, Dave Martin wrote:
>
> > @@ -289,8 +297,20 @@ clean_l2:
> > * - should be faster and will change with kernel
> > * - 'might' have to copy address, load and jump to it
> > */
> > +#ifdef CONFIG_THUMB2_KERNEL
> > + /* kernel is non-interworking : must do this from Thumb */
> > + adr r1, . + 1
> > + bx r1
> > + .thumb
> > +#endif
> > ldr r1, kernel_flush
>
> Didn't you mean this instead:
>
> /* kernel is non-interworking : must do this from Thumb */
> adr r1, 1f + 1
> bx r1
> .thumb
> 1: ldr r1, kernel_flush
> ...
Note that this is intended as an experimental hack, not a real patch
(apologies if I didn't make that clear...)
Well, actually I meant "add r1, pc, #1" ... which means I was too
busy trying to be clever... oops!
That is of course exactly equivalent to your code...
>
> ?
>
> > blx r1
> > +#ifdef CONFIG_THUMB2_KERNEL
> > + .align
> > + bx pc
> > + nop
> > + .arm
>
> Also here, the .align has the potential to introduce a zero halfword in
> the instruction stream before the bx. What about:
>
> adr r3, 1f
> bx r3
> .align
> .arm
> 1: ...
.align inserts a 16-bit nop when misaligned in Thumb in a text section,
and a word-aligned bx pc is a specific architecturally allowed way
to do an inline switch to ARM. The linker uses this trick for PLT
veneers etc.
A nicer fix for doing this sort of call from low-level code which
might be ARM is to convert arch/arm/mm/*-v7.S to use "bx lr" to return.
Generally, we can do this for all arches >= v5, without any
incompatibility. However, since the need for it will be rare and it
will generate patch noise for not much real benefit,
I haven't proposed this.
Updated patch below.
Cheers
---Dave
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index a204c78..6ae8a92 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -32,6 +32,14 @@
#include "sdrc.h"
#include "control.h"
+#undef ARM
+#undef THUMB
+#undef BSYM
+#define ARM(x...) x
+#define THUMB(x...)
+#define BSYM(x) (x)
+ .arm
+
/*
* Registers access definitions
*/
@@ -289,8 +297,20 @@ clean_l2:
* - should be faster and will change with kernel
* - 'might' have to copy address, load and jump to it
*/
- ldr r1, kernel_flush
+#ifdef CONFIG_THUMB2_KERNEL
+ /* kernel is non-interworking : must do this from Thumb */
+ adr r1, 1f + 1
+ bx r1
+ .thumb
+#endif
+1: ldr r1, kernel_flush
blx r1
+#ifdef CONFIG_THUMB2_KERNEL
+ .align
+ bx pc
+ nop
+ .arm
+#endif
omap3_do_wfi:
ldr r4, sdrc_power @ read the SDRC_POWER register
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 829d235..64faab8 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -34,6 +34,14 @@
#include "sdrc.h"
#include "cm2xxx_3xxx.h"
+#undef ARM
+#undef THUMB
+#undef BSYM
+#define ARM(x...) x
+#define THUMB(x...)
+#define BSYM(x) (x)
+ .arm
+
.text
/* r1 parameters */
--
1.7.1
^ permalink raw reply related
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Wolfram Sang @ 2011-02-14 15:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297650746-12841-2-git-send-email-shawn.guo@freescale.com>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index afe8c6f..42a9e21 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -319,6 +319,15 @@ config MMC_MXC
>
> If unsure, say N.
>
> +config MMC_MXS
> + tristate "Freescale MXS Multimedia Card Interface support"
> + depends on ARCH_MXS
> + help
> + This selects the Freescale SSP MMC controller found on MXS based
> + platforms like mx23/28.
> +
> + If unsure, say N.
> +
It should also depend on MXS_DMA?
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH 2/2] mach-mmp: Support for SD/MMC clock adjustment in brownstone
From: Russell King - ARM Linux @ 2011-02-14 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9C2307EC-8314-40D5-A33B-38834F0F4698@marvell.com>
On Sun, Feb 13, 2011 at 10:56:22PM -0800, Philip Rakity wrote:
>
> Set timing for brownstone for SD/MMC cards to enable detection
> timing adjustments are needed when speed > 25MHz
> remove limitation on maximum speed of 25MHz
>
> Signed-off-by: Philip Rakity <prakity@marvell.com>
> ---
> arch/arm/mach-mmp/brownstone.c | 10 +++++++++-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
> index 0e92fd7..35afe60 100644
> --- a/arch/arm/mach-mmp/brownstone.c
> +++ b/arch/arm/mach-mmp/brownstone.c
> @@ -178,14 +178,22 @@ static struct i2c_board_info brownstone_twsi1_info[] = {
> };
>
> static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
> - .max_speed = 25000000,
> + .adjust_clocks = 1,
> + .clk_select = 1,
> + .clk_delay = 31,
> };
>
> static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc1 = {
> + .adjust_clocks = 1,
> + .clk_select = 1,
> + .clk_delay = 15,
> .flags = PXA_FLAG_CARD_PERMANENT,
> };
>
> static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
> + .adjust_clocks = 1,
> + .clk_select = 1,
> + .clk_delay = 31,
You create the new fields in patch 1 and then add values to them in patch 2.
However, they remain unused, so it's impossible to see what the point of
creating them was.
^ permalink raw reply
* [PATCH 10/11] ASoC: Change dependency of ARCH_EXYNOS4
From: Mark Brown @ 2011-02-14 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297671787-10571-11-git-send-email-kgene.kim@samsung.com>
On Mon, Feb 14, 2011 at 05:23:06PM +0900, Kukjin Kim wrote:
> This patch changes dependency of ARCH_EXYNOS4 from ARCH_S5PV310
> according to the change of ARCH name, EXYNOS4.
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
^ permalink raw reply
* [PATCH 6/6] ARM: pm: allow generic sleep code to be used with SMP CPU idle
From: Russell King - ARM Linux @ 2011-02-14 16:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimmSbs7Q_068ERWeKUFV_1Fyxvj37e3r21LZYCL@mail.gmail.com>
On Sun, Feb 13, 2011 at 01:59:54PM -0800, Colin Cross wrote:
> On Fri, Feb 11, 2011 at 8:19 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > Allow the generic sleep code to be used with SMP CPU idle by storing
> > N CPU stack pointers rather than just one.
> >
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> > ?arch/arm/kernel/sleep.S | ? 26 +++++++++++++++++++++++++-
> > ?1 files changed, 25 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
> > index 9f106fa..e10618f 100644
> > --- a/arch/arm/kernel/sleep.S
> > +++ b/arch/arm/kernel/sleep.S
>
> <snip>
>
> > @@ -107,4 +129,6 @@ ENTRY(cpu_resume)
> > ?ENDPROC(cpu_resume)
> >
> > ?sleep_save_sp:
> > - ? ? ? .word ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ preserve stack phys ptr here
> > + ? ? ? .rept ? CONFIG_NR_CPUS
> > + ? ? ? .long ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ preserve stack phys ptr here
> > + ? ? ? .endr
>
> This doesn't compile on CONFIG_SMP=n, CONFIG_NR_CPUS is undefined.
> Including linux/threads.h will provide a default definition.
Added, thanks.
^ permalink raw reply
* [PATCH 1/2] ARM: Introduce THREAD_NOTIFY_COPY for copy_thread() hooks
From: Russell King - ARM Linux @ 2011-02-14 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000201cbcc40$6571c840$305558c0$@deacon@arm.com>
On Mon, Feb 14, 2011 at 12:12:05PM -0000, Will Deacon wrote:
> Hi Catalin,
>
> > Subject: [PATCH 1/2] ARM: Introduce THREAD_NOTIFY_COPY for copy_thread() hooks
> >
> > This patch adds THREAD_NOTIFY_COPY for colling registered handlers
> > during the copy_thread() function call. It also changes the VFP handler
> > to use a switch statement rather than if..else and ignore this event.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > ---
> > arch/arm/include/asm/thread_notify.h | 1 +
> > arch/arm/kernel/process.c | 2 ++
> > arch/arm/vfp/vfpmodule.c | 22 +++++++++++++++-------
> > 3 files changed, 18 insertions(+), 7 deletions(-)
>
> This would be useful for the hw-breakpoint code, where we need to clear
> (memset 0) the breakpoint structures in the child so that they don't get
> unregistered later on.
>
> However, we also need to flush (unregister) breakpoints in flush_thread
> so that they don't persist across an exec. Ideally, we'd have a single
> notifier block and act on THREAD_NOTIFY_{FLUSH,COPY} accordingly, but
> the problem is that THREAD_NOTIFY_FLUSH is only notified *after* zeroing
> most of the thread structure, so the call is currently inlined into
> flush_thread and we don't use a notifier.
It's better to avoid the thread notifier if you don't need all the
facilities it offers as it gets called for every thread switch. Every
additional registration will add additional cycles to the thread switch.
^ permalink raw reply
* [PATCH] Kirkwood: initialize PCIE1 for QNAP TS-419P+
From: Zintis Pētersons @ 2011-02-14 16:38 UTC (permalink / raw)
To: linux-arm-kernel
Initialize PCIE1 on the 6282-based QNAP TS-419P+ since it has a Marvell 9125
SATA chip on each PCI bus.
Signed-off-by: Zintis P?tersons <zintis.petersons@abcsolutions.lv>
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c
b/arch/arm/mach-kirkwood/ts41x-setup.c
index 9a44029..11f23c3 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -153,6 +153,8 @@ static void __init qnap_ts41x_init(void)
static int __init ts41x_pci_init(void)
{
+ u32 dev, rev;
+
if (machine_is_ts41x()) {
/*
* Without this explicit reset, the PCIe SATA
controller @@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
*/
orion_pcie_reset((void __iomem
*)PCIE_VIRT_BASE);
- kirkwood_pcie_init(KW_PCIE0);
+ kirkwood_pcie_id(&dev, &rev);
+ if (dev == MV88F6282_DEV_ID)
+ kirkwood_pcie_init(KW_PCIE1 |
KW_PCIE0);
+ else
+ kirkwood_pcie_init(KW_PCIE0);
}
return 0;
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^ permalink raw reply
* [PATCH] OMAP4: clockdomain: Remove pr_errs' stating unsupported wkdep
From: Paul Walmsley @ 2011-02-14 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297685165-25489-1-git-send-email-rnayak@ti.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> Now that wkup and sleep dependencies are supported (in the
> form of static deps) for OMAP4, remove all instances of
> pr_errs' stating dependencies are still unsupported
> on OMAP4.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Thanks, queued for 2.6.39 in the 'clkdm_statdep_omap4_2.6.39' branch of
git://git.pwsan.com/linux-2.6.
This patch is part of the 'integration-2.6.39' branch of
git://git.pwsan.com/linux-integration as of tag
'integration-2.6.39-20110214-003'.
- Paul
^ permalink raw reply
* [PATCH 3/3] OMAP4: clockdomain: Add wkup/sleep dependency support
From: Paul Walmsley @ 2011-02-14 16:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5cabb72b90513c61bc32035e3888577f@mail.gmail.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> Thanks for the changes. I used the 'integration-2.6.39-20110212-002'
> tag (with the OMAP4 changes as well) and tested OFF mode in suspend
> on my 3430sdp.
> Also boot tested (making sure all static deps are cleared at boot)
> on my 4430sdp.
Sounds good, thanks for the tests.
- Paul
^ permalink raw reply
* [PATCH 1/7] omap: clock: Check for enable/disable ops support
From: Paul Walmsley @ 2011-02-14 16:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <61921a70b7d31d38192210257bca3c0e@mail.gmail.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> > -----Original Message-----
> > From: Paul Walmsley [mailto:paul at pwsan.com]
> > Sent: Sunday, February 13, 2011 4:48 AM
> > To: Rajendra Nayak
> > Cc: linux-omap at vger.kernel.org; b-cousson at ti.com; khilman at ti.com;
> santosh.shilimkar at ti.com; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH 1/7] omap: clock: Check for enable/disable ops
> support
> >
> > On Tue, 8 Feb 2011, Rajendra Nayak wrote:
> >
> > > Check if enable/disable operations are supported for a given
> > > clock node before attempting to call them.
> > >
> > > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> >
> > Thanks, queued in branch 'clk_a_2.6.39' of
> git://git.pwsan.com/linux-2.6.
>
> This patch seems to be needed in clk_autoidle_a_2.6.39 too,
> without which there is an abort at boot on OMAP4.
Thanks for the note - I think 'clk_autoidle_a_2.6.39' was based on
v2.6.38-rc4, rather than on 'clk_a_2.6.39'. Fixed now.
- Paul
^ permalink raw reply
* [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops
From: Paul Walmsley @ 2011-02-14 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ab30a208ca55e9295e25b8c3495dfa31@mail.gmail.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> A couple of issues on the clk_autoidle_a_2.6.39 branch:
> -1- There seems to be a missing fix which causes an abort
> at boot on omap4
> http://marc.info/?l=linux-omap&m=129768574027232&w=2
This should be fixed now that this branch is rebased on your first two
clock patches.
> -2- There is a trivial fix (Patch below) needed which otherwise
> breaks build
Thanks for this, I've folded this fix into the original patch.
- Paul
^ permalink raw reply
* [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's
From: Paul Walmsley @ 2011-02-14 16:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <813a909da6bafa7ce0c15fa77d9d25b9@mail.gmail.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> Yes, the autogen scripts are updated, however they are
> currently in a separate branch (dpll-gatectrl).
> Will merge them into master soon.
OK, great.
> No real reason for not adding OMAP2 dpll autoidle support.
> Its just that I started off trying to do this for OMAP4, and
> then found me touching some omap3 stuff and hence
> also did it for OMAP3.(For some reason I thought there
> were no DPLL's in OMAP2).
That's fine, I have some patches in progress that enable this for the
OMAP2 DPLL and APLLs.
- Paul
^ permalink raw reply
* [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot
From: Paul Walmsley @ 2011-02-14 16:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ee3e93f406daf1a283b8d551f57933e3@mail.gmail.com>
On Mon, 14 Feb 2011, Rajendra Nayak wrote:
> Since I already tested the clk_autoidle_a_2.6.39 branch
> which also has this patch included, you can add a
> Tested-by: Rajendra Nayak <rnayak@ti.com>
Thanks, added.
- Paul
^ permalink raw reply
* [RFC] Inter-processor Mailboxes Drivers
From: Ira W. Snyder @ 2011-02-14 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinu9VMuFgHeFZGXptDYZyJL6P4qxAA9MA8UewpU@mail.gmail.com>
On Mon, Feb 14, 2011 at 12:03:59PM +0200, Ohad Ben-Cohen wrote:
> On Mon, Feb 14, 2011 at 12:01 PM, Jamie Iles <jamie@jamieiles.com> wrote:
> > On Fri, Feb 11, 2011 at 03:19:51PM -0600, Meador Inge wrote:
> >> ? ? 1. Hardware specific bits somewhere under '.../arch/*'. ?Drivers
> >> ? ? ? ?for the MPIC message registers on Power and OMAP4 mailboxes, for
> >> ? ? ? ?example.
> >> ? ? 2. A higher level driver under '.../drivers/mailbox/*'. ?That the
> >> ? ? ? ?pieces in (1) would register with. ?This piece would expose the
> >> ? ? ? ?main kernel API.
> >> ? ? 3. Userspace interfaces for accessing the mailboxes. ?A
> >> ? ? ? ?'/dev/mailbox1', '/dev/mailbox2', etc... mapping, for example.
> >
> > How about using virtio for all of this and having the mailbox as a
> > notification/message passing driver for the virtio backend?
>
> This is exactly what we are doing now, and it looks promising. expect
> patches soon.
I'll be happy to examine the feasibility of doing a port to mpc83xx as
soon as I see the code. :-) I have been using the message registers to
create a software "network card" over PCI (between a host system and an
mpc83xx in a PCI slot). I have wanted to use virtio for this task for a
long time.
I think a uniform interface for the mailbox registers would be a very
useful API.
Thanks,
Ira
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Wolfram Sang @ 2011-02-14 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297650746-12841-2-git-send-email-shawn.guo@freescale.com>
On Mon, Feb 14, 2011 at 10:32:20AM +0800, Shawn Guo wrote:
> This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> The driver calls into mxs-dma via generic dmaengine api for both pio
> and data transfer.
>
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
While trying, I got this lockdep-warning and BUG. It might be that my setup is
wrong, causing all these timeouts. But they probably are meant to be handled
more gracefully? I can continue testing tomorrow, maybe this report already
helps identifying a problem?
[ 1.000000] mxs-mmc mxs-mmc.0: initialized
[ 1.000000] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz
[ 1.010000] mmc0: clock 0Hz busmode 1 powermode 1 cs 0 Vdd 21 width 0 timing 0
[ 1.030000] TCP cubic registered
[ 1.030000] NET: Registered protocol family 17
[ 1.030000] Registering the dns_resolver key type
[ 1.040000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0
[ 1.050000] mxs-mmc mxs-mmc.0: mxs_mmc_set_clk_rate: div1 2, div2 72, ssp 57600000, bit 400000, rate 400000
[ 1.060000] registered taskstats version 1
[ 1.070000] i2c i2c-0: master_xfer[0] W, addr=0x68, len=1
[ 1.070000] i2c i2c-0: master_xfer[1] R, addr=0x68, len=7
[ 1.080000] mmc0: starting CMD52 arg 00000c00 flags 00000195
[ 1.080000] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000
[ 1.090000] mmc0: starting CMD52 arg 80000c08 flags 00000195
[ 1.100000] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000
[ 1.110000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 21 width 0 timing 0
[ 1.110000] mxs-mmc mxs-mmc.0: mxs_mmc_set_clk_rate: div1 2, div2 72, ssp 57600000, bit 400000, rate 400000
[ 1.120000] rtc-ds1307 0-0068: setting system clock to 2000-01-01 00:00:06 UTC (946684806)
[ 1.130000] mmc0: starting CMD0 arg 00000000 flags 000000c0
[ 1.140000] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000
[ 1.150000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0
[ 1.150000] mxs-mmc mxs-mmc.0: mxs_mmc_set_clk_rate: div1 2, div2 72, ssp 57600000, bit 400000, rate 400000
[ 1.170000] mmc0: starting CMD8 arg 000001aa flags 000002f5
[ 1.170000] mmc0: req done (CMD8): -110: 00000000 00000000 00000000 00000000
[ 1.180000] mmc0: starting CMD5 arg 00000000 flags 000002e1
[ 1.180000] mmc0: req failed (CMD5): -110, retrying...
[ 1.180000]
[ 1.180000] =============================================
[ 1.180000] [ INFO: possible recursive locking detected ]
[ 1.180000] 2.6.38-rc2-00375-gb26872a #134
[ 1.180000] ---------------------------------------------
[ 1.180000] swapper/0 is trying to acquire lock:
[ 1.180000] (&(&mxs_chan->lock)->rlock){..-...}, at: [<c01fd704>] mxs_dma_tx_submit+0x24/0xf0
[ 1.180000]
[ 1.180000] but task is already holding lock:
[ 1.180000] (&(&mxs_chan->lock)->rlock){..-...}, at: [<c01fd7f4>] mxs_dma_tasklet+0x24/0x5c
[ 1.180000]
[ 1.180000] other info that might help us debug this:
[ 1.180000] 1 lock held by swapper/0:
[ 1.180000] #0: (&(&mxs_chan->lock)->rlock){..-...}, at: [<c01fd7f4>] mxs_dma_tasklet+0x24/0x5c
[ 1.180000]
[ 1.180000] stack backtrace:
[ 1.180000] Backtrace:
[ 1.180000] [<c0039cd4>] (dump_backtrace+0x0/0x110) from [<c02a31ec>] (dump_stack+0x1c/0x20)
[ 1.180000] r7:00000000 r6:c0378fb8 r5:c0378fd0 r4:c0378cb0
[ 1.180000] [<c02a31d0>] (dump_stack+0x0/0x20) from [<c007ecfc>] (print_deadlock_bug+0xa4/0xd0)
[ 1.180000] [<c007ec58>] (print_deadlock_bug+0x0/0xd0) from [<c007ee9c>] (check_deadlock+0x174/0x1ac)
[ 1.180000] r6:c0378cb0 r5:c053783c r4:80000093
[ 1.180000] [<c007ed28>] (check_deadlock+0x0/0x1ac) from [<c00804c8>] (validate_chain+0x480/0x6b4)
[ 1.180000] [<c0080048>] (validate_chain+0x0/0x6b4) from [<c0080f44>] (__lock_acquire+0x848/0x924)
[ 1.180000] [<c00806fc>] (__lock_acquire+0x0/0x924) from [<c0081104>] (lock_acquire+0xe4/0x104)
[ 1.180000] [<c0081020>] (lock_acquire+0x0/0x104) from [<c02a5f40>] (_raw_spin_lock_irqsave+0x50/0x64)
[ 1.180000] [<c02a5ef0>] (_raw_spin_lock_irqsave+0x0/0x64) from [<c01fd704>] (mxs_dma_tx_submit+0x24/0xf0)
[ 1.180000] r7:c78190dc r6:c798fe14 r5:c798fe14 r4:c7819084
[ 1.180000] [<c01fd6e0>] (mxs_dma_tx_submit+0x0/0xf0) from [<c02092d4>] (mxs_mmc_ac+0x90/0xb4)
[ 1.180000] r8:c03a7120 r7:c037cc98 r6:c798fe14 r5:c798fe14 r4:c79972e0
[ 1.180000] [<c0209244>] (mxs_mmc_ac+0x0/0xb4) from [<c0209640>] (mxs_mmc_start_cmd+0xb0/0xec)
[ 1.180000] r4:c79972e0
[ 1.180000] [<c0209590>] (mxs_mmc_start_cmd+0x0/0xec) from [<c02096bc>] (mxs_mmc_request+0x40/0x4c)
[ 1.180000] r4:c79972e0
[ 1.180000] [<c020967c>] (mxs_mmc_request+0x0/0x4c) from [<c01fe700>] (mmc_request_done+0x9c/0x18c)
[ 1.180000] r5:c7997000 r4:c798fe48
[ 1.180000] [<c01fe664>] (mmc_request_done+0x0/0x18c) from [<c0209828>] (mxs_mmc_request_done+0x160/0x16c)
[ 1.180000] r6:c798fe14 r5:00000000 r4:c79972e0
[ 1.180000] [<c02096c8>] (mxs_mmc_request_done+0x0/0x16c) from [<c0209848>] (mxs_mmc_dma_irq_callback+0x14/0x18)
[ 1.180000] r6:20000013 r5:c78190dc r4:c7819080
[ 1.180000] [<c0209834>] (mxs_mmc_dma_irq_callback+0x0/0x18) from [<c01fd80c>] (mxs_dma_tasklet+0x3c/0x5c)
[ 1.180000] [<c01fd7d0>] (mxs_dma_tasklet+0x0/0x5c) from [<c0052ea8>] (tasklet_action+0xac/0x148)
[ 1.180000] r6:c03cb340 r5:c78190c8 r4:00000000
[ 1.180000] [<c0052dfc>] (tasklet_action+0x0/0x148) from [<c00536d0>] (__do_softirq+0xe0/0x204)
[ 1.180000] [<c00535f0>] (__do_softirq+0x0/0x204) from [<c005384c>] (irq_exit+0x58/0xa0)
[ 1.180000] [<c00537f4>] (irq_exit+0x0/0xa0) from [<c002f084>] (asm_do_IRQ+0x84/0xa4)
[ 1.180000] [<c002f000>] (asm_do_IRQ+0x0/0xa4) from [<c0035ad8>] (__irq_svc+0x38/0x80)
[ 1.180000] Exception stack(0xc0375f20 to 0xc0375f68)
[ 1.180000] 5f20: 00000001 00000004 0005217f 20000013 c0374000 c037a210 c03aa768 00000002
[ 1.180000] 5f40: 4001ee3c 41069265 4001ee08 c0375f74 c0375f38 c0375f68 c007ea54 c0037164
[ 1.180000] 5f60: 20000013 ffffffff
[ 1.180000] r5:f5000000 r4:ffffffff
[ 1.180000] [<c003712c>] (default_idle+0x0/0x3c) from [<c0037750>] (cpu_idle+0x78/0xc8)
[ 1.180000] [<c00376d8>] (cpu_idle+0x0/0xc8) from [<c02a1330>] (rest_init+0xb0/0xd8)
[ 1.180000] r6:c037ed58 r5:00000001 r4:00000000
[ 1.180000] [<c02a1280>] (rest_init+0x0/0xd8) from [<c0008b54>] (start_kernel+0x264/0x2b8)
[ 1.180000] r7:c037a198 r6:c002025c r5:c03aa6e0 r4:c0376ee8
[ 1.180000] [<c00088f0>] (start_kernel+0x0/0x2b8) from [<40008034>] (0x40008034)
[ 1.180000] r6:c0020660 r5:c037602c r4:00053175
[ 1.180000] BUG: spinlock lockup on CPU#0, swapper/0, c78190dc
[ 1.180000] Backtrace:
[ 1.180000] [<c0039cd4>] (dump_backtrace+0x0/0x110) from [<c02a31ec>] (dump_stack+0x1c/0x20)
[ 1.180000] r7:c0374000 r6:c78190dc r5:00000000 r4:00000000
[ 1.180000] [<c02a31d0>] (dump_stack+0x0/0x20) from [<c01bc8a4>] (do_raw_spin_lock+0x118/0x154)
[ 1.180000] [<c01bc78c>] (do_raw_spin_lock+0x0/0x154) from [<c02a5f48>] (_raw_spin_lock_irqsave+0x58/0x64)
[ 1.180000] [<c02a5ef0>] (_raw_spin_lock_irqsave+0x0/0x64) from [<c01fd704>] (mxs_dma_tx_submit+0x24/0xf0)
[ 1.180000] r7:c78190dc r6:c798fe14 r5:c798fe14 r4:c7819084
[ 1.180000] [<c01fd6e0>] (mxs_dma_tx_submit+0x0/0xf0) from [<c02092d4>] (mxs_mmc_ac+0x90/0xb4)
[ 1.180000] r8:c03a7120 r7:c037cc98 r6:c798fe14 r5:c798fe14 r4:c79972e0
[ 1.180000] [<c0209244>] (mxs_mmc_ac+0x0/0xb4) from [<c0209640>] (mxs_mmc_start_cmd+0xb0/0xec)
[ 1.180000] r4:c79972e0
[ 1.180000] [<c0209590>] (mxs_mmc_start_cmd+0x0/0xec) from [<c02096bc>] (mxs_mmc_request+0x40/0x4c)
[ 1.180000] r4:c79972e0
[ 1.180000] [<c020967c>] (mxs_mmc_request+0x0/0x4c) from [<c01fe700>] (mmc_request_done+0x9c/0x18c)
[ 1.180000] r5:c7997000 r4:c798fe48
[ 1.180000] [<c01fe664>] (mmc_request_done+0x0/0x18c) from [<c0209828>] (mxs_mmc_request_done+0x160/0x16c)
[ 1.180000] r6:c798fe14 r5:00000000 r4:c79972e0
[ 1.180000] [<c02096c8>] (mxs_mmc_request_done+0x0/0x16c) from [<c0209848>] (mxs_mmc_dma_irq_callback+0x14/0x18)
[ 1.180000] r6:20000013 r5:c78190dc r4:c7819080
[ 1.180000] [<c0209834>] (mxs_mmc_dma_irq_callback+0x0/0x18) from [<c01fd80c>] (mxs_dma_tasklet+0x3c/0x5c)
[ 1.180000] [<c01fd7d0>] (mxs_dma_tasklet+0x0/0x5c) from [<c0052ea8>] (tasklet_action+0xac/0x148)
[ 1.180000] r6:c03cb340 r5:c78190c8 r4:00000000
[ 1.180000] [<c0052dfc>] (tasklet_action+0x0/0x148) from [<c00536d0>] (__do_softirq+0xe0/0x204)
[ 1.180000] [<c00535f0>] (__do_softirq+0x0/0x204) from [<c005384c>] (irq_exit+0x58/0xa0)
[ 1.180000] [<c00537f4>] (irq_exit+0x0/0xa0) from [<c002f084>] (asm_do_IRQ+0x84/0xa4)
[ 1.180000] [<c002f000>] (asm_do_IRQ+0x0/0xa4) from [<c0035ad8>] (__irq_svc+0x38/0x80)
[ 1.180000] Exception stack(0xc0375f20 to 0xc0375f68)
[ 1.180000] 5f20: 00000001 00000004 0005217f 20000013 c0374000 c037a210 c03aa768 00000002
[ 1.180000] 5f40: 4001ee3c 41069265 4001ee08 c0375f74 c0375f38 c0375f68 c007ea54 c0037164
[ 1.180000] 5f60: 20000013 ffffffff
[ 1.180000] r5:f5000000 r4:ffffffff
[ 1.180000] [<c003712c>] (default_idle+0x0/0x3c) from [<c0037750>] (cpu_idle+0x78/0xc8)
[ 1.180000] [<c00376d8>] (cpu_idle+0x0/0xc8) from [<c02a1330>] (rest_init+0xb0/0xd8)
[ 1.180000] r6:c037ed58 r5:00000001 r4:00000000
[ 1.180000] [<c02a1280>] (rest_init+0x0/0xd8) from [<c0008b54>] (start_kernel+0x264/0x2b8)
[ 1.180000] r7:c037a198 r6:c002025c r5:c03aa6e0 r4:c0376ee8
[ 1.180000] [<c00088f0>] (start_kernel+0x0/0x2b8) from [<40008034>] (0x40008034)
[ 1.180000] r6:c0020660 r5:c037602c r4:00053175
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Russell King - ARM Linux @ 2011-02-14 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297650746-12841-2-git-send-email-shawn.guo@freescale.com>
On Mon, Feb 14, 2011 at 10:32:20AM +0800, Shawn Guo wrote:
> + switch (mmc_resp_type(cmd)) {
> + case MMC_RSP_NONE:
> + break;
> + case MMC_RSP_R1:
> + case MMC_RSP_R1B:
> + case MMC_RSP_R3:
> + cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
> + break;
> + case MMC_RSP_R2:
> + cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
> + cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
> + cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
> + cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
You really should be testing for MMC_RSP_PRESENT and MMC_RSP_136
here. The response types are made up of a bitfield which allows
you to detect what's required rather than having to decode the
response type itself.
> + else if (stat & BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ)
> + data->error = -ENODATA;
> + else if (stat & BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
> + data->error = -EOVERFLOW;
Both of these have a common error code - -EIO.
^ permalink raw reply
* [RFC PATCH 0/2] Support caching of higher page table level entries
From: Catalin Marinas @ 2011-02-14 17:39 UTC (permalink / raw)
To: linux-arm-kernel
Newer processors like Cortex-A15 may cache entries in the higher page
table levels. These cached entries are ASID-tagged and are invalidated
during normal TLB operations.
This causing problems in two areas: context switching and page tables
freeing. The patches in this series contain a more detailed explanation
of the failing scenarios.
Catalin Marinas (2):
ARMv7: Use a reserved TTB rather than ASID 0 during context switch
ARMv7: Invalidate the TLB before freeing page tables
arch/arm/include/asm/tlb.h | 17 +++++++++++++++--
arch/arm/include/asm/tlbflush.h | 16 +++++++++++-----
arch/arm/kernel/head.S | 3 +++
arch/arm/kernel/smp_tlb.c | 11 ++++++-----
arch/arm/mm/proc-v7.S | 11 +++++++----
5 files changed, 42 insertions(+), 16 deletions(-)
--
Catalin
^ permalink raw reply
* [RFC PATCH 1/2] ARMv7: Use a reserved TTB rather than ASID 0 during context switch
From: Catalin Marinas @ 2011-02-14 17:39 UTC (permalink / raw)
To: linux-arm-kernel
Newer processors like Cortex-A15 may cache entries in the higher page
table levels. These cached entries are ASID-tagged and are invalidated
during normal TLB operations.
When using the reserved ASID 0 during a context switch, the processor
may cache an entry from the first level of page tables and tag it with
ASID 0. Later the corresponding first level entry may no longer be valid
(e.g. second level table freed) but the TLB invalidation is done by the
ASID of the corresponding mm structure and not ASID 0. During a
subsequent context switch, the stale level 1 ASID 0 cached entry may be
used to speculatively fetch a TLB entry. If the level 2 page table it
points to contains random data (page freed as the previous process had
been removed) it could create a global TLB entry which is no longer ASID
tagged. This entry is then used in subsequent user space processes.
This patch uses one of the other methods specified in the ARM ARM for
the context switch sequence. It uses the swapper_pg_dir as it only
contains global (kernel) mappings.
Reported-by: Tony Thompson <anthony.thompson@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/kernel/head.S | 3 +++
arch/arm/mm/proc-v7.S | 11 +++++++----
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index c0225da..cc08f1b 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -48,6 +48,9 @@
.globl swapper_pg_dir
.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
+ .globl swapper_pg_dir_phys
+ .equ swapper_pg_dir_phys, KERNEL_RAM_PADDR - 0x4000
+
.macro pgtbl, rd
ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
.endm
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b..38d6436 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -101,19 +101,22 @@ ENDPROC(cpu_v7_dcache_clean_area)
*/
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
- mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
+ ldr r3, =swapper_pg_dir_phys @ prepare global-only TTB 0
ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
+ ALT_SMP(orr r3, r3, #TTB_FLAGS_SMP)
+ ALT_UP(orr r3, r3, #TTB_FLAGS_UP)
#ifdef CONFIG_ARM_ERRATA_430973
+ mov r2, #0
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif
- mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
- isb
-1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
+ mcr p15, 0, r3, c2, c0, 0 @ set global-only TTB 0
isb
mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb
+ mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
+ isb
#endif
mov pc, lr
ENDPROC(cpu_v7_switch_mm)
^ permalink raw reply related
* [RFC PATCH 2/2] ARMv7: Invalidate the TLB before freeing page tables
From: Catalin Marinas @ 2011-02-14 17:39 UTC (permalink / raw)
To: linux-arm-kernel
Newer processors like Cortex-A15 may cache entries in the higher page
table levels. These cached entries are ASID-tagged and are invalidated
during normal TLB operations.
When a level 2 (pte) page table is removed, the current code sequence
first clears the level 1 (pmd) entry, flushes the cache, frees the level
2 table and then invalidates the TLB. Because of the caching of the
higher page table entries, the processor may speculatively create a TLB
entry after the level 2 page table has been freed but before the TLB
invalidation. If such speculative PTW accesses random data, it could
create a global TLB entry that gets used for subsequent user space
accesses.
The patch ensures that the TLB is invalidated before the page table is
freed (pte_free_tlb). Since pte_free_tlb() does not get a vma structure,
the patch also introduces flush_tlb_user_page() which takes an mm_struct
rather than vma_struct. The original flush_tlb_page() is implemented as
a call to flush_tlb_user_page().
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/include/asm/tlb.h | 17 +++++++++++++++--
arch/arm/include/asm/tlbflush.h | 16 +++++++++++-----
arch/arm/kernel/smp_tlb.c | 11 ++++++-----
3 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f41a6f5..565403a 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -102,8 +102,21 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
}
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
-#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
-#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
+
+static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
+ unsigned long addr)
+{
+#if __LINUX_ARM_ARCH__ >= 7
+ flush_tlb_user_page(tlb->mm, addr);
+#endif
+ pte_free(tlb->mm, pte);
+}
+
+static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
+ unsigned long addr)
+{
+ pmd_free(tlb->mm, pmdp);
+}
#define tlb_migrate_finish(mm) do { } while (0)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index ce7378e..7bd9c52cd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -408,17 +408,17 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
}
static inline void
-local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+local_flush_tlb_user_page(struct mm_struct *mm, unsigned long uaddr)
{
const int zero = 0;
const unsigned int __tlb_flag = __cpu_tlb_flags;
- uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
+ uaddr = (uaddr & PAGE_MASK) | ASID(mm);
if (tlb_flag(TLB_WB))
dsb();
- if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+ if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
if (tlb_flag(TLB_V3_PAGE))
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_U_PAGE))
@@ -556,19 +556,25 @@ static inline void clean_pmd_entry(pmd_t *pmd)
#ifndef CONFIG_SMP
#define flush_tlb_all local_flush_tlb_all
#define flush_tlb_mm local_flush_tlb_mm
-#define flush_tlb_page local_flush_tlb_page
+#define flush_tlb_user_page local_flush_tlb_user_page
#define flush_tlb_kernel_page local_flush_tlb_kernel_page
#define flush_tlb_range local_flush_tlb_range
#define flush_tlb_kernel_range local_flush_tlb_kernel_range
#else
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_user_page(struct mm_struct *mm, unsigned long uaddr);
extern void flush_tlb_kernel_page(unsigned long kaddr);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#endif
+static inline void
+flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+{
+ flush_tlb_user_page(vma->vm_mm, uaddr);
+}
+
/*
* If PG_dcache_clean is not set for the page, we need to ensure that any
* cache entries for the kernels virtual memory range are written
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 7dcb352..8f57f32 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -32,6 +32,7 @@ static void on_each_cpu_mask(void (*func)(void *), void *info, int wait,
*/
struct tlb_args {
struct vm_area_struct *ta_vma;
+ struct mm_struct *ta_mm;
unsigned long ta_start;
unsigned long ta_end;
};
@@ -52,7 +53,7 @@ static inline void ipi_flush_tlb_page(void *arg)
{
struct tlb_args *ta = (struct tlb_args *)arg;
- local_flush_tlb_page(ta->ta_vma, ta->ta_start);
+ local_flush_tlb_user_page(ta->ta_mm, ta->ta_start);
}
static inline void ipi_flush_tlb_kernel_page(void *arg)
@@ -92,15 +93,15 @@ void flush_tlb_mm(struct mm_struct *mm)
local_flush_tlb_mm(mm);
}
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+void flush_tlb_user_page(struct mm_struct *mm, unsigned long uaddr)
{
if (tlb_ops_need_broadcast()) {
struct tlb_args ta;
- ta.ta_vma = vma;
+ ta.ta_mm = mm;
ta.ta_start = uaddr;
- on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(vma->vm_mm));
+ on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(mm));
} else
- local_flush_tlb_page(vma, uaddr);
+ local_flush_tlb_user_page(mm, uaddr);
}
void flush_tlb_kernel_page(unsigned long kaddr)
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