* [PATCH] ARM: Thumb-2: Enable ARM/Thumb interworking for v7 cache maintenance
From: Russell King - ARM Linux @ 2011-02-15 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297792565-30401-1-git-send-email-dave.martin@linaro.org>
On Tue, Feb 15, 2011 at 05:56:05PM +0000, Dave Martin wrote:
> Cache maintenence functions may need to be called from low-level
> platform code (such as for omap3).
I'd rather wait until we have the suspend stuff sorted out. I'm
waiting for OMAP folk to sort out what's happening with the sleep*.S
code so that it can have the generic CPU suspend code integrated.
That could result in this change not being required.
^ permalink raw reply
* [PATCH v7 0/4] Introduce support for TI816X processor series
From: Tony Lindgren @ 2011-02-15 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87tyg5rxyn.fsf@ti.com>
* Kevin Hilman <khilman@ti.com> [110215 09:46]:
> Hemant Pedanekar <hemantp@ti.com> writes:
>
> > This patch set adds support for TI816X processor series. This series includes
> > DM8168, C6A816x and AM389x devices.
>
> Acked-by: Kevin Hilman <khilman@ti.com>
Will queue for the upcoming merge window.
Tony
^ permalink raw reply
* [PATCH] ARM: Thumb-2: Enable ARM/Thumb interworking for v7 cache maintenance
From: Dave Martin @ 2011-02-15 17:56 UTC (permalink / raw)
To: linux-arm-kernel
Cache maintenence functions may need to be called from low-level
platform code (such as for omap3).
Some low-level code may need to be built as ARM code even in a Thumb-2
kernel, if the code needs to talk to a non-Thumb-2-aware bootloader
or firmware (again, omap3 is an example).
In order to avoid the need for complex hacks to make calling
these cache maintenance routines work, simply use "bx lr" to
return from these functions.
There's no risk of build failures, since mm/*-v7.S are by definition
built with -march=armv7-a.
bx lr always does the right thing for a pure ARM kernel, so we
shouldn't need any conditional assembly here.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
arch/arm/mm/cache-v7.S | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 6136e68..a5e5aa1 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -29,7 +29,7 @@ ENTRY(v7_flush_icache_all)
mov r0, #0
ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
- mov pc, lr
+ bx lr
ENDPROC(v7_flush_icache_all)
/*
@@ -87,7 +87,7 @@ finished:
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb
isb
- mov pc, lr
+ bx lr
ENDPROC(v7_flush_dcache_all)
/*
@@ -110,7 +110,7 @@ ENTRY(v7_flush_kern_cache_all)
ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
- mov pc, lr
+ bx lr
ENDPROC(v7_flush_kern_cache_all)
/*
@@ -136,7 +136,7 @@ ENTRY(v7_flush_user_cache_all)
* - we have a VIPT cache.
*/
ENTRY(v7_flush_user_cache_range)
- mov pc, lr
+ bx lr
ENDPROC(v7_flush_user_cache_all)
ENDPROC(v7_flush_user_cache_range)
@@ -194,7 +194,7 @@ ENTRY(v7_coherent_user_range)
ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
dsb
isb
- mov pc, lr
+ bx lr
/*
* Fault handling for the cache operation above. If the virtual address in r0
@@ -227,7 +227,7 @@ ENTRY(v7_flush_kern_dcache_area)
cmp r0, r1
blo 1b
dsb
- mov pc, lr
+ bx lr
ENDPROC(v7_flush_kern_dcache_area)
/*
@@ -256,7 +256,7 @@ v7_dma_inv_range:
cmp r0, r1
blo 1b
dsb
- mov pc, lr
+ bx lr
ENDPROC(v7_dma_inv_range)
/*
@@ -274,7 +274,7 @@ v7_dma_clean_range:
cmp r0, r1
blo 1b
dsb
- mov pc, lr
+ bx lr
ENDPROC(v7_dma_clean_range)
/*
@@ -292,7 +292,7 @@ ENTRY(v7_dma_flush_range)
cmp r0, r1
blo 1b
dsb
- mov pc, lr
+ bx lr
ENDPROC(v7_dma_flush_range)
/*
@@ -318,7 +318,7 @@ ENTRY(v7_dma_unmap_area)
add r1, r1, r0
teq r2, #DMA_TO_DEVICE
bne v7_dma_inv_range
- mov pc, lr
+ bx lr
ENDPROC(v7_dma_unmap_area)
__INITDATA
--
1.7.1
^ permalink raw reply related
* [PATCH v7 0/4] Introduce support for TI816X processor series
From: Kevin Hilman @ 2011-02-15 17:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297791319-31891-1-git-send-email-hemantp@ti.com>
Hemant Pedanekar <hemantp@ti.com> writes:
> This patch set adds support for TI816X processor series. This series includes
> DM8168, C6A816x and AM389x devices.
Acked-by: Kevin Hilman <khilman@ti.com>
^ permalink raw reply
* [PATCH v7 4/4] TI816X: Add low level debug support
From: Hemant Pedanekar @ 2011-02-15 17:36 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for low level debugging on TI816X boards. Currently the
support for UART3 console on TI816X EVM is added.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++++++++++
arch/arm/plat-omap/include/plat/serial.h | 8 ++++++++
arch/arm/plat-omap/include/plat/uncompress.h | 7 +++++++
3 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 6a4d413..e1b0f17 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -69,6 +69,12 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
+ cmp \rp, #TI816XUART1 @ ti816x UART offsets different
+ beq 81f @ configure UART1
+ cmp \rp, #TI816XUART2 @ ti816x UART offsets different
+ beq 82f @ configure UART2
+ cmp \rp, #TI816XUART3 @ ti816x UART offsets different
+ beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@@ -91,6 +97,12 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
+81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
+ b 98f
+82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
+ b 98f
+83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
+ b 98f
95: ldr \rp, =ZOOM_UART_BASE
mrc p15, 0, \rv, c1, c0
tst \rv, #1 @ MMU enabled?
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index cec5d56..4102bf4 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,6 +51,11 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
+/* TI816X serial ports */
+#define TI816X_UART1_BASE 0x48020000
+#define TI816X_UART2_BASE 0x48022000
+#define TI816X_UART3_BASE 0x48024000
+
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@@ -81,6 +86,9 @@
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
+#define TI816XUART1 81
+#define TI816XUART2 82
+#define TI816XUART3 83
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ad98b85..30b891c 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,6 +93,10 @@ static inline void flush(void)
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+#define DEBUG_LL_TI816X(p, mach) \
+ _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ TI816XUART##p)
+
static inline void __arch_decomp_setup(unsigned long arch_id)
{
int port = 0;
@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_ZOOM(omap_zoom2);
DEBUG_LL_ZOOM(omap_zoom3);
+ /* TI8168 base boards using UART3 */
+ DEBUG_LL_TI816X(3, ti8168evm);
+
} while (0);
}
--
1.7.3.5
^ permalink raw reply related
* [PATCH v7 3/4] TI816X: Create board support and enable build for TI816X EVM
From: Hemant Pedanekar @ 2011-02-15 17:36 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds minimal support and build configuration for TI816X EVM.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/Kconfig | 5 +++
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-ti8168evm.c | 57 +++++++++++++++++++++++++++++++++
3 files changed, 63 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6a4cfc2..9b4e78f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -299,6 +299,11 @@ config MACH_OMAP_3630SDP
default y
select OMAP_PACKAGE_CBP
+config MACH_TI8168EVM
+ bool "TI8168 Evaluation Module"
+ depends on SOC_OMAPTI816X
+ default y
+
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 742ca67..ec24999 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -224,6 +224,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
hsmmc.o
+obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
# Platform specific device init code
usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
obj-y += $(usbfs-m) $(usbfs-y)
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
new file mode 100644
index 0000000..6282cc4
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -0,0 +1,57 @@
+/*
+ * Code for TI8168 EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+
+static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+};
+
+static void __init ti8168_evm_init_irq(void)
+{
+ omap_board_config = ti8168_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ omap_init_irq();
+}
+
+static void __init ti8168_evm_init(void)
+{
+ omap_serial_init();
+}
+
+static void __init ti8168_evm_map_io(void)
+{
+ omap2_set_globals_ti816x();
+ omapti816x_map_common_io();
+}
+
+MACHINE_START(TI8168EVM, "ti8168evm")
+ /* Maintainer: Texas Instruments */
+ .boot_params = 0x80000100,
+ .map_io = ti8168_evm_map_io,
+ .init_irq = ti8168_evm_init_irq,
+ .timer = &omap_timer,
+ .init_machine = ti8168_evm_init,
+MACHINE_END
--
1.7.3.5
^ permalink raw reply related
* [PATCH v7 2/4] TI816X: Update common OMAP machine specific sources
From: Hemant Pedanekar @ 2011-02-15 17:35 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the common machine specific source files with support for
TI816X.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/clock3xxx_data.c | 5 +++-
arch/arm/mach-omap2/common.c | 21 +++++++++++++++
arch/arm/mach-omap2/control.h | 6 ++++
arch/arm/mach-omap2/id.c | 33 ++++++++++++++++++++++-
arch/arm/mach-omap2/include/mach/entry-macro.S | 13 +++++++++
arch/arm/mach-omap2/io.c | 22 +++++++++++++++-
arch/arm/mach-omap2/irq.c | 5 +++-
arch/arm/mach-omap2/serial.c | 8 +++---
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/io.h | 8 ++++++
arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++++++++++
arch/arm/plat-omap/io.c | 5 +++-
12 files changed, 144 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1..f14d986 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
+ } else if (cpu_is_ti816x()) {
+ cpu_mask = RATE_IN_TI816X;
+ cpu_clkflg = CK_TI816X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void)
/*
* Lock DPLL5 and put it in autoidle.
*/
- if (omap_rev() >= OMAP3430_REV_ES2_0)
+ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index d5eaee3..48de451 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -108,6 +108,27 @@ void __init omap3_map_io(void)
omap2_set_globals_3xxx();
omap34xx_map_common_io();
}
+
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI816X DEVICE ID register is at offset 0x600 from control base).
+ */
+#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
+ TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals ti816x_globals = {
+ .class = OMAP343X_CLASS,
+ .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+ .ctrl = TI816X_CTRL_BASE,
+ .prm = TI816X_PRCM_BASE,
+ .cm = TI816X_PRCM_BASE,
+};
+
+void __init omap2_set_globals_ti816x(void)
+{
+ __omap2_set_globals(&ti816x_globals);
+}
#endif
#if defined(CONFIG_ARCH_OMAP4)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f0629ae..c2804c1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,6 +52,9 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
+/* TI816X spefic control submodules */
+#define TI816X_CONTROL_DEVCONF 0x600
+
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
@@ -241,6 +244,9 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
+/* TI816X CONTROL_DEVCONF register offsets */
+#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
+
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8fd0535..3168b17 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -191,12 +191,19 @@ static void __init omap3_check_features(void)
if (!cpu_is_omap3505() && !cpu_is_omap3517())
omap3_features |= OMAP3_HAS_IO_WAKEUP;
+ omap3_features |= OMAP3_HAS_SDRC;
+
/*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
}
+static void __init ti816x_check_features(void)
+{
+ omap3_features = OMAP3_HAS_NEON;
+}
+
static void __init omap3_check_revision(void)
{
u32 cpuid, idcode;
@@ -287,6 +294,20 @@ static void __init omap3_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
}
break;
+ case 0xb81e:
+ omap_chip.oc = CHIP_IS_TI816X;
+
+ switch (rev) {
+ case 0:
+ omap_revision = TI8168_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = TI8168_REV_ES1_1;
+ break;
+ default:
+ omap_revision = TI8168_REV_ES1_1;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
@@ -381,6 +402,8 @@ static void __init omap3_cpuinfo(void)
/* Already set in omap3_check_revision() */
strcpy(cpu_name, "AM3505");
}
+ } else if (cpu_is_ti816x()) {
+ strcpy(cpu_name, "TI816X");
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
@@ -395,7 +418,7 @@ static void __init omap3_cpuinfo(void)
strcpy(cpu_name, "OMAP3503");
}
- if (cpu_is_omap3630()) {
+ if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
@@ -471,7 +494,13 @@ void __init omap2_check_revision(void)
omap24xx_check_revision();
} else if (cpu_is_omap34xx()) {
omap3_check_revision();
- omap3_check_features();
+
+ /* TI816X doesn't have feature register */
+ if (!cpu_is_ti816x())
+ omap3_check_features();
+ else
+ ti816x_check_features();
+
omap3_cpuinfo();
return;
} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 81985a6..a48690b 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -61,6 +61,14 @@
bne 9998f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
+ bne 9998f
+
+ /*
+ * ti816x has additional IRQ pending register. Checking this
+ * register on omap2 & omap3 has no effect (read as 0).
+ */
+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+ cmp \irqnr, #0x0
9998:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@@ -133,6 +141,11 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
+#ifdef CONFIG_SOC_OMAPTI816X
+ bne 9999f
+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
+ cmp \irqnr, #0x0
+#endif
9999:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 11decd8..fdef379 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
#endif
};
#endif
+
+#ifdef CONFIG_SOC_OMAPTI816X
+static struct map_desc omapti816x_io_desc[] __initdata = {
+ {
+ .virtual = L4_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_34XX_PHYS),
+ .length = L4_34XX_SIZE,
+ .type = MT_DEVICE
+ },
+};
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
@@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_SOC_OMAPTI816X
+void __init omapti816x_map_common_io(void)
+{
+ iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+ _omap2_map_common_io();
+}
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
@@ -402,7 +422,7 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
omap_hwmod_late_init();
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ if (cpu_is_omap24xx() || omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index d151aac..bc524b9 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -108,7 +108,7 @@ static void omap_mask_irq(struct irq_data *d)
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
int spurious = 0;
/*
@@ -203,6 +203,9 @@ void __init omap_init_irq(void)
BUG_ON(!base);
+ if (cpu_is_ti816x())
+ bank->nr_irqs = 128;
+
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 32e91a9..36a2828 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
@@ -759,13 +759,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
p->private_data = uart;
/*
- * omap44xx: Never read empty UART fifo
+ * omap44xx, ti816x: Never read empty UART fifo
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
- if (cpu_is_omap44xx())
+ if (cpu_is_omap44xx() || cpu_is_ti816x())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -847,7 +847,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
- if (cpu_is_omap34xx())
+ if (cpu_is_omap34xx() && !cpu_is_ti816x())
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26ad..e87efe1 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
+#include <plat/ti816x.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 478c5d9..d72ec85 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_SOC_OMAPTI816X
+extern void omapti816x_map_common_io(void);
+#else
+static inline void omapti816x_map_common_io(void)
+{
+}
+#endif
+
#ifdef CONFIG_ARCH_OMAP4
extern void omap44xx_map_common_io(void);
#else
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 0000000..50510f5
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI816X modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI816X_H
+
+#define L4_SLOW_TI816X_BASE 0x48000000
+
+#define TI816X_SCM_BASE 0x48140000
+#define TI816X_CTRL_BASE TI816X_SCM_BASE
+#define TI816X_PRCM_BASE 0x48180000
+
+#define TI816X_ARM_INTC_BASE 0x48200000
+
+#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1295fa..f1ecfa9 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP3
- if (cpu_is_omap34xx()) {
+ if (cpu_is_ti816x()) {
+ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+ return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+ } else if (cpu_is_omap34xx()) {
if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
--
1.7.3.5
^ permalink raw reply related
* [PATCH v7 1/4] TI816X: Update common omap platform files
From: Hemant Pedanekar @ 2011-02-15 17:35 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the common platform files with TI816X support.
The approach taken in this patch is to add TI816X as part of OMAP3 variant where
the cpu class is considered as OMAP34XX and the type is TI816X. This means, both
cpu_is_omap34xx() and cpu_is_ti816x() checks return success on TI816X.
A kernel config option CONFIG_SOC_OMAPTI816X is added under OMAP3 to include
support for TI816X build.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/Kconfig | 5 +++++
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 1 +
arch/arm/plat-omap/include/plat/common.h | 1 +
arch/arm/plat-omap/include/plat/cpu.h | 18 ++++++++++++++++++
5 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ae7f47d..6a4cfc2 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -72,6 +72,11 @@ config SOC_OMAP3430
default y
select ARCH_OMAP_OTG
+config SOC_OMAPTI816X
+ bool "TI816X support"
+ depends on ARCH_OMAP3
+ default y
+
config OMAP_PACKAGE_ZAF
bool
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 256ab3f..f1899a3 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -38,6 +38,7 @@ struct omap_clk {
#define CK_3517 (1 << 9)
#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 11)
+#define CK_TI816X (1 << 12)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..d43e623 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -53,6 +53,7 @@ struct clkops {
#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
#define RATE_IN_36XX (1 << 4)
#define RATE_IN_4430 (1 << 5)
+#define RATE_IN_TI816X (1 << 6)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 29b2afb..1dd97e7 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -66,6 +66,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
+void omap2_set_globals_ti816x(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 29d5953..8198bb6 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
+#define IS_TI_SUBCLASS(subclass, id) \
+static inline int is_ti ##subclass (void) \
+{ \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+}
+
IS_OMAP_CLASS(7xx, 0x07)
IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
@@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
+IS_TI_SUBCLASS(816x, 0x816)
+
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
#define cpu_is_omap16xx() 0
@@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
+#define cpu_is_ti816x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
@@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3530
# undef cpu_is_omap3505
# undef cpu_is_omap3517
+# undef cpu_is_ti816x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
(!omap3_has_iva()) && \
@@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# define cpu_is_omap3517() is_omap3517()
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
+# define cpu_is_ti816x() is_ti816x()
#endif
# if defined(CONFIG_ARCH_OMAP4)
@@ -389,6 +400,10 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+#define TI816X_CLASS 0x81600034
+#define TI8168_REV_ES1_0 TI816X_CLASS
+#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
@@ -423,6 +438,7 @@ IS_OMAP_TYPE(3517, 0x3517)
#define CHIP_IS_OMAP4430ES2 (1 << 11)
#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
+#define CHIP_IS_TI816X (1 << 14)
#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
@@ -461,6 +477,7 @@ extern u32 omap3_features;
#define OMAP3_HAS_ISP BIT(4)
#define OMAP3_HAS_192MHZ_CLK BIT(5)
#define OMAP3_HAS_IO_WAKEUP BIT(6)
+#define OMAP3_HAS_SDRC BIT(7)
#define OMAP3_HAS_FEATURE(feat,flag) \
static inline unsigned int omap3_has_ ##feat(void) \
@@ -475,5 +492,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
OMAP3_HAS_FEATURE(isp, ISP)
OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
#endif
--
1.7.3.5
^ permalink raw reply related
* [PATCH v7 0/4] Introduce support for TI816X processor series
From: Hemant Pedanekar @ 2011-02-15 17:35 UTC (permalink / raw)
To: linux-arm-kernel
This patch set adds support for TI816X processor series. This series includes
DM8168, C6A816x and AM389x devices.
The details can be found at following links:
http://focus.ti.com/general/docs/gencontent.tsp?contentId=77960
http://www.ti.com/ww/en/dsp/davinci-netra/index.shtml
This series is architecturally closer to the OMAP devices. Hence, these patches
are being submitted on linux-omap.
These patches are tested on OMAP3 EVM with multi-omap build.
Note that, additional patches consisting of TI816X specific hwmods, clock data
and DMTIMER changes, are required to enable successful booting on TI816X EVM.
These patches will follow shortly.
The TI816X support is added as part of OMAP3 variant. The approach taken is in
accordance to the discussions in thread related to following post:
http://www.spinics.net/lists/linux-omap/msg41505.html
In addition, TI816X specific customizations/optimizations are handled as a part
of build configuration CONFIG_SOC_OMAPTI816X. Discussed here:
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg41927.html
Hemant Pedanekar (4):
TI816X: Update common omap platform files
TI816X: Update common OMAP machine specific sources
TI816X: Create board support and enable build for TI816X EVM
TI816X: Add low level debug support
arch/arm/mach-omap2/Kconfig | 10 ++++
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-ti8168evm.c | 57 ++++++++++++++++++++++++
arch/arm/mach-omap2/clock3xxx_data.c | 5 ++-
arch/arm/mach-omap2/common.c | 21 +++++++++
arch/arm/mach-omap2/control.h | 6 +++
arch/arm/mach-omap2/id.c | 33 +++++++++++++-
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 +++++
arch/arm/mach-omap2/include/mach/entry-macro.S | 13 +++++
arch/arm/mach-omap2/io.c | 22 +++++++++-
arch/arm/mach-omap2/irq.c | 5 ++-
arch/arm/mach-omap2/serial.c | 8 ++--
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 1 +
arch/arm/plat-omap/include/plat/common.h | 1 +
arch/arm/plat-omap/include/plat/cpu.h | 18 +++++++
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/io.h | 8 +++
arch/arm/plat-omap/include/plat/serial.h | 8 +++
arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++
arch/arm/plat-omap/include/plat/uncompress.h | 7 +++
arch/arm/plat-omap/io.c | 5 ++-
22 files changed, 260 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h
--
1.7.3.5
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Russell King - ARM Linux @ 2011-02-15 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215172948.GE10770@pengutronix.de>
On Tue, Feb 15, 2011 at 06:29:48PM +0100, Wolfram Sang wrote:
> On Tue, Feb 15, 2011 at 05:19:17PM +0000, Russell King - ARM Linux wrote:
> > On Tue, Feb 15, 2011 at 06:13:41PM +0100, Wolfram Sang wrote:
> > > MMC fails for me (note: the card works fine with an mx35-based board)
> > >
> > > mmc0: new high speed MMC card at address 0001
> > > mmcblk0: mmc0:0001 AF HMP 247 MiB
> > > mmcblk0: retrying using single block read
> > > mmcblk0: error -84 transferring data, sector 0, nr 8, card status 0x900
> > > end_request: I/O error, dev mmcblk0, sector 0
> >
> > EILSEQ means CRC failure. Probably unrelated.
>
> Even if it works in another setup? As a result of the above, I can't read the
> partition table of that MMC. The mx35 can do so.
CRC is generated to protect the link between the card and the host. It
means that the CRC computed by the card for the transfer and the CRC
computed by the host didn't match.
In other words, data was corrupted in some way between the card and the
MMC host.
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Wolfram Sang @ 2011-02-15 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215171917.GQ4152@n2100.arm.linux.org.uk>
On Tue, Feb 15, 2011 at 05:19:17PM +0000, Russell King - ARM Linux wrote:
> On Tue, Feb 15, 2011 at 06:13:41PM +0100, Wolfram Sang wrote:
> >
> > > Ah, yes. I can also see the problem here after turning on
> > > DEBUG_SPINLOCK.
> >
> > Ah, okay. After turning it off, it works a lot better :)
>
> That doesn't mean the problem is fixed. [...]
Yes, I know that. I should have put the 'works' above in quotes, sorry.
> > MMC fails for me (note: the card works fine with an mx35-based board)
> >
> > mmc0: new high speed MMC card at address 0001
> > mmcblk0: mmc0:0001 AF HMP 247 MiB
> > mmcblk0: retrying using single block read
> > mmcblk0: error -84 transferring data, sector 0, nr 8, card status 0x900
> > end_request: I/O error, dev mmcblk0, sector 0
>
> EILSEQ means CRC failure. Probably unrelated.
Even if it works in another setup? As a result of the above, I can't read the
partition table of that MMC. The mx35 can do so.
> > SDIO card locks the machine. Is it supposed to work already?
>
> Guess it's the spinlock causing that problem.
Yeah, that could be. In addition, I was just generally interested if SDIO has
been tested by Shawn.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Russell King - ARM Linux @ 2011-02-15 17:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215171341.GD10770@pengutronix.de>
On Tue, Feb 15, 2011 at 06:13:41PM +0100, Wolfram Sang wrote:
>
> > Ah, yes. I can also see the problem here after turning on
> > DEBUG_SPINLOCK.
>
> Ah, okay. After turning it off, it works a lot better :)
That doesn't mean the problem is fixed. The spinlock debugging is there
to find broken code, and it's saying that the code is broken, and in
this case its saying that there's potential for deadlock.
> MMC fails for me (note: the card works fine with an mx35-based board)
>
> mmc0: new high speed MMC card at address 0001
> mmcblk0: mmc0:0001 AF HMP 247 MiB
> mmcblk0: retrying using single block read
> mmcblk0: error -84 transferring data, sector 0, nr 8, card status 0x900
> end_request: I/O error, dev mmcblk0, sector 0
EILSEQ means CRC failure. Probably unrelated.
> SDIO card locks the machine. Is it supposed to work already?
Guess it's the spinlock causing that problem.
^ permalink raw reply
* MMC quirks relating to performance/lifetime.
From: Arnd Bergmann @ 2011-02-15 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinPtiwXmtRy9qS2zZXwuhQDOyO-H8-wmF=fSNnJ@mail.gmail.com>
On Monday 14 February 2011, Andrei Warkentin wrote:
> > There are multiple ways how this could be implemented:
> >
> > 1. Have one exception cache for all "special" blocks. This would normally
> > be for FAT32 subdirectory updates, which always write to the same
> > few blocks. This means you can do small writes efficiently anywhere
> > on the card, but only up to a (small) fixed number of block addresses.
> > If you overflow the table, the card still needs to go through an
> > extra PE for each new entry you write, in order to free up an entry.
> >
> > 2. Have a small number of AUs that can be in a special mode with efficient
> > small writes but inefficient large writes. This means that when you
> > alternate between small and large writes in the same AU, it has to go
> > through a PE on every switch. Similarly, if you do small writes to
> > more than the maximum number of AUs that can be held in this mode, you
> > get the same effect. This number can be as small as one, because that
> > is what FAT32 requires.
> >
> > In both cases, you don't actually have a solution for the problem, you just
> > make it less likely for specific workloads.
>
> Aha, ok. By the way, I did find out that either suggestion works. So
> I'll pull out the reversing portion of the patch. No need to
> overcomplicate :).
BTW, what file system are you using? I could imagine that each of ext4, btrfs
and nilfs2 give you very different results here. It could be that if your
patch is optimizing for one file system, it is actually pessimising for
another one.
What benchmark do you use to find out of your optimizations actually help you?
Arnd
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Wolfram Sang @ 2011-02-15 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215223941.GJ10990@S2100-06.ap.freescale.net>
> Ah, yes. I can also see the problem here after turning on
> DEBUG_SPINLOCK.
Ah, okay. After turning it off, it works a lot better :)
SD seems to work:
mmc0: new high speed SD card at address b368
mmcblk0: mmc0:b368 NCard 1.86 GiB
mmcblk0: p1
mmc0: card b368 removed
SDHC seems to work:
mmc0: new high speed SDHC card at address 0007
mmcblk0: mmc0:0007 SD04G 3.70 GiB
mmcblk0: p1
mmc0: card 0007 removed
MMC fails for me (note: the card works fine with an mx35-based board)
mmc0: new high speed MMC card at address 0001
mmcblk0: mmc0:0001 AF HMP 247 MiB
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, card status 0x900
end_request: I/O error, dev mmcblk0, sector 0
mmcblk0: error -84 transferring data, sector 1, nr 7, card status 0x900
end_request: I/O error, dev mmcblk0, sector 1
mmcblk0: error -84 transferring data, sector 2, nr 6, card status 0x900
end_request: I/O error, dev mmcblk0, sector 2
mmcblk0: error -84 transferring data, sector 3, nr 5, card status 0x900
end_request: I/O error, dev mmcblk0, sector 3
mmcblk0: error -84 transferring data, sector 4, nr 4, card status 0x900
end_request: I/O error, dev mmcblk0, sector 4
mmcblk0: error -84 transferring data, sector 5, nr 3, card status 0x900
end_request: I/O error, dev mmcblk0, sector 5
mmcblk0: error -84 transferring data, sector 6, nr 2, card status 0x900
end_request: I/O error, dev mmcblk0, sector 6
mmcblk0: error -84 transferring data, sector 7, nr 1, card status 0x900
end_request: I/O error, dev mmcblk0, sector 7
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, card status 0x900
end_request: I/O error, dev mmcblk0, sector 0
mmcblk0: error -84 transferring data, sector 1, nr 7, card status 0x900
end_request: I/O error, dev mmcblk0, sector 1
mmcblk0: error -84 transferring data, sector 2, nr 6, card status 0x900
end_request: I/O error, dev mmcblk0, sector 2
mmcblk0: error -84 transferring data, sector 3, nr 5, card status 0x900
end_request: I/O error, dev mmcblk0, sector 3
mmcblk0: error -84 transferring data, sector 4, nr 4, card status 0x900
end_request: I/O error, dev mmcblk0, sector 4
mmcblk0: error -84 transferring data, sector 5, nr 3, card status 0x900
end_request: I/O error, dev mmcblk0, sector 5
mmcblk0: error -84 transferring data, sector 6, nr 2, card status 0x900
end_request: I/O error, dev mmcblk0, sector 6
mmcblk0: error -84 transferring data, sector 7, nr 1, card status 0x900
end_request: I/O error, dev mmcblk0, sector 7
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition table
mmc0: card 0001 removed
SDIO card locks the machine. Is it supposed to work already?
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v2] ARM: vfp: Always save VFP state in vfp_pm_suspend
From: Russell King - ARM Linux @ 2011-02-15 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297724147-6320-1-git-send-email-ccross@android.com>
On Mon, Feb 14, 2011 at 02:55:47PM -0800, Colin Cross wrote:
> diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> index 66bf8d1..7231d18 100644
> --- a/arch/arm/vfp/vfpmodule.c
> +++ b/arch/arm/vfp/vfpmodule.c
> @@ -415,13 +415,13 @@ static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state)
> struct thread_info *ti = current_thread_info();
> u32 fpexc = fmrx(FPEXC);
>
> - /* if vfp is on, then save state for resumption */
> - if (fpexc & FPEXC_EN) {
> + /* save state for resume */
> + if (last_VFP_context[ti->cpu]) {
I'm not entirely happy with this.
It is true that last_VFP_context[] when non-NULL indicates who owns the
hardware VFP state, so saving it would seem logical. However, this new
code now saves the state with the saved fpexc indicating that it's disabled.
This will cause a VFP exception to misbehave by reloading the state, and
then disabling the VFP unit. That will cause another VFP exception which
will find the VFP unit disabled, and re-enable it. All in all, this is
rather wasteful.
So...
/* If lazy disable, re-enable the VFP ready for it to be saved */
if (last_VFP_context[ti->cpu] != &ti->vfpstate) {
fpexc |= FPEXC_EN;
fmxr(FPEXC, fpexc);
}
/* If VFP is on, then save state for resumption */
if (fpexc & FPEXC_EN) {
...
^ permalink raw reply
* [PATCH] ARM: pxa: support 806MHz operating points for PXA31x processors A2 stepping
From: Igor Grinberg @ 2011-02-15 16:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297786849.2596.13.camel@phoenix>
Hi,
On 02/15/11 18:20, Axel Lin wrote:
> PXA3xx Specification Update document states that the 806MHz
> operating points were added for PXA31x processors A2 stepping.
>
> This patch adds 806MHz operating points support for PXA31x A2 stepping.
>
> Signed-off-by: Axel Lin <axel.lin@gmail.com>
> ---
>
> I cannot find any details for PXA31x stepping B1 and B2,
> thus I made this patch for PXA31x stepping A2 only.
>
> Axel
>
> arch/arm/mach-pxa/cpufreq-pxa3xx.c | 23 +++++++++++++++++++----
> 1 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> index 88fbec0..f4f0c2e 100644
> --- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> +++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> @@ -210,15 +210,30 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
>
> /* set default policy and cpuinfo */
> policy->cpuinfo.min_freq = 104000;
> - policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
> +
> + if (cpu_is_pxa300())
> + policy->cpuinfo.max_freq = 624000;
> + else if (cpu_is_pxa310())
> + policy->cpuinfo.max_freq = ((read_cpuid_id() & 0xf) == 0x2) ?
> + 806000 : 624000;
> + else if (cpu_is_pxa320())
> + policy->cpuinfo.max_freq = 806000;
> +
> policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
> policy->max = pxa3xx_get_clk_frequency_khz(0);
> policy->cur = policy->min = policy->max;
>
> - if (cpu_is_pxa300() || cpu_is_pxa310())
> + if (cpu_is_pxa300())
> ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
> -
> - if (cpu_is_pxa320())
> + else if (cpu_is_pxa310())
> + /* PXA310 A2 STEPPING supports 806Mhz operating points */
> + if ((read_cpuid_id() & 0xf) == 0x2)
> + ret = setup_freqs_table(policy,
> + ARRAY_AND_SIZE(pxa320_freqs));
> + else
> + ret = setup_freqs_table(policy,
> + ARRAY_AND_SIZE(pxa300_freqs));
> + else if (cpu_is_pxa320())
> ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
>
> if (ret) {
Yeah, I've proposed something like that about half a year ago:
http://www.spinics.net/lists/arm-kernel/msg92899.html
Eric was not so happy about it back then, may be this time?
Eric, what do you think?
Also, there is one thing that is not related to this patch, but
if you have the hardware, you need to be concerned with,
is that the vcc_core voltage has to be 1.4V, otherwise your
hardware will be unstable.
--
Regards,
Igor.
^ permalink raw reply
* [PATCH v2] ARM: vfp: Always save VFP state in vfp_pm_suspend
From: Catalin Marinas @ 2011-02-15 16:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297724147-6320-1-git-send-email-ccross@android.com>
On Mon, 2011-02-14 at 22:55 +0000, Colin Cross wrote:
> vfp_pm_suspend should save the VFP state any time there is
> a last_VFP_context. If it only saves when the VFP is enabled,
> the state can get lost when, on a UP system:
> Thread 1 uses the VFP
> Context switch occurs to thread 2, VFP is disabled but the
> VFP context is not saved to allow lazy save and restore
> Thread 2 initiates suspend
> vfp_pm_suspend is called with the VFP disabled, but the
> context has not been saved.
>
> Modify vfp_pm_suspend to save the VFP context whenever
> last_VFP_context is set.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH] ARM: Improve the L2 cache performance when PL310 is used
From: Catalin Marinas @ 2011-02-15 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=zUei0tNVObW18+bRd0f7oLSEoDMFTd+3=7JSZ@mail.gmail.com>
On Tue, 2011-02-15 at 11:29 +0000, Srinidhi Kasagar wrote:
> Just curious to know, why the spinlock surrounding
> l2x0_cache_sync still exists? I see that
> Catalin's first version adds void lock for PL310
> as they are atomic.
On PL310, range operations and the cache sync don't need the spinlock.
However, TI pushed optimisations to use "all" operations for large
ranges. These operations are background and you need to use a cache sync
until completed. You also need locks around since starting other
operations while a background one is active is unpredictable.
--
Catalin
^ permalink raw reply
* [PATCH] OMAP: Fix Memory Leaks in Smartreflex driver
From: Kevin Hilman @ 2011-02-15 16:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297757430-3059-1-git-send-email-shweta.gulati@ti.com>
Shweta Gulati <shweta.gulati@ti.com> writes:
> This Patch frees all the dynamically allocated memory
> which couldn't have been released in some error hitting cases.
>
> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
> Cc: linux-arm-kernel at lists.infradead.org
Thanks, queuing as a fix for 2.6.38-rc (branch: for_2.6.38/pm-fixes)
Kevin
> ---
> arch/arm/mach-omap2/smartreflex.c | 18 ++++++++++++------
> 1 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
> index a1f532e..5af8829 100644
> --- a/arch/arm/mach-omap2/smartreflex.c
> +++ b/arch/arm/mach-omap2/smartreflex.c
> @@ -284,6 +284,7 @@ error:
> dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
> "interrupt handler. Smartreflex will"
> "not function as desired\n", __func__);
> + kfree(name);
> kfree(sr_info);
> return ret;
> }
> @@ -881,7 +882,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
> ret = sr_late_init(sr_info);
> if (ret) {
> pr_warning("%s: Error in SR late init\n", __func__);
> - return ret;
> + goto err_release_region;
> }
> }
>
> @@ -892,14 +893,17 @@ static int __init omap_sr_probe(struct platform_device *pdev)
> * not try to create rest of the debugfs entries.
> */
> vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
> - if (!vdd_dbg_dir)
> - return -EINVAL;
> + if (!vdd_dbg_dir) {
> + ret = -EINVAL;
> + goto err_release_region;
> + }
>
> dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
> if (IS_ERR(dbg_dir)) {
> dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
> __func__);
> - return PTR_ERR(dbg_dir);
> + ret = PTR_ERR(dbg_dir);
> + goto err_release_region;
> }
>
> (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
> @@ -915,7 +919,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
> if (IS_ERR(nvalue_dir)) {
> dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
> "for n-values\n", __func__);
> - return PTR_ERR(nvalue_dir);
> + ret = PTR_ERR(nvalue_dir);
> + goto err_release_region;
> }
>
> omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
> @@ -924,7 +929,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
> " corresponding vdd vdd_%s. Cannot create debugfs"
> "entries for n-values\n",
> __func__, sr_info->voltdm->name);
> - return -ENODATA;
> + ret = -ENODATA;
> + goto err_release_region;
> }
>
> for (i = 0; i < sr_info->nvalue_count; i++) {
^ permalink raw reply
* [PATCH] ARM: errata: pl310 cache sync operation may be faulty
From: Catalin Marinas @ 2011-02-15 16:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297768683-30273-1-git-send-email-srinidhi.kasagar@stericsson.com>
On 15 February 2011 11:18, srinidhi kasagar
<srinidhi.kasagar@stericsson.com> wrote:
> +config ARM_ERRATA_753970
> + ? ? ? bool "ARM errata: cache sync operation may be faulty"
> + ? ? ? depends on CACHE_PL310
> + ? ? ? help
> + ? ? ? ? This option enables the workaround for the 753970 PL310 erratum.
Is this number correct? I couldn't find it in ARM's internal database.
> + ? ? ? ? Under some condition the effect of cache sync operation on
> + ? ? ? ? the store buffer still remains when the operation completes.
> + ? ? ? ? This means that the store buffer is always asked to drain and
> + ? ? ? ? this prevents it from merging any further writes. The workaround
> + ? ? ? ? is to replace the normal offset of cache sync operation (0x730)
> + ? ? ? ? by another offset targeting an unmapped PL310 register 0x740.
> + ? ? ? ? This has the same effect as the cache sync operation: store buffer
> + ? ? ? ? drain and waiting for all buffers empty.
You may want to specify the revision number this applies to so that
people to enable it if not needed.
--
Catalin
^ permalink raw reply
* [PATCHv2] omap2/3: dmtimer: Enable autoidle
From: Tero Kristo @ 2011-02-15 16:30 UTC (permalink / raw)
To: linux-arm-kernel
This saves some power. OMAP4 version should check for GPT module ID, as
autoidle is only supported on a subset of these.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
---
arch/arm/plat-omap/dmtimer.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf..ee9f6eb 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
l |= 0x02 << 3; /* Set to smart-idle mode */
l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
+ /* Enable autoidle on OMAP2 / OMAP3 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ l |= 0x1 << 0;
+
/*
* Enable wake-up on OMAP2 CPUs.
*/
--
1.7.1
^ permalink raw reply related
* [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Vishwanath Sripathy @ 2011-02-15 16:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215171652.601c9c68.jhnikula@gmail.com>
> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Jarkko Nikula
> Sent: Tuesday, February 15, 2011 8:47 PM
> To: Shweta Gulati
> Cc: Nishanth Menon; Thara Gopinath; linux-omap at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on
> TWL
>
> On Tue, 15 Feb 2011 13:28:58 +0530
> Shweta Gulati <shweta.gulati@ti.com> wrote:
>
> > This patch is based on LO PM Branch and Smartreflex has been
> > tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
> > OMAP2430 SDP.
> >
> I saw this was working on N900 (kind of special instrumentation
> setup) after enabling /sys/kernel/debug/voltage/[vdd_core |
> vdd_mpu]/smartreflex/autocomp. Few comments below.
>
> > @@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
> > omap3_core_volt_info.vp_vddmax =
> OMAP3630_VP2_VLIMITTO_VDDMAX;
> > }
> ...
> > + if (!twl_sr_enable_autoinit)
> > + omap3_twl_set_sr_bit(true);
> ...
> > +int __init omap3_twl_set_sr_bit(bool enable)
> > +{
> > + u8 temp;
> > + int ret;
> > + if (twl_sr_enable_autoinit)
> > + pr_warning("%s: unexpected multiple calls\n", __func__);
> > +
> > + ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
> > + TWL4030_DCDC_GLOBAL_CFG);
> > + if (ret)
> > + goto err;
> > +
> > + if (enable)
> > + temp |= SMARTREFLEX_ENABLE;
> > + else
> > + temp &= ~SMARTREFLEX_ENABLE;
> > +
> > + ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
> > + TWL4030_DCDC_GLOBAL_CFG);
>
> Would it make more sense to set only the flag here and do the register
> writes when omap3_twl_init is executing? Then it's not so strict when
> the board code calls this function.
What if board code calls this function after twl_init is executed? Then
you will not clear the bit right?
Intention of this function is to make sure the bit is set/cleared when it
is called.
vishwa
>
> > + if (!ret) {
> > + twl_sr_enable_autoinit = true;
> > + return 0;
>
> Should this be twl_sr_enable_autoinit = enable (if going to do
> register write here)?
>
> --
> Jarkko
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCHv2] omap2/3: dmtimer: Enable autoidle
From: Santosh Shilimkar @ 2011-02-15 16:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <878vxhuv6w.fsf@ti.com>
> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at ti.com]
> Sent: Tuesday, February 15, 2011 9:50 PM
> To: Santosh Shilimkar
> Cc: Tero Kristo; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCHv2] omap2/3: dmtimer: Enable autoidle
>
> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>
> >> -----Original Message-----
> >> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> >> owner at vger.kernel.org] On Behalf Of Tero Kristo
> >> Sent: Tuesday, February 15, 2011 10:00 PM
> >> To: linux-omap at vger.kernel.org
> >> Cc: linux-arm-kernel at lists.infradead.org
> >> Subject: [PATCHv2] omap2/3: dmtimer: Enable autoidle
> >>
> >> This saves some power. OMAP4 version should check for GPT module
> ID,
> >> as
> >> autoidle is only supported on a subset of these.
> >>
> >> Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
> >> ---
> >> arch/arm/plat-omap/dmtimer.c | 4 ++++
> >> 1 files changed, 4 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-
> >> omap/dmtimer.c
> >> index 1d706cf..ee9f6eb 100644
> >> --- a/arch/arm/plat-omap/dmtimer.c
> >> +++ b/arch/arm/plat-omap/dmtimer.c
> >> @@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct
> >> omap_dm_timer *timer)
> >> l |= 0x02 << 3; /* Set to smart-idle mode */
> >> l |= 0x2 << 8; /* Set clock activity to perserve f-clock on
> >> idle */
> >>
> >> + /* Enable autoidle on OMAP2 / OMAP3 */
> >> + if (cpu_is_omap24xx() || cpu_is_omap34xx())
> >> + l |= 0x1 << 0;
> >> +
> > We should get rid of this CPU checks. How about adding a flag
> > and populating it on init for the architectures it supports.
> >
>
> Instead, this should be implemented on top of Tarun's hwmod
> conversion
> which knows that different timers have different capabilities (e.g.
> 1ms)
> and autoidle can be set based on capabilities.
>
You are right. Looking at patches it's seems to be already
implemented.
So this patch isn't needed really.
Regards,
Santosh
^ permalink raw reply
* [PATCH] i2c-pxa: fix unbinding/rebinding of the device
From: Uwe Kleine-König @ 2011-02-15 16:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimO1KFNm5xZ+2qJoGQq-ndVg0ER3KKwf0RYYOLK@mail.gmail.com>
On Tue, Feb 15, 2011 at 04:59:28PM +0300, Dmitry Eremin-Solenikov wrote:
> Hello, all
>
> 2011/1/8 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> > On Sat, Jan 08, 2011 at 07:06:44PM +0300, Dmitry Eremin-Solenikov wrote:
> >> When a "pxa2xx-i2c" device was unbound (e.g. via sysfs) the remove
> >> callback was not called because it was discarded when linking the
> >> kernel. ?Because of that the resources allocated in probe were not
> >> freed and so a clean unbind/rebind was impossible.
> >>
> >> Fix that by moving the remove callback to .devexit.text.
> >>
> >> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> > Acked-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
>
> I see this patch is still not pushed to neither linus nor linux-next.
> Should I put it into rmk's patch system? Or will it find it's way to main kernel
> via other paths?
rmk's patch system isn't the right place. Ben needs to take it. Ben?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH] ARM: pxa: support 806MHz operating points for PXA31x processors A2 stepping
From: Axel Lin @ 2011-02-15 16:20 UTC (permalink / raw)
To: linux-arm-kernel
PXA3xx Specification Update document states that the 806MHz
operating points were added for PXA31x processors A2 stepping.
This patch adds 806MHz operating points support for PXA31x A2 stepping.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
I cannot find any details for PXA31x stepping B1 and B2,
thus I made this patch for PXA31x stepping A2 only.
Axel
arch/arm/mach-pxa/cpufreq-pxa3xx.c | 23 +++++++++++++++++++----
1 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 88fbec0..f4f0c2e 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -210,15 +210,30 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
/* set default policy and cpuinfo */
policy->cpuinfo.min_freq = 104000;
- policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
+
+ if (cpu_is_pxa300())
+ policy->cpuinfo.max_freq = 624000;
+ else if (cpu_is_pxa310())
+ policy->cpuinfo.max_freq = ((read_cpuid_id() & 0xf) == 0x2) ?
+ 806000 : 624000;
+ else if (cpu_is_pxa320())
+ policy->cpuinfo.max_freq = 806000;
+
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
policy->max = pxa3xx_get_clk_frequency_khz(0);
policy->cur = policy->min = policy->max;
- if (cpu_is_pxa300() || cpu_is_pxa310())
+ if (cpu_is_pxa300())
ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
-
- if (cpu_is_pxa320())
+ else if (cpu_is_pxa310())
+ /* PXA310 A2 STEPPING supports 806Mhz operating points */
+ if ((read_cpuid_id() & 0xf) == 0x2)
+ ret = setup_freqs_table(policy,
+ ARRAY_AND_SIZE(pxa320_freqs));
+ else
+ ret = setup_freqs_table(policy,
+ ARRAY_AND_SIZE(pxa300_freqs));
+ else if (cpu_is_pxa320())
ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
if (ret) {
--
1.7.2
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