* [RFC] MMC: error handling improvements
From: Pawel Moll @ 2011-02-16 19:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215230311.GT4152@n2100.arm.linux.org.uk>
Hi,
> The adaptive clock
> rate algorithm can probably do with a lot more work to avoid it up-
> clocking to a rate which has proven to never work. I'd actually go as
> far as to say that the algorithm probably has a lot to be desired - but
> it seems to work for my test scenarios.
I've just gave it a try (on top of a clean 2.6.38-rc5):
/ # dd if=/dev/mmcblk0 of=/dev/null bs=128k count=10
10+0 records in
10+0 records out
1310720 bytes (1.3MB) copied, 2.922722 seconds, 437.9KB/s
/ # cat /dev/sda > /dev/null &
/ # dd if=/dev/mmcblk0 of=/dev/null bs=128k count=10
mmcblk0: error -5 transferring data, sector 0, nr 120, cmd response 0x900, card status 0xb00
mmcblk0: error -5 transferring data, sector 0, nr 120, cmd response 0x900, card status 0xb00
mmcblk0: retrying with slower /2 clock rate
mmcblk0: error -5 transferring data, sector 0, nr 120, cmd response 0x900, card status 0xb00
mmcblk0: retrying with slower /4 clock rate
mmcblk0: error -5 transferring data, sector 0, nr 120, cmd response 0x900, card status 0xb00
mmcblk0: retrying with slower /8 clock rate
mmcblk0: error -5 transferring data, sector 0, nr 120, cmd response 0x900, card status 0xb00
mmcblk0: retrying with slower /16 clock rate
10+0 records in
10+0 records out
1310720 bytes (1.3MB) copied, 46.763456 seconds, 27.4KB/s
/ # kill %1
/ #
[1]+ Terminated cat /dev/sda 1>/dev/null
/ # dd if=/dev/mmcblk0 of=/dev/null bs=128k count=10
10+0 records in
10+0 records out
1310720 bytes (1.3MB) copied, 46.539866 seconds, 27.5KB/s
/ # sleep 30
/ # dd if=/dev/mmcblk0 of=/dev/null bs=128k count=10
10+0 records in
10+0 records out
1310720 bytes (1.3MB) copied, 46.540215 seconds, 27.5KB/s
So it does the right thing with decreasing the clock rate in face of
problems, I just can't see it clocking it back up...
Cheers!
Pawe?
^ permalink raw reply
* [RFC] MMC: error handling improvements
From: Linus Walleij @ 2011-02-16 18:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8yaoc6c7tan.fsf@huya.qualcomm.com>
2011/2/16 David Brown <davidb@codeaurora.org>:
> On Tue, Feb 15 2011, Russell King - ARM Linux wrote:
>
>> This patch is for RFC only; it needs splitting up somewhat. ?However, I
>> wanted to get it out there for some comment.
>
> Just for kicks, I applied this and ran it on an MSM target (8x50). ?It
> seems to cause lots of:
>
> ?mmc0: Data timeout
> ?mmc0: Controller has been re-initialized
> ?...
> ?mmc0: Data CRC error
>
> and I can post more if you would find them interesting. ?Eventually the
> MSM mmc driver derefernces a null pointer in the interrupt code.
>
> It's also possible this is finding problems in our SDCC driver.
The SDCC is obviously an MMCI derivate, VHDL hacking
on top of ARMs source code for PL180/PL181.
Why do you insist on maintaining a forked driver?
Please consider switching to using mmci.c like everyone else.
The quirks we have in place for U300, Nomadik and Ux500
should show you the way for how to do this (yes we did the
same thing, hacking the ARM VHDL).
If I remember correctly I could even see that some early
Android sources were using Russells mmci.c driver before this
fork was created.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Rabin Vincent @ 2011-02-16 17:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <146267380211262372@unknownmsgid>
(adding tglx)
On Wed, Feb 16, 2011 at 21:47, Will Deacon <will.deacon@arm.com> wrote:
>> >> Several of the platforms using the GIC also have GPIO code which uses
>> >> set_irq_chained_handler(). ?I think you will have to modify all of
>> >> these to call irq_eoi() appropriately and not the other functions.
>> >> Some of these will also likely be used with other interrupt handlers
>> >> than the GIC, though.
>> >
>> > Hmm, I had a quick look at some platforms that do this (mach-dove and
>> > plat-spear) and I don't see what the problem is. They use their own irq_chip
>> > structures, with their own function pointers, so this doesn't seem to relate
>> > to the GIC at all. What am I missing?!
>>
>> The chained handlers are usually installed on GIC interrupts. ?So, when
>> a chained handler does something like this
>>
>> ? ? ? desc->irq_data.chip->irq_unmask(&desc->irq_data);
>>
>> the desc->irq_data.chip refers to the gic_chip. ?These handlers are
>> written with the knowledge of what flow handler the GIC uses and what
>> functions it implements, so when you change that, the chained handler
>> code will not work correctly, and they'll need to be updated just like
>> you've updated the cascade IRQ handler.
>
> Ah yes, thanks for the explanation. After looking at the plat-omap code
> I finally understand what's going on and I can't help but feel that the
> chained GPIO handlers are terminally broken! The generic irq chip high-level
> handlers (handle_{edge,level}_irq for example) at least check to see if
> the irq_chip functions are non-NULL before calling them.
>
> Ideally, the chained handler would be able to query the irq_chip to find
> out what types of IRQ flow-control it supports and then assume that behaviour.
Thomas, suggestions on how best to handle this? (Some of these chained
handlers are the ones in plat-omap/gpio.c, plat-nomadik/gpio.c, and
mach-s5pv310/irq-combiner.c.)
>
>> In fact, I think that 846afbd1 ("GIC: Dont disable INT in ack callback")
>> has broken not just GIC cascading interrupts but assumptions in several
>> of these chained handlers, since several of them seem to have been
>> written assuming (invalidly) that irq_ack() masks the interrupt, but
>> this is no longer the case with the GIC after that commit.
>
> Yep - it was further reaching that I originally thought. The question now is:
> is it worth changing all of these handlers or are we better off hacking the gic
> code so that .irq_ack calls .irq_eoi? In the case of the latter, your performance
> will suck in a virtualised environment, but that's better than broken.
^ permalink raw reply
* [PATCH] ARM: reenable DEBUG_SECTION_MISMATCH
From: Randy Dunlap @ 2011-02-16 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297876993-4146-1-git-send-email-u.kleine-koenig@pengutronix.de>
On Wed, 16 Feb 2011 18:23:13 +0100 Uwe Kleine-K?nig wrote:
> For 2.6.38-rc4-git9 only 29 out of 133 defconfigs still produce section
> mismatches. These defconfigs produce 55 mismatches (weighted sum, so
> maybe less uniq mismatches).
>
> This is in my opinion enough to start scaring people about the remaining
> problems.
Yes, we have way too many of these and need more eyes on them.
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> ---
> lib/Kconfig.debug | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index 3967c23..1130dd4 100644
> --- a/lib/Kconfig.debug
> +++ b/lib/Kconfig.debug
> @@ -102,7 +102,7 @@ config HEADERS_CHECK
>
> config DEBUG_SECTION_MISMATCH
> bool "Enable full Section mismatch analysis"
> - depends on UNDEFINED || (BLACKFIN)
> + depends on ARM || BLACKFIN
I would even like something like this:
depends on ARM || BLACKFIN || KERNEL_DEVELOPER
or even
select DEBUG_SECTION_MISMATCH if KERNEL_DEVELOPER
to make these warnings appear... but even with today's other warnings, lots
of them are ignored.
> default y
> # This option is on purpose disabled for now.
> # It will be enabled when we are down to a reasonable number
> --
---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***
^ permalink raw reply
* [PATCH] ARM: reenable DEBUG_SECTION_MISMATCH
From: Uwe Kleine-König @ 2011-02-16 17:23 UTC (permalink / raw)
To: linux-arm-kernel
For 2.6.38-rc4-git9 only 29 out of 133 defconfigs still produce section
mismatches. These defconfigs produce 55 mismatches (weighted sum, so
maybe less uniq mismatches).
This is in my opinion enough to start scaring people about the remaining
problems.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
lib/Kconfig.debug | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 3967c23..1130dd4 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -102,7 +102,7 @@ config HEADERS_CHECK
config DEBUG_SECTION_MISMATCH
bool "Enable full Section mismatch analysis"
- depends on UNDEFINED || (BLACKFIN)
+ depends on ARM || BLACKFIN
default y
# This option is on purpose disabled for now.
# It will be enabled when we are down to a reasonable number
--
1.7.2.3
^ permalink raw reply related
* [PATCH] omap: Move omap2_check_revision and omap_sram_init out of map_io
From: Tony Lindgren @ 2011-02-16 17:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215015320.GX20795@atomide.com>
* Tony Lindgren <tony@atomide.com> [110214 17:52]:
> * Tony Lindgren <tony@atomide.com> [110214 15:51]:
> > With the early init changes we just want to map IO in map_io.
> > Both omap2_check_revision and omap_sram_init can be moved to
> > happen later in omap2_init_common_infrastructure.
> >
> > Note that now we can now remove _omap2_map_common_io and remove
> > the extra flushes too as devicemaps_init will take care of it.
>
> Hmm this one seems to need a bit more work, won't work on 2420.
That's because calling iotable_init after bootmem_init will skip
calling arm_bootmem_init and the new memblock_region we never
call reserve_bootmem on the new entry. So let's skip this for now.
If we want to do SoC detection and SRAM init later during the
boot, we'd have to allocate SRAM the same way as dma-mapping
and ioremap code does.
Regards,
Tony
^ permalink raw reply
* [PATCH] TI816X: Update to use init_early
From: Tony Lindgren @ 2011-02-16 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215180533.GA20795@atomide.com>
* Tony Lindgren <tony@atomide.com> [110215 10:04]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [110215 10:00]:
> > On Tue, Feb 15, 2011 at 11:06:08PM +0530, Hemant Pedanekar wrote:
> > > +static void __init ti8168_evm_init_irq(void)
> > > +{
> > > + omap_board_config = ti8168_evm_config;
> > > + omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
> > > + omap2_init_common_infrastructure();
> > > + omap2_init_common_devices(NULL, NULL);
> > > + omap_init_irq();
> > > +}
> >
> > What here can use the new init_early hook in the machine record?
>
> I can fix this up for the init_early changes when I merge the branches
> together.
Here's the patch to do that.
Tony
From: Tony Lindgren <tony@atomide.com>
Date: Wed, 16 Feb 2011 08:45:46 -0800
Subject: [PATCH] TI816X: Update to use init_early
Update to use init_early
Signed-off-by: Tony Lindgren <tony@atomide.com>
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -27,12 +27,16 @@
static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
};
-static void __init ti8168_evm_init_irq(void)
+static void __init ti8168_init_early(void)
{
omap_board_config = ti8168_evm_config;
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
+}
+
+static void __init ti8168_evm_init_irq(void)
+{
omap_init_irq();
}
@@ -51,6 +55,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.boot_params = 0x80000100,
.map_io = ti8168_evm_map_io,
+ .init_early = ti8168_init_early,
.init_irq = ti8168_evm_init_irq,
.timer = &omap_timer,
.init_machine = ti8168_evm_init,
^ permalink raw reply
* [PATCH 16/17] mc13xxx: mfd_cell is now implicitly available to drivers
From: Andres Salomon @ 2011-02-16 17:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216094154.GV13279@pengutronix.de>
On Wed, 16 Feb 2011 10:41:54 +0100
Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> On Fri, Feb 11, 2011 at 06:19:21PM -0800, Andres Salomon wrote:
> >
> > The cell's platform_data is now accessed with a helper function;
> > change clients to use that, and remove the now-unused data_size.
> >
> > Note that mfd-core no longer makes a copy of platform_data, but the
> why was this changed and where? I'm not able to find your complete
> series via gmane.
http://permalink.gmane.org/gmane.linux.kernel/1099164
I screwed up the threading, so the patches aren't underneath that
one. Patchwork provides them nicely, though.
Here are the relevant patches:
https://patchwork.kernel.org/patch/551241/
https://patchwork.kernel.org/patch/551251/
https://patchwork.kernel.org/patch/551261/
..through
https://patchwork.kernel.org/patch/551451/
The next series is here:
http://thread.gmane.org/gmane.linux.kernel/1100514/focus=6046
^ permalink raw reply
* platform data and mfd design question
From: Mark Brown @ 2011-02-16 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5B8F61.3090105@stericsson.com>
On Wed, Feb 16, 2011 at 09:48:33AM +0100, Linus Walleij wrote:
> On 02/15/2011 10:51 PM, Abhijeet Dharmapurikar wrote:
> >Msm on the other hand declares the struct mfd_cell subdevice[] array in
> >the board file and passes this on to the core driver via platfom data.
> This way the platform data tells the core driver what kind of
> silicon it has "hey, PM8058, guess what, you have an RTC!"
> which looks backwards to me, especially given that it does
> not need any fancy platform data at all, just two IRQ numbers
> which the core driver can very well handle.
Indeed, and the RTC would still be useful even without IRQ support I
imagine (it should still be able to tell you the time).
^ permalink raw reply
* [PATCH] ARM: Avoid discarding sections that might have SMP_ON_UP fixups
From: Dave Martin @ 2011-02-16 16:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110211163247.GB31529@n2100.arm.linux.org.uk>
Hi,
On Fri, Feb 11, 2011 at 04:32:47PM +0000, Russell King - ARM Linux wrote:
[...]
> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
> index 45b5651..343d29f 100644
> --- a/arch/arm/kernel/vmlinux.lds.S
> +++ b/arch/arm/kernel/vmlinux.lds.S
> @@ -21,6 +21,12 @@
> #define ARM_CPU_KEEP(x)
> #endif
>
> +#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
> +#define ARM_EXIT_KEEP(x) x
> +#else
> +#define ARM_EXIT_KEEP(x)
> +#endif
> +
> OUTPUT_ARCH(arm)
> ENTRY(stext)
>
> @@ -43,6 +49,7 @@ SECTIONS
> _sinittext = .;
> HEAD_TEXT
> INIT_TEXT
> + ARM_EXIT_KEEP(EXIT_TEXT)
> _einittext = .;
> ARM_CPU_DISCARD(PROC_INFO)
> __arch_info_begin = .;
> @@ -71,6 +78,7 @@ SECTIONS
> #ifndef CONFIG_XIP_KERNEL
> __init_begin = _stext;
> INIT_DATA
> + ARM_EXIT_KEEP(EXIT_DATA)
> #endif
> }
>
> @@ -166,6 +174,7 @@ SECTIONS
> . = ALIGN(PAGE_SIZE);
> __init_begin = .;
> INIT_DATA
> + ARM_EXIT_KEEP(EXIT_DATA)
> . = ALIGN(PAGE_SIZE);
> __init_end = .;
> #endif
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
This works for me in a case known to fail without the patch.
Tested-by: Dave Martin <dave.martin@linaro.org>
I still don't quite understand the intricacies of how vmlinux
is laid out, but the patch looks sensible.
Do you need anything more from me on this? If not, I will
throw away my patch and replace it with yours.
Cheers
---Dave
^ permalink raw reply
* [PATCH v2 1/1] OMAP: IOMMU: add support to callback during fault handling
From: David Cohen @ 2011-02-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikK0zAYtSaA1LCdkn2t4_XiTH_DmESEzw8MLvfU@mail.gmail.com>
On Tue, Feb 15, 2011 at 5:10 PM, David Cohen <dacohen@gmail.com> wrote:
> On Tue, Feb 15, 2011 at 4:48 PM, Hiroshi DOYU <Hiroshi.DOYU@nokia.com> wrote:
>> Hi David,
>
> Hi Hiroshi,
>
>>
>> Sorry for a bit late reply....
>
> You're just in time. :)
>
>>
>> From: David Cohen <dacohen@gmail.com>
>> Subject: [PATCH v2 1/1] OMAP: IOMMU: add support to callback during fault handling
>> Date: Tue, 15 Feb 2011 16:36:31 +0200
>>
>>> Add support to register a callback for IOMMU fault situations. Drivers using
>>> IOMMU module might want to be informed when such errors happen in order to
>>> debug it or react.
>>>
>>> Signed-off-by: David Cohen <dacohen@gmail.com>
>>> ---
>>> ?arch/arm/mach-omap2/iommu2.c ? ? ? ? ? ?| ? 21 +++++++++++++--
>>> ?arch/arm/plat-omap/include/plat/iommu.h | ? 15 ++++++++++-
>>> ?arch/arm/plat-omap/iommu.c ? ? ? ? ? ? ?| ? 41 ++++++++++++++++++++++++++++---
>>> ?3 files changed, 69 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
>>> index 14ee686..504310d 100644
>>> --- a/arch/arm/mach-omap2/iommu2.c
>>> +++ b/arch/arm/mach-omap2/iommu2.c
>>> @@ -143,10 +143,10 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
>>> ? ? ? __iommu_set_twl(obj, false);
>>> ?}
>>>
>>> -static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
>>> +static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra, u32 *iommu_errs)
>>> ?{
>>> ? ? ? int i;
>>> - ? ? u32 stat, da;
>>> + ? ? u32 stat, da, errs;
>>> ? ? ? const char *err_msg[] = {
>>> ? ? ? ? ? ? ? "tlb miss",
>>> ? ? ? ? ? ? ? "translation fault",
>>> @@ -157,8 +157,10 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
>>>
>>> ? ? ? stat = iommu_read_reg(obj, MMU_IRQSTATUS);
>>> ? ? ? stat &= MMU_IRQ_MASK;
>>> - ? ? if (!stat)
>>> + ? ? if (!stat) {
>>> + ? ? ? ? ? ? *iommu_errs = 0;
>>> ? ? ? ? ? ? ? return 0;
>>> + ? ? }
>>>
>>> ? ? ? da = iommu_read_reg(obj, MMU_FAULT_AD);
>>> ? ? ? *ra = da;
>>> @@ -171,6 +173,19 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
>>> ? ? ? }
>>> ? ? ? printk("\n");
>>>
>>> + ? ? errs = 0;
>>> + ? ? if (stat & MMU_IRQ_TLBMISS)
>>> + ? ? ? ? ? ? errs |= OMAP_IOMMU_ERR_TLB_MISS;
>>> + ? ? if (stat & MMU_IRQ_TRANSLATIONFAULT)
>>> + ? ? ? ? ? ? errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
>>> + ? ? if (stat & MMU_IRQ_EMUMISS)
>>> + ? ? ? ? ? ? errs |= OMAP_IOMMU_ERR_EMU_MISS;
>>> + ? ? if (stat & MMU_IRQ_TABLEWALKFAULT)
>>> + ? ? ? ? ? ? errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
>>> + ? ? if (stat & MMU_IRQ_MULTIHITFAULT)
>>> + ? ? ? ? ? ? errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
>>> + ? ? *iommu_errs = errs;
>>> +
>>> ? ? ? iommu_write_reg(obj, stat, MMU_IRQSTATUS);
>>>
>>> ? ? ? return stat;
>>> diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
>>> index 19cbb5e..5a2475f 100644
>>> --- a/arch/arm/plat-omap/include/plat/iommu.h
>>> +++ b/arch/arm/plat-omap/include/plat/iommu.h
>>> @@ -31,6 +31,7 @@ struct iommu {
>>> ? ? ? struct clk ? ? ?*clk;
>>> ? ? ? void __iomem ? ?*regbase;
>>> ? ? ? struct device ? *dev;
>>> + ? ? void ? ? ? ? ? ?*fault_cb_priv;
>>>
>>> ? ? ? unsigned int ? ?refcount;
>>> ? ? ? struct mutex ? ?iommu_lock; ? ? /* global for this whole object */
>>> @@ -48,6 +49,7 @@ struct iommu {
>>> ? ? ? struct mutex ? ? ? ? ? ?mmap_lock; /* protect mmap */
>>>
>>> ? ? ? int (*isr)(struct iommu *obj);
>>> + ? ? void (*fault_cb)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
>>
>> What about making use of (*isr)() for fault call back as well?
>>
>> Basic concept is that, client can decide how to deal with iommu
>> fault. For example, for advanced case, client wants daynamic loading of
>> TLB(or PTE), or for ISP case, clients just want more appropriate fault
>> reporting. This (*isr)() could be used in such flexibility.
>
> In this case, it seems we can re-use it.
>
>>
>> ? 785 ? * ? ? ?Device IOMMU generic operations
>> ? 786 ? */
>> ? 787 ?static irqreturn_t iommu_fault_handler(int irq, void *data)
>> ? 788 ?{
>> ? 789 ? ? ? ? ?u32 stat, da;
>> ? 790 ? ? ? ? ?u32 *iopgd, *iopte;
>> ? 791 ? ? ? ? ?int err = -EIO;
>> ? 792 ? ? ? ? ?struct iommu *obj = data;
>> ? 793
>> ? 794 ? ? ? ? ?if (!obj->refcount)
>> ? 795 ? ? ? ? ? ? ? ? ?return IRQ_NONE;
>> ? 796
>> ? 797 ? ? ? ? ?/* Dynamic loading TLB or PTE */
>> ? 798 ? ? ? ? ?if (obj->isr)
>> ? 799 ? ? ? ? ? ? ? ? ?err = obj->isr(obj);
>> ? 800
>> ? 801 ? ? ? ? ?if (!err)
>> ? 802 ? ? ? ? ? ? ? ? ?return IRQ_HANDLED;
>> ? 803
>> ? 804 ? ? ? ? ?clk_enable(obj->clk);
>> ? 805 ? ? ? ? ?stat = iommu_report_fault(obj, &da);
>> ? 806 ? ? ? ? ?clk_disable(obj->clk);
>> ? 807 ? ? ? ? ?if (!stat)
>> ? 808 ? ? ? ? ? ? ? ? ?return IRQ_HANDLED;
>> ? 809
>> ? 810 ? ? ? ? ?iommu_disable(obj);
>>
>> I guess that this modifying the above code could make (*isr)()
>> flexible to be used for any purpose for clients? For me, having both
>> following may be a bit residual.
>
There are few possible issues in this case. (*isr)() is meant to
replace the generic fault handler on iommu, but the fault callback
isn't. Basically fault callback needs to call specific iommu fault
report to know faulty 'da' and iommu errors, so part of the generic
fault handler must be called.
One possible solution is always call specific fault report before
(*isr)(). IMO it makes sense as (*isr)() might want to know at least
the current faults.
But in this case, specific fault report should not print anything else
as only the upper layer and user will know when a fault is actually an
error or not. So, they're responsible for error messages.
I'm sending a v3 with these changes. Comments will be welcome.
Br,
David
> I agree. We need to add 'void *isr_priv' to iommu struct and the
> function to register isr.
> I'll send a v3 soon.
>
> Regards,
>
> David
>
>>
>>> ? ? ? int (*isr)(struct iommu *obj);
>>> + ? ? void (*fault_cb)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
>>
>
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Will Deacon @ 2011-02-16 16:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikaZkRMHH1bUmO0pWYT1FgTC+83F5KxPySasG-S@mail.gmail.com>
Hi Rabin,
> >> Several of the platforms using the GIC also have GPIO code which uses
> >> set_irq_chained_handler(). I think you will have to modify all of
> >> these to call irq_eoi() appropriately and not the other functions.
> >> Some of these will also likely be used with other interrupt handlers
> >> than the GIC, though.
> >
> > Hmm, I had a quick look at some platforms that do this (mach-dove and
> > plat-spear) and I don't see what the problem is. They use their own irq_chip
> > structures, with their own function pointers, so this doesn't seem to relate
> > to the GIC at all. What am I missing?!
>
> The chained handlers are usually installed on GIC interrupts. So, when
> a chained handler does something like this
>
> desc->irq_data.chip->irq_unmask(&desc->irq_data);
>
> the desc->irq_data.chip refers to the gic_chip. These handlers are
> written with the knowledge of what flow handler the GIC uses and what
> functions it implements, so when you change that, the chained handler
> code will not work correctly, and they'll need to be updated just like
> you've updated the cascade IRQ handler.
Ah yes, thanks for the explanation. After looking at the plat-omap code
I finally understand what's going on and I can't help but feel that the
chained GPIO handlers are terminally broken! The generic irq chip high-level
handlers (handle_{edge,level}_irq for example) at least check to see if
the irq_chip functions are non-NULL before calling them.
Ideally, the chained handler would be able to query the irq_chip to find
out what types of IRQ flow-control it supports and then assume that behaviour.
> In fact, I think that 846afbd1 ("GIC: Dont disable INT in ack callback")
> has broken not just GIC cascading interrupts but assumptions in several
> of these chained handlers, since several of them seem to have been
> written assuming (invalidly) that irq_ack() masks the interrupt, but
> this is no longer the case with the GIC after that commit.
Yep - it was further reaching that I originally thought. The question now is:
is it worth changing all of these handlers or are we better off hacking the gic
code so that .irq_ack calls .irq_eoi? In the case of the latter, your performance
will suck in a virtualised environment, but that's better than broken.
Cheers,
Will
^ permalink raw reply
* [PATCH V3 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support
From: John Linn @ 2011-02-16 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297872716-13353-4-git-send-email-john.linn@xilinx.com>
Minimum infrastructure to add the Xilinx machine and allow it to
be selected in the build.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
No updates for V3
V2 Changes
Updates based on Russell King's comments
Cleanup of the Kconfig
Moved this patch to be last in the patch series
arch/arm/Kconfig | 13 +++++++++++++
arch/arm/Makefile | 1 +
arch/arm/mm/Kconfig | 2 +-
3 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..3317671 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -875,6 +875,17 @@ config PLAT_SPEAR
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
+config ARCH_XILINX
+ bool "Xilinx ARM Cortex A9 Based FPGA"
+ select CPU_V7
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select ARM_GIC
+ select ARM_AMBA
+ help
+ Support for Xilinx ARM Cortex A9 Based FPGA
+
endchoice
#
@@ -1009,6 +1020,8 @@ source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/mach-w90x900/Kconfig"
+source "arch/arm/mach-xilinx/Kconfig"
+
# Definitions to make life easier
config ARCH_ACORN
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1ad..4bad6ef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -197,6 +197,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
machine-$(CONFIG_MACH_SPEAR600) := spear6xx
+machine-$(CONFIG_ARCH_XILINX) := xilinx
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9d30c6f..c8a9f5c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_XILINX
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
--
1.6.2.1
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^ permalink raw reply related
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: John Linn @ 2011-02-16 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297872716-13353-3-git-send-email-john.linn@xilinx.com>
These are the minimum needed to build the kernel for the new platform.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
Updated the constant to use UL in vmalloc.h
V2 Changes
Updates based on Russell King's comments
moved to using entry-macro-gic.S
moved stuff from hardware.h to xilinx_soc.h
added IOMEM() in io.h to help with typing
Minor updates to IO_SPACE_LIMIT and __io()
Updated addresses to be clear with seperate virtual
and physical addresses
arch/arm/mach-xilinx/include/mach/clkdev.h | 33 ++++++++++++++++
arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 +++++++++++++++++
arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 ++++++++++++++
arch/arm/mach-xilinx/include/mach/hardware.h | 18 +++++++++
arch/arm/mach-xilinx/include/mach/io.h | 33 ++++++++++++++++
arch/arm/mach-xilinx/include/mach/irqs.h | 29 ++++++++++++++
arch/arm/mach-xilinx/include/mach/memory.h | 23 +++++++++++
arch/arm/mach-xilinx/include/mach/system.h | 28 +++++++++++++
arch/arm/mach-xilinx/include/mach/timex.h | 24 ++++++++++++
arch/arm/mach-xilinx/include/mach/uart.h | 31 +++++++++++++++
arch/arm/mach-xilinx/include/mach/uncompress.h | 47 +++++++++++++++++++++++
arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 ++++++++++
arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 46 ++++++++++++++++++++++
13 files changed, 398 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h
new file mode 100644
index 0000000..5dd1453
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/clkdev.h
+ *
+ * Copyright (C) 2011 Xilinx, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+struct clk {
+ unsigned long rate;
+};
+
+static inline int __clk_get(struct clk *clk)
+{
+ return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S
new file mode 100644
index 0000000..30d3d3d
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/* arch/arm/mach-xilinx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+
+ .macro addruart, rp, rv
+ ldr \rp, =LL_UART_PADDR @ physical
+ ldr \rv, =LL_UART_VADDR @ virtual
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
+ .endm
+
+ .macro waituart,rd,rx
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
+ tst \rd, #UART_SR_TXFULL @
+ bne 1002b @ wait if FIFO is full
+ .endm
diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S
new file mode 100644
index 0000000..11a2866
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/plat-mxc/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
new file mode 100644
index 0000000..f9685c4
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-xilinx/include/mach/hardware.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_HARDWARE_H__
+#define __MACH_HARDWARE_H__
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h
new file mode 100644
index 0000000..ef69e65
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/io.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-xilinx/include/mach/io.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IO_H__
+#define __MACH_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+
+#define IO_SPACE_LIMIT 0xffff
+
+/* IO address mapping macros, nothing special at this time but required */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) (x)
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h
new file mode 100644
index 0000000..47a8162
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/irqs.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-xilinx/include/mach/irqs.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define ARCH_NR_GPIOS 118
+#define NR_IRQS (128 + ARCH_NR_GPIOS)
+
+/*
+ * GIC Interrupts
+ */
+
+#define IRQ_GIC_SPI_START 32
+#define IRQ_TIMERCOUNTER0 42
+#define IRQ_UART0 59
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h
new file mode 100644
index 0000000..c200486
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/memory.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-xilinx/include/mach/memory.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MEMORY_H__
+#define __MACH_MEMORY_H__
+
+#include <mach/hardware.h>
+
+#define PHYS_OFFSET 0x0
+#define MEM_SIZE SZ_256M
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h
new file mode 100644
index 0000000..e8514a0
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/system.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-xilinx/include/mach/system.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_SYSTEM_H__
+#define __MACH_SYSTEM_H__
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ /* Add architecture specific reset processing here */
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h
new file mode 100644
index 0000000..6765e15
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/timex.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-xilinx/include/mach/timex.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TIMEX_H__
+#define __MACH_TIMEX_H__
+
+#include <mach/hardware.h>
+
+#define PERIPHERAL_CLOCK_RATE 2500000
+
+#define CLOCK_TICK_RATE (PERIPHERAL_CLOCK_RATE / 32)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h
new file mode 100644
index 0000000..20a10d7
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uart.h
@@ -0,0 +1,31 @@
+/* arch/arm/mach-xilinx/include/mach/uart.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UART_H__
+#define __MACH_UART_H__
+
+#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
+#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
+#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
+
+#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
+
+#define UART_FIFO_WRITE(base, value) \
+ (*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) = (value))
+
+#define UART_STATUS(base) \
+ (*(volatile unsigned int *)((base) + UART_SR_OFFSET))
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
new file mode 100644
index 0000000..b7a5110
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/* arch/arm/mach-xilinx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H__
+#define __MACH_UNCOMPRESS_H__
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+
+void arch_decomp_setup(void)
+{
+}
+
+static inline void flush(void)
+{
+ /*
+ * Wait while the FIFO is not empty
+ */
+ while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
+ ;
+}
+
+#define arch_decomp_wdog()
+
+static void putc(char ch)
+{
+ /*
+ * Wait for room in the FIFO, then write the char into the FIFO
+ */
+ while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
+ ;
+
+ UART_FIFO_WRITE(LL_UART_PADDR, ch);
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h
new file mode 100644
index 0000000..aba20a3
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-xilinx/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_VMALLOC_H__
+#define __MACH_VMALLOC_H__
+
+#define VMALLOC_END 0xE0000000UL
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
new file mode 100644
index 0000000..d01cde1
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
@@ -0,0 +1,46 @@
+/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_SOC_H__
+#define __MACH_XILINX_SOC_H__
+
+/* For now, all mappings are flat (physical = virtual)
+ */
+#define UART0_PHYS 0xE0000000
+#define UART0_VIRT UART0_PHYS
+
+#define TTC0_PHYS 0xF8001000
+#define TTC0_VIRT TTC0_PHYS
+
+#define PL310_L2CC_PHYS 0xF8F02000
+#define PL310_L2CC_VIRT PL310_L2CC_PHYS
+
+#define SCU_PERIPH_PHYS 0xF8F00000
+#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
+
+/* The following are intended for the devices that are mapped early */
+
+#define TTC0_BASE IOMEM(TTC0_VIRT)
+#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
+#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
+#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
+#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
+
+/*
+ * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
+ */
+#define LL_UART_PADDR UART0_PHYS
+#define LL_UART_VADDR UART0_VIRT
+
+#endif
--
1.6.2.1
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^ permalink raw reply related
* [PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform
From: John Linn @ 2011-02-16 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297872716-13353-2-git-send-email-john.linn@xilinx.com>
The timer driver supports the Xilinx PS Timer Counter IP.
Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
V2 Changes
The timer code was changed quite a bit based on review inputs. It
got much smaller and cleaner I think.
Updates based on Russell King's comments
minor cleanups for documentation comments
removed the name from the timer structure
removed interrupt for clock source
moved to using clock functions provided in the kernel
for calculating shift/mult values
removed PM code as generic handles it
Updated based on Jamie Iles's comment
cleaned up ENABLE_MASK which was confusing
now using platform_add_devices() from platform code
moved base_addr to void __iomem pointer
removed stop of the event timer in one shot mode
arch/arm/mach-xilinx/Makefile | 2 +-
arch/arm/mach-xilinx/timer.c | 301 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 302 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-xilinx/timer.c
diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
index 76e9e55..660fb19 100644
--- a/arch/arm/mach-xilinx/Makefile
+++ b/arch/arm/mach-xilinx/Makefile
@@ -3,5 +3,5 @@
#
# Common support
-obj-y := common.o
+obj-y := common.o timer.o
obj-$(CONFIG_MACH_XILINX) += board_ep107.o
diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c
new file mode 100644
index 0000000..f08a2f1
--- /dev/null
+++ b/arch/arm/mach-xilinx/timer.c
@@ -0,0 +1,301 @@
+/* arch/arm/mach-xilinx/timer.c
+ *
+ * This file contains driver for the Xilinx PS Timer Counter IP.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/mips/kernel/time.c timer driver
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/xilinx_soc.h>
+
+/*
+ * This driver configures the 2 16-bit count-up timers as follows:
+ *
+ * T1: Timer 1, clocksource for generic timekeeping
+ * T2: Timer 2, clockevent source for hrtimers
+ * T3: Timer 3, <unused>
+ *
+ * The input frequency to the timer module for emulation is 2.5MHz which is
+ * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
+ * the timers are clocked at 78.125KHz (12.8 us resolution).
+ *
+ * The input frequency to the timer module in silicon will be 200MHz. With the
+ * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
+ */
+#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
+#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
+
+#define XTTCPSS_TIMER_BASE TTC0_BASE
+#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
+/*
+ * Timer Register Offset Definitions of Timer 1, Increment base address by 4
+ * and use same offsets for Timer 2
+ */
+#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
+#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
+#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
+#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
+#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
+#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
+#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
+#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
+#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
+
+#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
+
+/**
+ * struct xttcpss_timer - This definition defines local timer structure
+ *
+ * @base_addr: Base address of timer
+ * @timer_irq: irqaction structure for the timer device
+ * @mode: only valid for an clock event, periodic or one-shot
+ **/
+struct xttcpss_timer {
+ void __iomem *base_addr;
+ enum clock_event_mode mode;
+};
+
+static struct xttcpss_timer timers[2];
+static struct clock_event_device xttcpss_clockevent;
+
+/**
+ * xttcpss_set_interval - Set the timer interval value
+ *
+ * @timer: Pointer to the timer instance
+ * @cycles: Timer interval ticks
+ **/
+static void xttcpss_set_interval(struct xttcpss_timer *timer,
+ unsigned long cycles)
+{
+ u32 ctrl_reg;
+
+ /* Disable the counter, set the counter value and re-enable counter */
+ ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+
+ __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+
+ /* Reset the counter (0x10) so that it starts from 0, one-shot
+ mode makes this needed for timing to be right. */
+ ctrl_reg |= 0x10;
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+}
+
+/**
+ * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ *
+ * @irq: IRQ number of the Timer
+ * @dev_id: void pointer to the xttcpss_timer instance
+ *
+ * returns: Always IRQ_HANDLED - success
+ **/
+static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = &xttcpss_clockevent;
+ struct xttcpss_timer *timer = dev_id;
+
+ /* Acknowledge the interrupt and call event handler */
+ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+ timer->base_addr + XTTCPSS_ISR_OFFSET);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction event_timer_irq = {
+ .name = "xttcpss clockevent",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = xttcpss_clock_event_interrupt,
+};
+
+/**
+ * xttcpss_timer_hardware_init - Initialize the timer hardware
+ *
+ * Initialize the hardware to start the clock source, get the clock
+ * event timer ready to use, and hook up the interrupt.
+ **/
+static void __init xttcpss_timer_hardware_init(void)
+{
+ /* Setup the clock source counter to be an incrementing counter
+ * with no interrupt and it rolls over at 0xFFFF. Pre-scale
+ it by 32 also. Let it start running now.
+ */
+ timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
+
+ __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_IER_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+
+ /* Setup the clock event timer to be an interval timer which
+ * is prescaled by 32 using the interval interrupt. Leave it
+ * disabled for now.
+ */
+
+ timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
+
+ __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_IER_OFFSET);
+
+ /* Setup IRQ the clock event timer */
+ event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
+
+ if (event_timer_irq.handler != NULL)
+ setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
+}
+
+/**
+ * __raw_readl_cycles - Reads the timer counter register
+ *
+ * returns: Current timer counter register value
+ **/
+static cycle_t __raw_readl_cycles(struct clocksource *cs)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
+
+ return (cycle_t)__raw_readl(timer->base_addr +
+ XTTCPSS_COUNT_VAL_OFFSET);
+}
+
+
+/*
+ * Instantiate and initialize the clock source structure
+ */
+static struct clocksource clocksource_xttcpss = {
+ .name = "xttcpss_timer1",
+ .rating = 200, /* Reasonable clock source */
+ .read = __raw_readl_cycles,
+ .mask = CLOCKSOURCE_MASK(16),
+ .shift = 0, /* Initialized to zero */
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+/**
+ * xttcpss_set_next_event - Sets the time interval for next event
+ *
+ * @cycles: Timer interval ticks
+ * @evt: Address of clock event instance
+ *
+ * returns: Always 0 - success
+ **/
+static int xttcpss_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+
+ xttcpss_set_interval(timer, cycles);
+ return 0;
+}
+
+/**
+ * xttcpss_set_mode - Sets the mode of timer
+ *
+ * @mode: Mode to be set
+ * @evt: Address of clock event instance
+ **/
+static void xttcpss_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+ u32 ctrl_reg;
+
+ timer->mode = mode;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ }
+}
+
+/*
+ * Instantiate and initialize the clock event structure
+ */
+static struct clock_event_device xttcpss_clockevent = {
+ .name = "xttcpss_timer2",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 0, /* Initialized to zero */
+ .set_next_event = xttcpss_set_next_event,
+ .set_mode = xttcpss_set_mode,
+ .rating = 200,
+};
+
+/**
+ * xttcpss_timer_init - Initialize the timer
+ *
+ * Initializes the timer hardware and register the clock source and clock event
+ * timers with Linux kernal timer framework
+ **/
+static void __init xttcpss_timer_init(void)
+{
+ xttcpss_timer_hardware_init();
+ clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
+
+ /* Calculate the parameters to allow the clockevent to operate using
+ integer math
+ */
+ clockevents_calc_mult_shift(&xttcpss_clockevent, CLOCK_TICK_RATE, 4);
+
+ xttcpss_clockevent.max_delta_ns =
+ clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
+ xttcpss_clockevent.min_delta_ns =
+ clockevent_delta2ns(1, &xttcpss_clockevent);
+
+ /* Indicate that clock event can be used on any of the CPUs */
+
+ xttcpss_clockevent.cpumask = cpu_all_mask;
+ clockevents_register_device(&xttcpss_clockevent);
+}
+
+/*
+ * Instantiate and initialize the system timer structure
+ */
+struct sys_timer xttcpss_sys_timer = {
+ .init = xttcpss_timer_init,
+};
--
1.6.2.1
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply related
* [PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support
From: John Linn @ 2011-02-16 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297872716-13353-1-git-send-email-john.linn@xilinx.com>
The 1st board support is minimal to get a system up and running
on the Xilinx platform.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
Changed the name of functions to include "xilinx" in
common.c and common.h
Changed the Kconfig and Makefile to use MACH_XILINX which
matches the machine registered.
V2 Changes
Updates based on Russell King's comments
minor cleanups
cleaned up physical/virtual addresses in early i/o table
Updated based on Jamie Iles's comment
added clk_get_rate() function
now using platform_add_devices() from platform code
arch/arm/mach-xilinx/Kconfig | 14 +++++
arch/arm/mach-xilinx/Makefile | 7 ++
arch/arm/mach-xilinx/Makefile.boot | 3 +
arch/arm/mach-xilinx/board_ep107.c | 82 ++++++++++++++++++++++++++
arch/arm/mach-xilinx/common.c | 113 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-xilinx/common.h | 30 ++++++++++
6 files changed, 249 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-xilinx/Kconfig
create mode 100644 arch/arm/mach-xilinx/Makefile
create mode 100644 arch/arm/mach-xilinx/Makefile.boot
create mode 100644 arch/arm/mach-xilinx/board_ep107.c
create mode 100644 arch/arm/mach-xilinx/common.c
create mode 100644 arch/arm/mach-xilinx/common.h
diff --git a/arch/arm/mach-xilinx/Kconfig b/arch/arm/mach-xilinx/Kconfig
new file mode 100644
index 0000000..61532af
--- /dev/null
+++ b/arch/arm/mach-xilinx/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_XILINX
+
+choice
+ prompt "Board Selection"
+ default MACH_XILINX
+
+config MACH_XILINX
+ bool "Xilinx EP107 Board"
+ help
+ Select if you are using a Xilinx EP107 board.
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
new file mode 100644
index 0000000..76e9e55
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o
+obj-$(CONFIG_MACH_XILINX) += board_ep107.o
diff --git a/arch/arm/mach-xilinx/Makefile.boot b/arch/arm/mach-xilinx/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-xilinx/board_ep107.c b/arch/arm/mach-xilinx/board_ep107.c
new file mode 100644
index 0000000..a1635b5
--- /dev/null
+++ b/arch/arm/mach-xilinx/board_ep107.c
@@ -0,0 +1,82 @@
+/* arch/arm/mach-xilinx/board_ep107.c
+ *
+ * This file contains code specific to the Xilinx EP107 board.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on /arch/arm/mach-realview/core.c
+ *
+ * Copyright (C) 1999 - 2003 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/xilinx_soc.h>
+#include <mach/irqs.h>
+#include <linux/clkdev.h>
+#include "common.h"
+
+/*
+ * Fixed clocks for now
+ */
+
+static struct clk ref50_clk = {
+ .rate = 50000000,
+};
+
+/* Create all the platform devices for the board */
+
+static struct resource uart0[] = {
+ {
+ .start = UART0_PHYS,
+ .end = UART0_PHYS + 0xFFF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_UART0,
+ .end = IRQ_UART0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device uart_device0 = {
+ .name = "xuartpss",
+ .id = 0,
+ .dev = {
+ .platform_data = &ref50_clk.rate,
+ },
+ .resource = uart0,
+ .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct platform_device *xilinx_pdevices[] __initdata = {
+ &uart_device0,
+};
+
+/**
+ * board_ep107_init - Board specific initialization for the Xilinx EP107 board.
+ *
+ **/
+static void __init board_ep107_init(void)
+{
+ xilinx_system_init();
+ platform_add_devices(&xilinx_pdevices[0], ARRAY_SIZE(xilinx_pdevices));
+}
+
+MACHINE_START(XILINX_EP107, "Xilinx EP107")
+ .boot_params = PHYS_OFFSET + 0x00000100,
+ .map_io = xilinx_map_io,
+ .init_irq = xilinx_irq_init,
+ .init_machine = board_ep107_init,
+ .timer = &xttcpss_sys_timer,
+MACHINE_END
diff --git a/arch/arm/mach-xilinx/common.c b/arch/arm/mach-xilinx/common.c
new file mode 100644
index 0000000..564b707
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.c
@@ -0,0 +1,113 @@
+/* arch/arm/mach-xilinx/common.c
+ *
+ * This file contains common code that is intended to be used across
+ * boards so that it's not replicated.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/mach/map.h>
+#include <asm/page.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/xilinx_soc.h>
+#include <mach/clkdev.h>
+
+/*
+ * Clock function infrastructure.
+ */
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+/**
+ * system_init - System specific initialization, intended to be called from
+ * board specific initialization.
+ *
+ **/
+void __init xilinx_system_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 64KB way size, 8-way associativity, parity disabled
+ */
+ l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
+#endif
+}
+
+/**
+ * irq_init - Interrupt controller initialization for the GIC.
+ *
+ **/
+void __init xilinx_irq_init(void)
+{
+ gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
+}
+
+/* The minimum devices needed to be mapped before the VM system is up and
+ * running include the GIC, UART and Timer Counter.
+ */
+
+static struct map_desc io_desc[] __initdata = {
+ {
+ .virtual = TTC0_VIRT,
+ .pfn = __phys_to_pfn(TTC0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = SCU_PERIPH_VIRT,
+ .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = PL310_L2CC_VIRT,
+ .pfn = __phys_to_pfn(PL310_L2CC_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+
+#ifdef CONFIG_DEBUG_LL
+ {
+ .virtual = UART0_VIRT,
+ .pfn = __phys_to_pfn(UART0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
+
+};
+
+/**
+ * map_io - Create memory mappings needed for early I/O.
+ *
+ **/
+void __init xilinx_map_io(void)
+{
+ iotable_init(io_desc, ARRAY_SIZE(io_desc));
+}
diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h
new file mode 100644
index 0000000..9a7cf65
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-xilinx/common.h
+ *
+ * This file contains common function prototypes to avoid externs
+ * in the c files.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_COMMON_H__
+#define __MACH_XILINX_COMMON_H__
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+void __init xilinx_system_init(void);
+void __init xilinx_irq_init(void);
+void __init xilinx_map_io(void);
+
+extern struct sys_timer xttcpss_sys_timer;
+
+#endif
--
1.6.2.1
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply related
* [PATCH V3 0/4] ARM: Basic Xilinx Support
From: John Linn @ 2011-02-16 16:11 UTC (permalink / raw)
To: linux-arm-kernel
V3
I incorporated more feedback from Russell King.
Primarily clean up of the license header to remove
the address.
Also minor cleanup of the Kconfig and Makefile for the board
to match the MACH_XILINX entry in the machine ID database.
These changes were tested on 2.6.38-rc4 and rc5.
V2
I incorporated review comments from Russell King and Jamie Iles.
Each patch has V2 comments describing the details. The order of
each patch in the series did change.
Thanks a lot to them for the detailed review as this patch set
is much cleaner and improved (I think anyway).
Thanks for comments from Arnd and Grant also.
This was tested against 2.6.38-rc4.
----
This patch series adds very basic support for the Xilinx ARM platform.
The entire patch set must be used, I only broke it up into logical
pieces to make the review easier (I hope).
I would like to get the review feedback and make any changes, but after
that I need to change mach-xilinx to the real product name. The real
product name is expected to be released by marketing very soon.
There's always the option of keeping mach-xilinx and then only
documenting the product name in the Kconfig. I'm less in favor of that
but it could be ok.
This code has been tested against 2.6.38-rc2, r3, and against head. The
only checkpatch warnings are about volatile in the uncompress.h file
and this method I used seems normal.
Thanks,
John
arch/arm/Kconfig | 13 +
arch/arm/Makefile | 1
arch/arm/mach-xilinx/Kconfig | 14 +
arch/arm/mach-xilinx/Makefile | 9
arch/arm/mach-xilinx/Makefile.boot | 3
arch/arm/mach-xilinx/board_ep107.c | 82 ++++++
arch/arm/mach-xilinx/common.c | 113 ++++++++
arch/arm/mach-xilinx/common.h | 31 ++
arch/arm/mach-xilinx/include/mach/clkdev.h | 33 ++
arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++
arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 ++
arch/arm/mach-xilinx/include/mach/hardware.h | 18 +
arch/arm/mach-xilinx/include/mach/io.h | 33 ++
arch/arm/mach-xilinx/include/mach/irqs.h | 29 ++
arch/arm/mach-xilinx/include/mach/memory.h | 23 +
arch/arm/mach-xilinx/include/mach/system.h | 28 ++
arch/arm/mach-xilinx/include/mach/timex.h | 24 +
arch/arm/mach-xilinx/include/mach/uart.h | 31 ++
arch/arm/mach-xilinx/include/mach/uncompress.h | 47 +++
arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +
arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 47 +++
arch/arm/mach-xilinx/timer.c | 302 +++++++++++++++++++++++-
arch/arm/mm/Kconfig | 3
23 files changed, 964 insertions(+), 6 deletions(-)
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^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Arnd Bergmann @ 2011-02-16 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216202818.GA11467@S2100-06.ap.freescale.net>
On Wednesday 16 February 2011, Shawn Guo wrote:
> It's caused by spinlock recursion introduced by mxs-dma functions
> mxs_dma_tx_submit and mxs_dma_tasklet. We have mmc_request_done
> invoked in the dma callback tasklet. At the meantime,
> mmc_request_done will issue retries in some case, which will call in
> mxs_dma_tx_submit.
>
> I added the lock by referring to other dma driver implementation, but
> now I'm considering to remove the lock completely, as I do not see
> any global data needs to be protected there. Comments?
You need to be sure that the data accessed in the tasklet does not
need to be locked against mxs_dma_tx_submit.
I haven't looked at the dmaengine code for this, but it's quite likely
that you actually need it, because you need to serialize adding an
element to the DMA device with removing it again.
Also, since the lock is taken in a tasklet, every thread that takes
it outside of a tasklet must do spin_lock_bh(), not spin_lock(), to
prevent the tasklet from running.
Arnd
^ permalink raw reply
* [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
From: Santosh Shilimkar @ 2011-02-16 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikEjTgisftQV46djrOP8iWMFV267v-efHsVf_Nd@mail.gmail.com>
> -----Original Message-----
> From: catalin.marinas at gmail.com [mailto:catalin.marinas at gmail.com]
> On Behalf Of Catalin Marinas
> Sent: Wednesday, February 16, 2011 9:24 PM
> To: Santosh Shilimkar
> Cc: linux-arm-kernel at lists.infradead.org; Andrei Warkentin; Kevin
> Hilman; tony at atomide.com; linux-omap at vger.kernel.org
> Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
> operation can cause data corruption
>
> On 15 February 2011 07:14, Santosh Shilimkar
> <santosh.shilimkar@ti.com> wrote:
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
> >
> > ?config PL310_ERRATA_588369
> > ? ? ? ?bool "Clean & Invalidate maintenance operations do not
> invalidate
> > clean lines"
> > - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> > + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
>
> It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
>
Ok.
> > +config PL310_ERRATA_727915
> > + ? ? ? bool "Background Clean & Invalidate by Way operation can
> cause
> > data corruption"
> > + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
>
> Same here.
>
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -45,7 +45,10 @@ config ARCH_OMAP4
> > ? ? ? ?select CPU_V7
> > ? ? ? ?select ARM_GIC
> > ? ? ? ?select LOCAL_TIMERS
> > + ? ? ? select CACHE_L2X0
>
> CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
> there or just change the other platforms to select a
> HAVE_CACHE_L2X0.
> Ideally we would like this option to be selectable in config just in
> case you want to debug some issues.
>
I will add ARCH_OMAP4 under CACHE_L2X0.
> > --- a/arch/arm/mach-omap2/omap4-common.c
> > +++ b/arch/arm/mach-omap2/omap4-common.c
> > @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> > ? ? ? ?omap_smc1(0x102, 0x0);
> > ?}
> >
> > +static void omap4_l2x0_set_debug(unsigned long val)
> > +{
> > + ? ? ? /* Program PL310 L2 Cache controller debug register */
> > + ? ? ? omap_smc1(0x100, val);
> > +}
>
> This part together with the Kconfig changes for OMAP4 could be a
> separate patch, OMAP-specific.
>
Agree. I will split this patch and repost.
> The rest seems fine.
Thanks for the feedback.
Regards,
Santosh
^ permalink raw reply
* [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
From: Catalin Marinas @ 2011-02-16 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4dfaffa99292bf8e36791ea9a68de75e@mail.gmail.com>
On 15 February 2011 07:14, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote:
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
>
> ?config PL310_ERRATA_588369
> ? ? ? ?bool "Clean & Invalidate maintenance operations do not invalidate
> clean lines"
> - ? ? ? depends on CACHE_L2X0 && ARCH_OMAP4
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
It can just depend on CACHE_PL310 as this depends on CACHE_L2X0.
> +config PL310_ERRATA_727915
> + ? ? ? bool "Background Clean & Invalidate by Way operation can cause
> data corruption"
> + ? ? ? depends on CACHE_L2X0 && CACHE_PL310
Same here.
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -45,7 +45,10 @@ config ARCH_OMAP4
> ? ? ? ?select CPU_V7
> ? ? ? ?select ARM_GIC
> ? ? ? ?select LOCAL_TIMERS
> + ? ? ? select CACHE_L2X0
CACHE_L2X0 has a long dependency list. You could add ARCH_OMAP4 in
there or just change the other platforms to select a HAVE_CACHE_L2X0.
Ideally we would like this option to be selectable in config just in
case you want to debug some issues.
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void)
> ? ? ? ?omap_smc1(0x102, 0x0);
> ?}
>
> +static void omap4_l2x0_set_debug(unsigned long val)
> +{
> + ? ? ? /* Program PL310 L2 Cache controller debug register */
> + ? ? ? omap_smc1(0x100, val);
> +}
This part together with the Kconfig changes for OMAP4 could be a
separate patch, OMAP-specific.
The rest seems fine.
--
Catalin
^ permalink raw reply
* [PATCH v2 1/7] mmc: mxs-mmc: add mmc host driver for i.MX23/28
From: Wolfram Sang @ 2011-02-16 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216202818.GA11467@S2100-06.ap.freescale.net>
Hi Shawn,
[CRC failures on MMC]
> I guess you will also get the unknown partition table message if you
> test this card on mx35 right now.
No, I didn't see that message on MX35. (Doesn't matter much now).
> I just tested 7 mmc cards in total. 6 cards work fine, and 1 card
> (Transcend MMC plus 1GB) has the exactly same problem as yours. And
> if I remove the 8 bit cap, this card also works fine. So I would
> agree with Russell that it's unrelated to the driver.
Ah, the 8_BIT_CAP was the right pointer. It works now and I can see the
partitions \o/ But IMHO it is related to the driver because it cannot set that
8_BIT_DATA_CAP unconditionally? Probably something like 'flags' should be added
to platform_data? One flag could then be 8_BIT_CAPABLE_SLOT or something.
> I tested the SDIO, but probably in different way from yours. I had
> two card slots on my board, rootfs on mmc0 and SDIO card on mmc1.
> It seems working fine in this way. However, when I use nfs and test
> SDIO on mmc0, my systems hangs too. I will look into it.
The latter scenario is the only one I can test, because I don't have an
(active) second slot.
Thanks for keeping up with the driver!
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* newbie question: location of frame buffer driver for imx27
From: Fabio Estevam @ 2011-02-16 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5B91BA.9090306@televic.com>
Hi J?rgen,
2011/2/16 J?rgen Lambrecht <J.Lambrecht@televic.com>:
> Hello,
>
> we have the Freescale IMX27-PDK demo kit. Along with it, we got the source
> code for the linux kernel version 2.6.22, and a lot of patches.
> Also for the video part, there are a lot of patches, creating a
> /drivers/video/mxc subdirectory.
> In the linux sources 2.6.37, I only find 2 files: mx3fb.c (imx3x i guess)
> and imxfb.c.
> When we try to compile linux for the imx27 (with the latest ltib) there are
> no framebuffers under devices.
>
> Do I still need to patch linux/drivers/video for the imx27, or should it
> work fine like it is?
> (and if so, what do I do wrong ;-)
Framebuffer support for MX27 is available at: drivers/video/imxfb.c
You can also take a look at arch/arm/mach-imx/mach-mx27ads.c to see an
example of a MX27 based board with framebuffer support.
Regards,
Fabio Estevam
^ permalink raw reply
* [PATCH] i.MX23/28 framebuffer driver
From: Jesse Barker @ 2011-02-16 14:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201102161322.08126.arnd@arndb.de>
Speaking for the Linaro graphics working group, I think it's great. And, I
think you're right, that if enough of the KMS support in xf86-video-* is
similar enough (I was only aware of intel and nouveau supporting it properly
at current), pulling it out into a common layer would make it easier to
support in new drivers (including fbdev).
cheers,
Jesse
On Wed, Feb 16, 2011 at 4:22 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 15 February 2011, Clark, Rob wrote:
> > I'd been experimenting a bit on the side w/ the DRM driver framework (
> >
> http://gitorious.com/~robclark/pandaboard/robclarks-kernel-omap4/commits/omap_gpu
> > ), but had to add a good chunk of mostly boilerplate code to our xorg
> > driver in order just to test it. Maybe some generic support for KMS
> > in xf86-video-fbdev would have made this easier to develop the kernel
> > part without in parallel having to implement the userspace part. I'm
> > not sure if this is the sort of thing the linaro-wg has in mind?
>
> I'm not sure what the the linaro multimedia wg thinks of this, but the
> kernel code you linked looks like it's doing exactly the right thing.
>
> Arnd
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev
>
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* ep93xx: IP-Config: Failed to open eth0
From: 余谨智 @ 2011-02-16 14:40 UTC (permalink / raw)
To: linux-arm-kernel
Hi, everyone. I am a newbie here. I come from China.
I have a board based on ep9315. I am trying to port embeded linux to that board.
I used 'make zImage' to generate a zImage, and u-boot command 'dhcp' to download zImage into board sdram at address 0x1000000, then 'go 0x1000000'. Thank God! The kernel ran!
But I get this message in my minicom:
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37 (root at myhost) (gcc version 4.1.2) #4 Wed Feb 16 20:23:04 CST 2011
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
CPU: VIVT data cache, VIVT instruction cache
Machine: Cirrus Logic EDB9315 Evaluation Board
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4064
Kernel command line: console=ttyAM0,115200 root=/dev/nfs ip=dhcp
PID hash table entries: 64 (order: -4, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Memory: 16MB = 16MB total
Memory: 12584k/12584k available, 3800k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
vmalloc : 0xc1800000 - 0xfe800000 ( 976 MB)
lowmem : 0xc0000000 - 0xc1000000 ( 16 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.init : 0xc0008000 - 0xc0023000 ( 108 kB)
.text : 0xc0023000 - 0xc0352090 (3261 kB)
.data : 0xc0354000 - 0xc0374400 ( 129 kB)
NR_IRQS:120
VIC @fefb0000: id 0x00041190, vendor 0x41
VIC @fefc0000: id 0x00041190, vendor 0x41
Calibrating delay loop... 99.73 BogoMIPS (lpj=498688)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
NET: Registered protocol family 16
ep93xx clock: PLL1 running at 199 MHz, PLL2 at 192 MHz
ep93xx clock: FCLK 199 MHz, HCLK 99 MHz, PCLK 49 MHz
ep93xx dma_m2p: M2P DMA subsystem initialized
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: 1, 10240 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
UDP hash table entries: 128 (order: 0, 6144 bytes)
UDP-Lite hash table entries: 128 (order: 0, 6144 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (extended precision)
JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
msgmni has been set to 24
io scheduler noop registered
io scheduler deadline registered (default)
Serial: AMBA driver
apb:uart1: ttyAM0 at MMIO 0x808c0000 (irq = 52) is a AMBA
console [ttyAM0] enabled
apb:uart2: ttyAM1 at MMIO 0x808d0000 (irq = 54) is a AMBA
apb:uart3: ttyAM2 at MMIO 0x808e0000 (irq = 55) is a AMBA
nbd: registered device at major 43
physmap platform flash device: 02000000 at 60000000
physmap-flash.0: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000089 Chip ID 0x000018
Intel/Sharp Extended Query Table at 0x0031
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
Searching for RedBoot partition table in physmap-flash.0 at offset 0x1fc0000
No RedBoot partition table detected in physmap-flash.0
ep93xx-eth version 0.1 loading
eth0: ep93xx on-chip ethernet, IRQ 39, 01:02:93:12:15:07
rtl8150: v0.6.2 (2004/08/27):rtl8150 based usb-ethernet driver
usbcore: registered new interface driver rtl8150
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ep93xx-ohci ep93xx-ohci: EP93xx OHCI
ep93xx-ohci ep93xx-ohci: new USB bus registered, assigned bus number 1
ep93xx-ohci ep93xx-ohci: irq 56, io mem 0x80020000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EP93xx OHCI
usb usb1: Manufacturer: Linux 2.6.37 ohci_hcd
usb usb1: SerialNumber: ep93xx
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 3 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver usbserial
usbserial: USB Serial Driver core
USB Serial support registered for pl2303
usbcore: registered new interface driver pl2303
pl2303: Prolific PL2303 USB to serial adaptor driver
ep93xx-rtc ep93xx-rtc: rtc core: registered ep93xx-rtc as rtc0
i2c /dev entries driver
ep93xx_wdt: EP93XX watchdog, driver version 0.3
TCP cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
NET: Registered protocol family 15
ep93xx-rtc ep93xx-rtc: setting system clock to 1970-01-01 00:57:09 UTC (3429)
IP-Config: Failed to open eth0
IP-Config: No network devices available.
Root-NFS: no NFS server address
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "nfs" or unknown-block(2,0)
Please append a correct "root=" boot option; here are the available partitions:
1f00 32768 mtdblock0 (driver?)
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)
After analyzing, I think the main problem is IP-Config: Failed to open eth0, so that the kernel can not mount the nfs root.
Is there some problem in the network driver ep93xx-eth or in some code generate "IP-Config: Failed to open eth"
Any reply will be appreciated!
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* [PATCH 7/7] ARM i.MX51 babbage: Add framebuffer support
From: Sascha Hauer @ 2011-02-16 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297865452-32181-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-mx5/Kconfig | 1 +
arch/arm/mach-mx5/board-mx51_babbage.c | 74 ++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992f..89e71da 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -42,6 +42,7 @@ config MACH_MX51_BABBAGE
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
+ select IMX_HAVE_PLATFORM_IMX_IPUV3
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e8..c5170e8 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -22,11 +22,13 @@
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
+#include <linux/mfd/imx-ipu-v3.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
+#include <mach/ipu-v3.h>
#include <asm/irq.h>
#include <asm/setup.h>
@@ -158,6 +160,41 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
+
+ /* Display */
+ MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
+ MX51_PAD_NANDF_D12__GPIO3_28,
+
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0,
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1,
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2,
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3,
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4,
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5,
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6,
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7,
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8,
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9,
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10,
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11,
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12,
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13,
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14,
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15,
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16,
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17,
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18,
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19,
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20,
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21,
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22,
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23,
+#define MX51_PAD_DI_GP4__IPU_DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0, 0, NO_PAD_CTRL)
+ MX51_PAD_DI_GP4__IPU_DI2_PIN15,
+
+ /* I2C DVI enable */
+ MX51_PAD_CSI2_HSYNC__GPIO4_14,
};
/* Serial ports */
@@ -346,6 +383,23 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};
+static struct ipuv3_fb_platform_data babbage_fb0_data = {
+ .interface_pix_fmt = IPU_PIX_FMT_RGB24,
+ .flags = IMX_IPU_FB_USE_MODEDB | IMX_IPU_FB_USE_OVERLAY,
+ .display = 0,
+};
+
+static struct ipuv3_fb_platform_data babbage_fb1_data = {
+ .interface_pix_fmt = IPU_PIX_FMT_RGB565,
+ .flags = IMX_IPU_FB_USE_MODEDB,
+ .display = 1,
+};
+
+static struct imx_ipuv3_platform_data ipu_data = {
+ .fb_head0_platform_data = &babbage_fb0_data,
+ .fb_head1_platform_data = &babbage_fb1_data,
+};
+
/*
* Board specific initialization.
*/
@@ -392,6 +446,26 @@ static void __init mxc_board_init(void)
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
imx51_add_imx2_wdt(0, NULL);
+
+#define GPIO_DVI_DETECT (2 * 32 + 28)
+#define GPIO_DVI_RESET (2 * 32 + 5)
+#define GPIO_DVI_PWRDN (2 * 32 + 6)
+#define GPIO_DVI_I2C (3 * 32 + 14)
+
+ /* DVI Detect */
+ gpio_request(GPIO_DVI_DETECT, "dvi detect");
+ gpio_direction_input(GPIO_DVI_DETECT);
+ /* DVI Reset - Assert for i2c disabled mode */
+ gpio_request(GPIO_DVI_RESET, "dvi reset");
+ gpio_direction_output(GPIO_DVI_RESET, 0);
+ /* DVI Power-down */
+ gpio_request(GPIO_DVI_PWRDN, "dvi pwdn");
+ gpio_direction_output(GPIO_DVI_PWRDN, 1);
+
+ gpio_request(GPIO_DVI_I2C, "dvi i2c");
+ gpio_direction_output(GPIO_DVI_I2C, 0);
+
+ imx51_add_ipuv3(&ipu_data);
}
static void __init mx51_babbage_timer_init(void)
--
1.7.2.3
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